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Semiconductor Memories
Prof. MacDonald
Types of Memories!l Volatile Memories
– require power supply to retain information
– dynamic memories l use charge to store information and require refreshing
– static memories l use feedback (latch) to store information – no refresh required
l Non-Volatile Memories – ROM (Mask) – EEPROM – FLASH – NAND or NOR – MRAM
Memory Hierarchy!
RF 100pS 100’s of bytes L1 SRAM 1nS 10’s of Kbytes
L2 SRAM 10nS 100’s of Kbytes
L3 DRAM 100nS 100’s of
Mbytes
Disks / Flash 1us Gbytes
Memory Hierarchy!l Large memories are slow
l Fast memories are small
l Memory hierarchy gives us illusion of large memory space with speed of small memory.
– temporal locality
– spatial locality
Register Files !l Fastest and most robust memory array
l Largest bit cell size
l Basically an array of large latches
l No sense amps – bits provide full rail data out
l Often multi-ported (i.e. 8 read ports, 2 write ports)
l Often used with ALUs in the CPU as source/destination
l Typically less than 10,000 bits – 32 32-bit fixed point registers
– 32 60-bit floating point registers
SRAM!l Same process as logic so often combined on one die
l Smaller bit cell than register file – more dense but slower
l Uses sense amp to detect small bit cell output
l Fastest for reads and writes after register file
l Large per bit area costs – six transistors (single port), eight transistors (dual port)
l L1 and L2 Cache on CPU is always SRAM
l On-chip Buffers – (Ethernet buffer, LCD buffer)
l Typical sizes 16k by 32
Static Memory Cell!
T1!
True!Bit!Line!
Complement!Bit!Line!
Wordline!
T2!
T5!
T3!
T6!
T4!
Example Chip!
SRAM cache
LCD Frame Buffer SRAM
Register file
SRAM Interface !!l Dirt simple
– clk – only required if registered inputs and/or outputs
– csn – usually negatively active chip select
– wen – usually negatively active write enable
– a – address bus – logarithmically related to number of locations
– d – data in bus – inputs used during writes
– q – data out bus – outputs used during reads
l read – csn active / wen inactive – data in the byte located by A bus launches out Q bus
l write – csn active / wen active – D bus value is loaded into memory location determined by A
SRAM Operation !!
Dual Port SRAM Operation !!l Two complete single port interfaces
– can read two locations simultaneously
– can write two different locations simultaneously
– can not write one location with two different ports
– Typically requires 2 additional transistors per bit l (6 to 8 for 33% increase)
– Typically requires 4 bit lines and 2 word lines l double the global routing than single port
Dual Port SRAM Interface !!l Two merged SRAM interfaces
– clk – if registered inputs and/or outputs
– csnA / csnB – usually negatively active chip select
– wenA / wenB – usually negatively active write enable
– aA / aB – address bus – logarithmically related to number of locations
– dA / dB – data in bus – inputs used during writes
– qA / aB – data out bus – outputs used during reads
Two Port Memory Cell!
T1!True!Bit!Line !Port 0!
Complement!Bit!Line !Port 0!
Word Line!Port 0!
T3!
T5!
T2!
T6!
T4!True!Bit!Line !Port 1!
Complement!Bit!
Line !Port 1!
Word!Line !Port 1!
T7! T8!
Memory Compilers!l ASIC library providers give logic designers:
– Standard cells - ANDs, NANDs, FLIP-FLOPs, etc
– Chip IOs
– Memory compilers l single port SRAM,
l dual port SRAM, and
l register files.
l Dial in size and generates verilog, layout, timing.
l DRAM, FLASH not supported
Motherboard architecture
Dynamic RAM!l Most dense RAM (1 Gbit chips available)
l Historically, different semiconductor process so built on a separate die
l L3 Cache (old days) and computer main memory
l Requires refresh of data due to leakage
l New push to combine DRAM and logic – embedded DRAM, eDRAM
– business case hard to close – yields drop
DRAM Bit Cells (1T)
Cbl Cb
wordline
bitline
DRAM used since the early 70s Destructive Read Highest density
DRAM Bit Cells (3T)
write wordline
read bitline
DRAM used in the early 70s Non-destructive read
write bitline
read wordline
DRAM Cross Section
DRAM Array
DRAM Interface Evolution!l Asynch DRAM – up until early 90’s
l Synch DRAM – add a clock
l Double Data Rate (DDR) SDRAM
l DDR2 SDRAM – Faster
l Others – RAMBUS – Intel supported – dead except for PS3
– graphics versions – specifically for frame buffers
– Mobile SDRAM – low power, good for palm pilots
DRAM Read Timings
RA1 CA1 RA CA
RAS
CAS
Addr
data 1 Addr data 2
DRAM Read Timings (EDO)
RA1 CA1 CA
RAS
CAS
Addr
data 1 Addr data 2
SDRAM
l Same array as Asynch DRAM
l Add pipelining to data to increase bandwidth
l Requires new clock signal
l Treats RAS, CAS, WE as command inputs
l Replaced by DDR for high performance apps
l Still alive for mobile applications due to power
SDRAM Block
SDRAM Commands
Maskable ROM!l Most dense ROM
l Tie bit high or low at mask level (metallization)
l Mistakes take weeks to fix with new silicon – hold lots at metal layer for quick implementation
SDRAM Timings
command is just the value of CSN, CAS, RAS and WEN together in that cycle
address is usually 9-11 bits plus 2 bits for bank address
ROM/EEPROM/FLASH!l Metal Mask ROM
l Electrically erasable programmable ROM
l FLASH is block erasable only EEPROM
l EEPROM can be byte-written but requires extra transistor
l FLASH may take over the world – replacing disk drives with FLASH drives (no moving parts – more reliable).
l Motorola is leader in combining FLASH with logic
l Intel leader in NOR Flash
l Toshiba / Samsung leaders in NAND Flash
EPROM!l Erasable Programmable ROM
l Can be erased by UV light
l Programmed by Hot Carrier Injection
l Obsolete but still mentioned – only used in EE2369 to provide historical perspective
NOR ROM Structure!
NOR ROM Structure!
NAND ROM Structure!
Flash Cross Section!
FLASH!
FLASH!l NOR Flash
– less dense (256 Mbit) but provides fast random read access – Erase FN / Program HEI – 100,000 write cycles – Slow erase, fast program and read – SRAM like interface – give an address – get a byte of data – great for code memory ( bios, boot-up, cell phone, etc)
l NAND Flash – More than 2X denser – up to 2Gbit – Erase FN/ Program FN – Fast erase, slow program and read – 1,000,000 write cycles – IO like interface – not as simple as NOR – good for data storage – memory cards, IPODs, USB keydrives
Flash Cross Section!
NOR FLASH!
NAND Flash Reading!
Tunneling vs Injection!
Charge Pumps!l Flash and EEPROM architectures need
unavailable higher voltage for programming (+10v)
l Charge pumps can pump a cap to get high voltage
l DC to DC (higher) converter - without inductors
l Need to consider Vmax across any gate oxide
l Generally cannot provide much power (I*V)
l Charge pumps used for a lot of other things like overdrive voltages and PLLs
Basic charge pump concept!
Staged Diode Charge Pump!
Dickson Charge Pump!
Vin
C out C C C C
V out
φ
φ
M d1
M d2
M d3
M d4
M d15
V 1 V 2 V3 V 4
Improved versions!
Vin
C f
CC
V out
_1
_2
M D1 M D2 M D3 M D4 M Do
V 1 V 2 V3 V 4
C
M s1 M s2 M s3 M s4 M D5
C C M N1
M N2 M N3 M N4 M P1
M P2 M P3 M P4
_1
_2
VDD
Stage 1 Stage 2
N1 N2 N3 N4
P1
P2
P3
P4
C1
C2
C3
C4
Cout
P7
P8
Clock booster!
Outb Out
Vo Vob
N1 N1b
N2 N2b
P1 P2
C1b
C1
4 Phase Charge Pump!
Vin
C2 C1
M 0
M1
C3
M3
Clk1 Clk1
Clk2 Clk4
Clk3
M2
M4
Cb1 Cb2
M n
V out
CAMs!l SRAM structure that will do a parallel compare against
the contents to provide a hit signal for each row (value)
l Used by caches to find if data is in cache
l Also used for translation look-aside buffers
l Also used in switches / routers to check destination address in ethernet against list of addresses
l Ternary CAMs allow for bit masking the compare
Encoders / Decoders
3 to 8 line decode
input 0 1 2 3 4 5 6 7 000 1 0 0 0 0 0 0 0 001 0 1 0 0 0 0 0 0 010 0 0 1 0 0 0 0 0 011 0 0 0 1 0 0 0 0 100 0 0 0 0 1 0 0 0 101 0 0 0 0 0 1 0 0 110 0 0 0 0 0 0 1 0 111 0 0 0 0 0 0 0 1
Encoder Decoder
Read Only Memories - ROM
Address Data Out 1 2 2 3 4 5 6 7
000 1 0 1 0 1 0 0 0 001 0 1 0 0 0 0 0 1 010 0 0 1 0 0 1 0 0 011 0 0 1 1 0 0 0 0 100 0 0 1 0 0 0 1 1 101 1 1 1 0 0 1 1 1 110 1 1 0 0 0 0 1 0 111 1 1 1 1 0 0 0 1
n
m
ROM
2n addresses addressed by n bit m output data bits
Read Only Memories - ROM
n
m
Memory array n to 2n decoder
2n
Address input word lines
data output
ROM memory array
pd pd pd pd pd pd pd pd pd pd word line 2N-1
word line 2N-2
word line 2
word line 1
word line 0
data m-1 data m-2 data0 data1 data 2
programmed “one”
programmed “zero”
bit lines
weak pull down
Random Access Memory (RAM)
wordline
bitline bitlineN
6 Transistor SRAM cell
n+c
m
sram array of 6-t cells n to 2n decoder
2n
Address input
word lines
m rnw
data in data out
peripheral circuits – column mux, sense amps, write circuitry
n
c
SRAM Organization!!l Blocks with unity aspect ratio
l Rows
l Columns
l IO
Static Memory Cell!
T1!
True!Bit!Line!
Complement!Bit!Line!
Wordline!
T2!
T5!
T3!
T6!
T4!
Cell!
T!True!Bit!Line!
Complement!Bit!Line!
Wordline!
C!
4D - Static Memory Cell!
SRAM Read Cross-Section!TSA!
CSA!
Set!Sense!Amp!
Bit !Line !Isolation!
Bit !Line!Precharge!
Isolation Circuit!
Precharge ! Circuit!
Cell!
T!TBL! CBL!
Wordline!
DRAMs precharge!to half Vdd so PFET enable required as well!
SRAM Isolation & Pre-charge Circuits!
Bit !Line !Isolation!
Bit Switch Circuit!
Pre-charge ! Circuit!Bit !Line !Pre-charge!
Cells!
Sense Amp!
SRAM Sense Amplifier Circuit!
TSA!
CSA!
Set!Sense!Amp!
Bit Switch!
DRAMs precharge!to half Vdd so PFET enable required as well!
SRAM Internal Memory Waveforms !Clock!
Word line!!!!Isolation!!Set Sense Amp!!!!Sense Amp Output!!!Data!
SRAM Write Head Circuit!
Data!
Write!Enable!
Bit Line!True!
Bit Line!Complement!
SRAM Decode Circuit!
Clock!
W0C!
W1C! W1T!
W0T! W0C! W0T!
WL0! WL1! WL2! WL3!
Word line (Polysilicon)
Bit line contacts
Ground
Vdd
NFET diffusion
PFET diffusion
SRAM Cell with Center GND Contact
Word line (Polysilicon) Bit line contacts
Ground
Vdd
NFET diffusion
PFET diffusion
SRAM Cell with Shared Vdd Contact
Word line (Polysilicon)
Bit line contact
Ground Vdd
NFET diffusion
PFET diffusion
Bit line contact
Split Word Line SRAM Cell
Bit Cell Analysis – Read Disturb!
T1!
True!Bit!Line!
Complement!Bit!Line!
Wordline!
T2!
T5!
T3!
T6!
T4!starts at 0v but will jump up. If it jumps too high, can flip the bit. T6 is often not min L to keep the jump low.
precharged to 1.8v
Bit Cell Analysis – Read Disturb!
If low, right data node (Vrd) cannot exceed the threshold of T2 or bit may flip. (Kn6 / 2) (Vdd – Vrd – Vtn)2 = (Kn5 / 2) ( 2 ( Vdd – Vtn)*Vrd – Vrd2) Kn6/Kn5 < (2(Vdd – 1.5 Vtn) Vtn) / (Vdd – 2*Vtn)2
Bit Cell Analysis - Write!l Must ensure that write head circuit can over power cell
by the end of the write cycle.
l The side of the bit cell with a 0 dominates the write transaction as the pass transistor is an NFET.
l When the word line asserts the write head circuit drives a zero on one of the two sides.
l The bit data in the cell must be brought below the threshold of the cross-coupled inverter to flip the bit.
Bit Cell Analysis – Soft Error !l Radiation (particularly in space – but occasionally on
Earth) causes the generation of charge in circuits.
l SOI technology helps as it shields transistors from charge in the bulk silicon.
l The bit cell node has a capacitance and introduced charge will change the voltage at the node.
l If the voltage swing exceeds the threshold of the cross-coupled inverter, the bit will flip (i.e. soft error)
l Qcrit is charge required to flip bit.
l Data is bad, but the bit cell still works (thus soft error).
Bit Cell Analysis – Soft Error !
T1!
True!Bit!Line!
Complement!Bit!Line!
Wordline!
T2!
T5!
T3!
T6!
T4!constant current source turned on for time t Qcrit = I * t
Redundancy and Repair!l DRAM and SRAMs often have extra rows, columns,
IOs and / or Blocks to replace those that are bad.
l Two dimensional redundancy (i.e. rows and columns) provides good coverage with minimized.
l Rule of thumb (which changes over time) is currently that 2 Mbit memories and above will benefit in terms of yield if redundancy is included.
Redundancy and Repair!
Built-In Self Test!l Many register files and embedded SRAMs in ASICs
now come with wrapper logic that will test the memory.
l The BIST includes muxes that all the test logic access to the ports of the memory.
l A BIST state machine generates address and data and writes to the ram, followed by reads and compares of the data.
l Some BIST also implement redundancy if necessary – This is often referred to as Built-In Self Repair.
