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MODIFIED BOOTH ENCODING ALGORITHM

A Project Based Laboratory Report

In partial fulfillment for the award of III/IV B.Tech - II Semester

By

A.Sree Madhuri (45)

M.Udaya Bhanu (46)

P.Vineela (47)

Dayanand (48)

K L UniversityDepartment of Electronics & Communication Engineering

Year: 2013

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Modified Booth Encoding AlgorithmMini Project report submitted in partial fulfilment of the requirement for the award of the

Degree of B.TechByA.SREE MADHURI

11004264

M.UDAYA BHANU11004264

P.VINEELA11004287

K L University

Department of Electronics & Communication Engineering

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Certificate

This is to certify that the project report entitled MODIFIED BOOTH ENCODINGALGORITHM being submitted by Miss A.SREE MADHURI (1100264), Miss M.UDAYABHANU (11004278), Miss P.VINEELA (11004287), and Mr DAYANAND (11004304). In

partial fulfilment for the award of the Degree of Bachelor of Technology in ECE to the KLUniversity is a record of benefited work carried out by them under my guidance and supervision.

The results embodied in this project report have not been submitted to any other University orInstitute for the award of any Degree or Diploma.

Mr. G.V.Ganesh Dr.K.S. Ramesh Mr. PranobKumar Dr.ASCS SastryInternal Guide Miniproject-coordinator Academic Coordinator (HOD-Dept of ECE)

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ACKNOWLEDGEMENT

The successful completion of any task is not possible without proper suggestion, guidance

and environment. Combination of these three factors acts like backbone to my project

titled MODIFIED BOOTH ENCODING ALGORITHM.

We express our sincere thanks to our guide, G.V.Ganesh Asst. Professor, Department of

E CE, for her valuable suggestions during our course period, timely help, guidance and

providing us with the most essential materials required for the completion of this work.

We are thankful to all teaching and non-teaching staff of the Department of ECE for the

cooperation given for the successful completion of my project.

We would like to thank our Head of Department, Dr A.S.C.S.SASTRY sir for providing

support and simulating environment. We would like to express my gratitude to the

Management of KL UNIVERSITY for providing me a pleasant environment.

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ABSTRACT

Multipliers are used for high performance embedded cores and in all multiplierdesigns. In conventional two s complement multiplier the main problem is that it requiresmore computation time. In this paper computation time of the Two s complement multiplieris reduced by decreasing the maximum height of the partial product array by one row in aradix- 4 Modified Booth Encoded Multiplier. The classic two s complement (nxn) bitmultiplier using the radix-4 MBE scheme generates a partial product(PP) array with amaximum height of n/2+1 rows, here we are going to reduce the maximum height of PP arrayto n/2. This technique allows for faster compression of the partial product array without anyincrease in the delay and can be extended to higher radix encodings. This technique mostly

relies on circuit optimization and minimization of the critical paths. We are using CadenceRTL compiler for synthesize report and Model simulator for simulation results. Short bit-width (8- 16 bits) two s complement multipliers with single -cycle throughput and latencyhave emerged and become very important building blocks for high-performance embedded

processors and DSP execution cores. In this case, the multiplier must be highly optimized tofit within the required cycle time and power budgets. Using these multipliers we can savecost (time and area) for adding partial products. Lower power consumption is there in thiscase of radix-4 multiplier because it is high speed parallel multiplier. It is used in multi-mediaand communication systems. As the multiplier and accumulator are the essential elements ofthe digital signal processing such as filtering, convolution, this algorithm is efficient.

KEY WORDS: Multiplier, Modified Booth Algorithm, Compiler, Power consumption.

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INDEX

CHAPTER

1. Introduction2. Software and Hardware requirements3. Multipliers 4. Modified booth encoding algorithm 5. Verilog code6. Results

7. Design summary8. Conclusion

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LIST OF FIGURES

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CHAPTER 1

INTRODUCTION

Multipliers play an important role in today s digital signal processing and variousother applications. With advances in technology, many researchers have tried and are tryingto design multipliers which offer either of the following design targets high speed, low

power consumption, regularity of layout and hence less area or even combination of them inone multiplier thus making them suitable for various high speed, low power and compactVLSI implementation. The common multiplication method is add and shift algorithm. In

parallel multipliers number of partial products to be added is the main parameter thatdetermines the performance of the multiplier. To reduce the number of partial products to beadded, Modified Booth algorithm is one of the most popular algorithms. To achieve speedimprovements Wallace Tree algorithm can be used to reduce the number of sequential adding

stages. The Modified Booth Multiplier was proposed by O. L. Macsorley in 1961. Therecoding method is widely used to generate the partial products for implementation of large parallel multipliers, which adopts the parallel encoding scheme. One of the solutions ofrealizing high speed multipliers is to enhance parallelism which helps to decrease the numberof subsequent stages.

The majority of the steps involved calculating the set of partial product and summingthe partial product together. The technique for multiplying decimal number is on the basis ofcomputing the partial products, shifting them to the left and then adding them together. Thefirst stage of majority of multipliers involves making the partial products which is an array ofAND gates. For partial product generation, an n-bit by n-bit multiplier needs n2AND gates.

The most difficult part is to get the partial products, as it involves multiplying the longnumber by one digit. The technique is very slow since it involves several intermediateadditions. The multiplier bits are categorized into groups of s bits, called selection groups ins-bit selection. By multiplying the ith selection group Si with the multiplicand N, the ith

partial product Pi is received, and shifting it to the same position x as The selection group,these multiplications takes lot of time. The sign with a separate rule generally in the 2 scomplement representation is the second issue. That compels the multiplication process to beadapted to manage 2 s complement numbers, and that perplexes the process a little more. Forthe multiplication process it takes more time and it consumes high power, delay increasedand switching activity also increased .More and more sophisticated signal processing systemsare being used on a VLSI chip, as the scale of integration remains developing. The signalProcessing applications not only need great computation capacity but also eat up substantialamount of energy. Power consumption has become a vital conc ern in today s VLSI system Design, while performance and area stay to be the two key design tolls. From two importantForces, the demand for low-power VLSI system wakes up. In portable devices, the low

power design straightly leads to prolonged operation time. Multiplication is a fundamentaloperation. Multipliers have large area, long latency and consume substantial power.

So, in low power VLSI system design, the low power multiplier design has been asignificant part. There has been widespread work on low-power multipliers at technology,

physical, circuit and logic levels. Commonly, the performance of the multiplier decides thesystem s performance, because the slowest element in the system generally is the multiplier.And also, generally it is the most area consuming. Thus, a major design issue is the

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CHAPTER-2

SOFTWARE AND HARDWARE REQUIREMENTS

SOFTWARE REQUIREMENTS

1. Xilinx ISE design suite2. Modelsim Altera3. Digilent Adept 2.15.3

Xilinx ISE (Integrated Software Environment) is a software tool produced by Xilinx forsynthesis and analysis of HDL designs, enabling the developer to synthesize ("compile") theirdesigns, perform timing analysis , examine RTL diagrams, simulate a design's reaction todifferent stimuli, and configure the target device with the programmer . Along with XilinxISE Design suite modelsim is used as a simulator to show the simulated wave form analysis.After loading the required file from work to the simulator it generates the waveforms. Digilent Adept is a unique and powerful solution which allows you to communicate withDigilent system boards and a wide assortment of logic devices.

HARDWARE REQUIREMENTS NEXYS 2

The Nexys-2 is a powerful digital systemDesign platform built around a Xilinx Spartan3E FPGA. With 16Mbytes of fast SDRAM and16Mbytes of Flash ROM, the Nexys-2 is ideallySuited to embedded processors like Xilinx's32-bit RISC Micro blaze. The on-board high-speed

USB2 port, together with a collection of I/O devices,data ports, and expansion connectors, allow a widerange of designs to be completed without the needfor any additional components.

Fig:- 2.1

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CHAPTER-3

REVIEW OF LITERATURE

MULTIPLIER

A binary multiplier is an electronic circuit used in digital electronics, such as acomputer, to multiply two binary numbers. The multiplier is a device which is used to

perform the multiplication operation. The adders and multipliers are the basic components ofdesigning of communication circuits. The multiplier is the basic key component of any digitalsignal processing system. Multiplication includes two basic steps, generation of partial

products and their accumulation. Multipliers are key components of many high performancesystems such as FIR filters, microprocessors, digital signal processors and multimediaapplications. The type of the multiplier used for an application is based upon therequirements of the application. There are different types of multiplier available according tothe requirements. The difference is in the way in which data is processed for themultiplication, the examples are serial multipliers, parallel multipliers and serial-parallelmultipliers. Using VHDL language a single component can be described using all three stylesof modelling.

In several of the digital circuits, the multiplier is mainly implemented. To use thedigital multiplier, various methods can be implemented. The majority of the steps involvedcalculating the set of partial product and summing the partial product together. The techniquefor multiplying decimal number is on the basis of computing the partial products, shifting

them to the left and then adding them together. The first stage of majority of multipliersinvolves making the partial products which is an array of AND gates. For partial productgeneration, an n-bit by n-bit multiplier needs n2 AND gates. The most difficult part is to getthe partial products, as it involves multiplying the long number by one digit. The technique isvery slow since it involves several intermediate additions. The multiplier bits are categorizedinto groups of s bits, called selection groups in s-bit selection.

In the process of normal multiplication of binary numbers the multiplicand iswritten first and then followed by the multiplier. For negative numbers the 2 s complement

form is required for representation of numbers in binary form. After writing like that take theleft most significant bit of the multiplier and then multiply it with the multiplicand and thenwrite down the result after that take the bit adjacent to the lsb bit and multiply it with themultiplicand and then shift it to the left once and then add it to the previous partial productand then take the third bit and multiply with multiplicand and shift it twice and add to the

partial product and similarly the fourth step and now result is obtained.

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EXAMPLE:-

1011 (Multiplicand)-11

1101 (Multiplier)-13

1011

0000 (Partial Products)

1011

1011

10001111 (Product-143)

3.1 DISADVANTAGES OF MULTIPLIERS

1. Circuit complexity increases with the use of usual multipliers so, time taken forexecution is more by using these multipliers.

2. By using multipliers number of partial product array is generally high.3. Any single error in the partial product array leads to results which are not accurate.

So we go for an efficient multiplication algorithm which overcomes the above disadvantages.This is a modified booth encoding algorithm which comes from booth algorithm.

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products. Thus the when it is implemented using FPGA the area occupied will be less.

3.4 BOOTH RECODING TABLE

X i+1 X X i-1 Z i/2 0 0 0 00 0 1 10 1 0 10 1 1 21 0 0 -21 0 1 -11 1 0 -1

1 1 1 0

Table: 3.2

3.5 EXAMPLE

Here in the above example

000011 is the multiplicand. 011101 is the multiplier. According to booth multiplication 3 partial products are to be obtained.

By adding the partial products we get the final result. The result is 000001010111 that is 87 in decimal.

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3.6 ADVANTAGES OF BOOTH ALGORITHM

1. The booth algorithm has its major advantages if the operands have a large number of bits.

2. Booth algorithm is efficient if the multiplier contains long sequence s of 1 s.

3. Bit pairing can reduce the number of summands further.

3.7 DISADVANTAGES OF BOOTH ALGORITHM

1. It has its limitations if the multiplier contains only small groups of 1 s or even alternating0 1 pairs.2. Booth algorithm may double the number of non-zero summands which is a disadvantage.

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CHAPTER-4

HARDWARE AND SOFTWARE REQUIREMENT ANALYSIS

MODIFIED BOOTH MULTIPLIER

The Modified Booth multiplier is an extension of Booth s multiplier. In ModifiedBooth, the number of partial products reduced by N/2, that is half of total partial products ascompare to simple multiplication process. So, clearly if the number of partial products

becomes reduced, the area of the multiplier also will reduce and automatically as the result ofit, the speed will increased. So, this multiplier is more efficient.

4.1 MODIFIED BOOTH ALGORITHM

The Modified Booth algorithm is the most frequently used method to generate partial products. The partial products are reduced by n/2 by using this algorithm. So as the result ofthis, the multiplier can be implemented using less hardware components as compare toconventional multiplier. This algorithm can save multiplier layout area and reduces delay atthe same time which are the important design advantages. One of the method for high speedmultiplier is to enhance the parallelism by reducing the number of calculating stages .Boothencoding reduces partial products to N/2. It converts the multiplier from radix-2 to radix-4using redundant digit set {-2, -1, 0, 1, 2}. So in new multiplier withradix-4 there are only N/2digits.

Booth algorithm is a method that will reduce the number of multiplicand multiples.For a given range of numbers to be represented, a higher representation radix leads to fewerdigits. Since a k-bit binary number can be interpreted as K/2-digit radix-4 number, a K/3-digitradix-8 number, and so on, it can deal with more than one bit of the multiplier in each cycle

by using high radix multiplication.

4.2 MODULES AND THEIR FUNCTIONALITIES

As shown in the example , if multiplication is done in radix 4, in each step, the partial

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product term (Bi+1Bi) 2 A needs to be formed and added to the cumulative partial product.Whereas in radix-2 multiplication, each row of dots in the partial products matrix represents 0or a shifted version of A must be included and added.

STEPS TO EXECUTE THE CODE IN VERILOG

1. First double click on the Xilinx ISE icon in its respective location.2. Close the existing projects if any are opened.3. Create a new project with a name (MBE say) in a folder by click on the Verilog

module. 4. Then a window appears with the module name created earlier along with respective

inputs and outputs.5. The program must be typed in the module and then the module must be saved.6. Towards left side of the Xilinx window there exists synthesize option where the

syntax of the module can be verified using the option check syntax. 7. When it was verified that there are no errors in the module it must be synthesized by

running the synthesize option.8. Double click on view RTL schematic and Technology schematic to view the

designs.9. To view the output of the module a test bench must be created.10. For this right click on the name of the module towards left of the window and then

click on new source.11. There appears a window and then select Verilog test fixture and then name the test-

bench as (MBEtb say) and then click finish.12. Give the respective inputs in the test-bench and then save it.13. Click on the simulation option towards left of the window and then double click on

the Model-sim Simulator to view the output waveforms.

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CHAPTER-5

HARDWARE AND SOFTWARE DESIGN

VERILOG CODE

module finalmodified(a,b,c,clk);input [3:0]a;input [3:0]b;input clk;output [7:0]c;reg [5:0] w1,w2,w4,w5;reg [7:0]w3;

always@(posedge clk) beginif(b[1:0]==2'b00) w1=4'b0000;else if(b[1:0]==2'b01) w1=a[3:0];else if(b[1:0]==2'b10) w1={a[3:0],1'b0};else if(b[1:0]==2'b11)

beginw2={a[3:0],1'b0};w1=a[3:0]+w2[4:0];endif(b[3:2]==2'b00) w3=4'b0000;else if(b[3:2]==2'b01) w3={a[3:0],2'b00};else if(b[3:2]==2'b10) w3={a[3:0],3'b000};else if(b[3:2]==2'b11)

beginw4={a[3:0],1'b0};w5=a[3:0]+w4[4:0];w3={w5,2'b0};endendassign c=w1[5:0]+w3[7:0];endmodule

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5.1 TEST BENCH

module finalmodifiedtb;// Inputs

reg [3:0] a;reg [3:0] b;reg clk;

// Outputswire [7:0] c;

// Instantiate the Unit Under Test (UUT)finalmodified uut (

.a(a),.b(b),

.c(c),

.clk(clk));

initial begin// Initialize Inputs

a = 4'b1111; b = 4'b1111;clk = 1;

// Wait 100 ns for global reset to finish#100;// Add stimulus here

end

endmodule

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CHAPTER-6

RESULTS AND SIMULATIONS (multiplication result for numbers 15 and 8)

Fig:-6.1

Fig:-6.2

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6.1 DESIGN SUMMARY

Fig:-6.36.2 TECHNOLOGY SHEMATIC

Fig:-6.4

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6.4 TIMING SUMMARY

SPEED GRADE: -4

Minimum period: No path found

Minimum input arrival time before clock: 4.929 ns

Maximum output arrival time after clock: 7.204 ns

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6.5 SNAPSHOT OF THE OUTPUT

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CONCLUSION

In this project a low power multiplier using Modified booth encoding algorithm was proposed. The modifications to the conventional architecture included the Modified Boothalgorithm for Radix-4 reducing the switching activities use of encoding and bypassing zeros

technique. The results were shown for dynamic power and delay reduction compared to othermultiplier design. For this proposed low power multiplier was successfully designed andsynthesized using XILINX ISE. Output power for proposed design was 50% minimized anddelay was minimized up to 30% compared to the existing low power Booth s multipliers.

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CHAPTER-7

REFERENCES

1.Eric Whartona, Dr. Karen Panettac, Dr. Sos Agaian, Digital electronicarithmetic with applications, IEEE Inter. Conf., 2007.

2. Design and performance of pixel-level pipelined-parallel architecture forhigh speed wavelet-based image compression, Computers and ElectricalEngineering, 2005.

3.G. Deng and L. W. Cahill Logarithmic number system and its application toimage processing, Department of Electronic Engineering, La Trobe University,Bundoora Victoria 3083 Australia. IEEE.

4. R. Hashemian and C.P. Chen A New Parallel Technique for Design ofDecrement/Increm ent and Two s Complement Circuits, Proc. 34th MidwestSymp. Circuits and Systems, vol. 2, pp. 887-890, 1991.

5. J.-Y .Kang and J. - L.Gaudiot, A Fast and Well - Structured Multiplier,Proc. Euromicro Symp. Digital System Design, pp. 508-515, Sept. 2004.

6. M.D. Ercegovac and T. Lang, Digital Arithmetic. Morgan Kaufmann

Publishers, 2003.