LTC3723-1/LTC3723-2

1372312f

, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.APPLICATIO S

U

FEATURES

TYPICAL APPLICATIO

U

DESCRIPTIO

U

The LTC®3723-1/LTC3723-2 synchronous push-pull PWMcontrollers provide all of the control and protection func-tions necessary for compact and highly efficient, isolatedpower converters. High integration minimizes externalcomponent count, while preserving design flexibility.

The robust push-pull output stages switch at half theoscillator frequency. Dead-time is independently pro-grammed with an external resistor. Synchronous rectifiertiming is adjustable to optimize efficiency. A UVLO pro-gram input provides precise system turn-on and turn offvoltages. The LTC3723-1 features peak current modecontrol with programmable slope compensation and lead-ing edge blanking, while the LTC3723-2 employs voltagemode control with voltage feedforward capability.

The LTC3723-1/LTC3723-2 feature extremely low operat-ing and start-up currents. Both devices provide reliableshort-circuit and overtemperature protection. TheLTC3723-1/LTC3723-2 are offered in a 16-pin SSOPpackage.

Telecommunications, Infrastructure Power Systems Distributed Power Architectures

High Efficiency Synchronous Push-Pull PWM 1.5A Sink, 1A Source Output Drivers Supports Push-Pull, Full-Bridge, Half-Bridge, and

Forward Topologies Adjustable Push-Pull Dead-Time and Synchronous

Timing Adjustable System Undervoltage Lockout and

Hysteresis Adjustable Leading Edge Blanking Low Start-Up and Quiescent Currents Current Mode (LTC3723-1) or Voltage Mode

(LTC3723-2) Operation Single Resistor Slope Compensation VCC UVLO and 25mA Shunt Regulator Programmable Fixed Frequency Operation to 1MHz 50mA Synchronous Output Drivers Soft-Start, Cycle-by-Cycle Current Limiting and

Hiccup Mode Short-Circuit Protection 5V, 15mA Low Dropout Regulator Available in 16-Pin SSOP Package

Synchronous Push-PullPWM Controllers

••

VOUT

VOUT

V+

VOUT

GND-F

LT1431

GND-S

COLL RREF

372312 TA01

VIN

VREF

FROMAUXILIARY

WINDING

VREF

DRVA

DRVB

CSVCC

DPRG

LTC3723-1

SDRA

SDRB

VREF

COMP

UVLO

SPRG

CT

RLEB

SS

FB GND

LTC3901

SYNCME

MF

Isolated Push-Pull Converter

LTC3723-1/LTC3723-2

2372312f

VCC to GND (Low Impedance Source) .......–0.3V to 10V(Chip Self-Regulates at 10.3V)

UVLO to GND............................................. –0.3V to VCCAll Other Pins to GND(Low Impedance Source) .........................–0.3V to 5.5VVCC (Current Fed) ................................................. 40mA

ABSOLUTE AXI U RATI GS

W WW U

PACKAGE/ORDER I FOR ATIOU UW

(Note 1)

ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V unless otherwise noted.

VREF Output Current ............................... Self-RegulatedOperating Temperature (Notes 5,6)

LTC3723E ........................................... –40°C to 85°CStorage Temperature Range ................. –65°C to 125°CLead Temperature (Soldering, 10sec)................... 300°C

TJMAX = 125°C, θJA = 100°C/W

ORDER PART NUMBER GN PART MARKING

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LTC3723EGN-1

Order Options Tape and Reel: Add #TRLead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBFLead Free Part Marking: http://www.linear.com/leadfree/

37231

1

2

3

4

5

6

7

8

TOP VIEW

GN PACKAGE16-LEAD PLASTIC SSOP

16

15

14

13

12

11

10

9

VREF

SDRB

SDRA

DRVB

VCC

DRVA

GND

CT

SPRG

UVLO

SS

FB

RLEB

COMP

CS

DPRG

TJMAX = 125°C, θJA = 100°C/W

ORDER PART NUMBER GN PART MARKING

LTC3723EGN-2 37232

1

2

3

4

5

6

7

8

TOP VIEW

GN PACKAGE16-LEAD PLASTIC SSOP

16

15

14

13

12

11

10

9

VREF

SDRB

SDRA

DRVB

VCC

DRVA

GND

CT

SPRG

UVLO

SS

FB

DPRG

COMP

CS

RAMP

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Supply

VCCUV VCC Undervoltage Lockout Measured on VCC 10.25 10.7 V

VCCHY VCC UVLO Hysteresis Measured on VCC 3.8 4.2 V

ICCST Start-Up Current VCC = VUVLO – 0.3V 145 230 µA

ICCRN Operating Current No Load on Outputs 3 8 mA

VSHUNT Shunt Regulator Voltage Current into VCC = 10mA 10.3 10.8 V

RSHUNT Shunt Resistance Current into VCC = 10mA to 17mA 1.4 3.5 ΩSUVLO System UVLO Threshold Measured on UVLO Pin, 10mA into VCC 4.8 5.0 5.2 V

SHYST System UVLO Hysteresis Current Current Flows Out of UVLO Pin, 10mA into VCC 8.5 10 11.5 µA

Pulse Width Modulator

ROS Ramp Offset Voltage Measured on COMP, RAMP = 0V 0.65 V

IRMP Ramp Discharge Current RAMP = 1V, COMP = 0V, CT = 4V, 3723-1 Only 50 mA

LTC3723-1/LTC3723-2

3372312f

ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ISLP Slope Compensation Current Measured on CS, CT = 1V, 3723-1 Only 30 µACT = 2.25V 68 µA

DCMAX Maximum Duty Cycle COMP = 4.5V 47 48.2 50 %

DCMIN Minimum Duty Cycle COMP = 0V 0 %

DTADJ Dead-Time 130 ns

Oscillator

OSCI Initial Accuracy TA = 25°C, CT = 270pF 220 250 280 kHz

OSCT VCC Variation VCC = 6.5V to 9.5V, Overtemperature –3 3 %

OSCV CT Ramp Amplitude Measured on CT 2.35 V

Error Amplifier

VFB FB Input Voltage COMP = 2.5V, (Note 3) 1.172 1.2 1.22 V

FBI FB Input Range Measured on FB, (Note 4) –0.3 2.5 V

AVOL Open-Loop Gain COMP = 1V to 3V, (Note 3) 70 90 dB

IIB Input Bias Current COMP = 2.5V, (Note 3) 5 50 nA

VOH Output High Load on COMP = –100µA 4.7 4.92 V

VOL Output Low Load on COMP = 100µA 0.27 0.5 V

ISOURCE Output Source Current COMP = 2.5V 400 700 µA

ISINK Output Sink Current COMP = 2.5V 2 5 mA

Reference

VREF Initial Accuracy TA = 25°C, Measured on VREF 4.925 5.00 5.075 V

REFLD Load Regulation Load on VREF = 100µA to 5mA 2 15 mV

REFLN Line Regulation VCC = 6.5V to 9.5V 1 10 mV

REFTV Total Variation Line, Load and Temperature 4.900 5.000 5.100 V

REFSC Short-Circuit Current VREF Shorted to GND 18 30 45 mA

Push-Pull Outputs

DRVH(x) Output High Voltage IOUT(x) = –100mA 9.0 9.2 V

DRVL(x) Output Low Voltage IOUT(x) = 100mA 0.17 0.6 V

RDH(x) Pull-Up Resistance IOUT(x) = –10mA to –100mA 2.9 4 ΩRDL(x) Pull-Down Resistance IOUT(x) = –10mA to –100mA 1.7 2.5 ΩTDR(x) Rise-Time COUT(x) = 1nF 10 ns

TDF(x) Fall-Time COUT(x) = 1nF 10 ns

Synchronous Outputs

OUTH(x) Output High Voltage IOUT(x) = –30mA 9.0 9.2 V

OUTL(x) Output Low Voltage IOUT(x) = 30mA 0.44 0.6 V

RHI(x) Pull-Up Resistance IOUT(x) = –10mA to -30mA 11 15 ΩRLO(x) Pull-Down Resistance IOUT(x) = –10mA to -30mA 15 20 ΩTR(x) Rise-Time COUT(x) = 50pF 10 ns

TF(x) Fall-Time COUT(x) = 50pF 10 ns

Current Limit and Shutdown

CLPP Pulse by Pulse Current Limit Threshold Measured on CS 280 300 320 mV

CLSD Shutdown Current Limit Threshold Measured on CS 475 600 725 mV

CLDEL Current Limit Delay to Output 100mV Overdrive on CS, (Note 2) 80 ns

LTC3723-1/LTC3723-2

4372312f

VCC (V)0

I CC

(µA)

100

150

8

372312 G01

50

02 4 6 10

200

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V unless otherwise noted.

Start-Up ICC vs VCC VCC vs ISHUNT

Oscillator Frequency vsTemperature

TYPICAL PERFOR A CE CHARACTERISTICS

UW

ISHUNT (mA)0

V CC

(V)

10.00

10.25

40

372312 G02

9.75

9.5010 20 30 50

10.50

TEMPERATURE (°C)

FREQ

UENC

Y (k

Hz)

240

250

80

372312 G03

230

220–40–60 –20 200 40 60 100

260CT = 270pF

(TA = 25°C unless otherwise noted)

Leading Edge Blanking Timevs RLEB VREF vs IREF VREF vs Temperature

RLEB (kΩ)0

BLAN

K TI

ME

(ns)

350

300

250

200

150

100

50

0

372312 G04

40 1002010 30 50 70 9060 80IREF (mA)

0

V REF

(V)

5.05

5.00

4.95

4.90

4.85

4.8015 25 40

372312 G05

5 10 20 30 35

TJ = 25°C

TJ = 85°C

TJ = –40°C

TEMPERATURE (°C)

V REF

(V)

4.99

5.00

80

372312 G06

4.98

4.97–40–60 –20 200 40 60 100

5.01

Note 1: Absolute Maximum Ratings are those values beyond which the lifeof a device may be impaired.Note 2: Includes leading edge blanking delay, RLEB = 20k, not tested inproduction.Note 3: FB is driven by a servo loop amplifier to control VCOMP for thesetests.Note 4: Set FB to –0.3V, 2.5V and insure that COMP does not phase invert.Note 5: The LTC3723E–1/LTC3723E-2 are guaranteed to meet

performance specifications from 0°C to 70°C. Specifications over the–40°C to 85°C operating temperature range are assured by design,characterization and correlation with statistical process controls.Note 6: This IC includes overtemperature protection that is intended toprotect the device during momentary overload conditions. Junctiontemperature will exceed 125°C when overtemperature protection is active.Continuous operation above the specified maximum operating junctiontemperature may impair device reliability.

SSI Soft-Start Current SS = 2.5V 10 13 16 µA

SSR Soft-Start Reset Threshold Measured on SS 0.7 0.4 0.1 V

FLT Fault Reset Threshold Measured on SS 4.5 4.2 3.5 V

LTC3723-1/LTC3723-2

5372312f

FREQUENCY (Hz)

GAIN

(dB)

PHAS

E (D

EG) –180

1M

372312 G07

–270

–360

10 1k100 10k 100k 10M

100806040200

TEMPERATURE (°C)–55

I CC

(µA)

190

180

170

160

150

140

130

120

110

100

372312 G08

–25 5 35 95 12565RDPRG (kΩ)

050

DELA

Y (n

s)

100

150

200

75

125

175

225

275

50 100 150 200

372312 G09

250 500450400350300

250

NO 200k PREBIAS

200k PREBIAS

RSPRG (kΩ)0

0

DELA

Y (n

s)

400

500

700

600

900

100 150

372312 G12

300

200

100

800

250 30050 200TEMPERATURE (°C)

–55

CURR

ENT

(µA)

90

80

70

60

50

40

30

20

10

0

372312 G10

–25 5 35 95 12565

CT = 1V

CT = 2.25V

TEMPERATURE (°C)–55

10.5

10.4

10.3

10.2

10.1

10.0

9.9

9.8

372312 G11

–25 5 35 95 12565

SHUN

T VO

LTAG

E (V

)

ICC = 10mA

Error Amplifier Gain/Phase Start-Up ICC vs Temperature

TYPICAL PERFOR A CE CHARACTERISTICS

UW

LTC3723 Deadtime vs RDPRGWith and Without 200k PrebiasCompensation

(TA = 25°C unless otherwise noted)

Synchronous Driver Turn-Off Delayvs RSPRG Referenced to CT PeakSlope Current vs Temperature

VCC Shunt Voltage vsTemperature

FB Input Voltage vs Temperature

TEMPERATURE (°C)–55

FB V

OLTA

GE (V

)

1.205

1.204

1.203

1.202

1.201

1.200

1.199

1.198

1.197

372312 G13

–25 5 35 95 12565

Synchronous Driver Turn-OffDelay vs RSPRG Referenced toPush-Pull Driver Outputs

RSPRG (kΩ)0

200

250

350

100

372312 G14

150

100

50 200150 250 300

50

–50

0

300

DELA

Y (n

s)

RDPRG = 150k

LTC3723-1/LTC3723-2

6372312f

VREF (Pin 1/Pin 1): Output of the 5.0V Reference. VREF iscapable of supplying up to 18mA to external circuitry. VREFshould be decoupled to GND with a 0.47µF ceramiccapacitor.

SDRB (Pin 2/Pin 2): 50mA Driver for Synchronous Recti-fier associated with DRVB.

SDRA (Pin 3/Pin 3): 50mA Driver for Synchronous Recti-fier associated with DRVA.

DRVB (Pin 4/Pin 4): High Speed 1.5A Sink, 1A SourceTotem Pole MOSFET Driver. Connect to gate of externalpush-pull MOSFET with as short a PCB trace as practicalto preserve drive signal integrity. A low value resistorconnected between DRVA and the MOSFET gate is op-tional and will improve the gate drive signal quality if thePCB trace from the driver to the MOSFET cannot be madeshort.

VCC (Pin 5/Pin 5): Supply Voltage Input to the LTC3723-1/LTC3723-2 and 10.25V Shunt Regulator. The chip isenabled after VCC has risen high enough to allow the VCCshunt regulator to conduct current and the UVLO com-parator threshold is exceeded. Once the VCC shunt regu-lator has turned on, VCC can drop to as low as 6V (typical)and maintain operation. Bypass VCC to GND with a highquality 1µF or larger ceramic capacitor to supply thetransient currents caused by the high speed switching andcapacitive loads presented by the on chip totem poledrivers.

DRVA (Pin 6/Pin 6): High Speed 1.5A Sink, 1A SourceTotem Pole MOSFET Driver. Connect to gate of externalpush-pull MOSFET with as short a PCB trace as practicalto preserve drive signal integrity. A low value resistorconnected between DRVA and the MOSFET gate is op-tional and will improve the gate drive signal quality if thePCB trace from the driver to the MOSFET cannot be madeshort.

GND (Pin 7/Pin 7): All circuits in the LTC3723 are refer-enced to GND. Use of a ground plane is highly recom-

DESCRIPTIO S

U

PI

U

(LTC3723-1/LTC3723-2)

mended. VIN and VREF bypass capacitors must be termi-nated with a star configuration as close to GND as practicalfor best performance.

CT (Pin 8/Pin 8): Timing Capacitor for the Oscillator. Usea ±5% or better low ESR ceramic capacitor for bestresults. CT ramp amplitude is 2.35V peak-to-peak(typical).

DPRG (Pin 9/Pin 12): Programming Input for Push-PullDead-Time. Connect a resistor between DPRG and VREFto program the dead-time. The nominal voltage on DPRGis 2V.

RAMP (N/A/Pin 9): Input to PWM Comparator forLTC3723-2 Only (Voltage Mode Controller). The voltageon RAMP is internally level shifted by 650mV.

CS (Pin 10/Pin 10): Input to Pulse-by-Pulse and OverloadCurrent Limit Comparators, Output of Slope Compensa-tion Circuitry. The pulse-by-pulse comparator has a nomi-nal 300mV threshold, while the overload comparator hasa nominal 600mV threshold. An internal switch dischargesCS to GND after every timing period. Slope compensationcurrent flows out of CS during the PWM period.An external resistor connected from CS to the externalcurrent sense resistor programs the amount of slopecompensation.

COMP (Pin 11/Pin 11): Error Amplifier Output, InvertingInput to Phase Modulator.

RLEB (Pin 12/N/A): Timing Resistor for Leading EdgeBlanking. Use a 10k to 100k resistor connected betweenRLEB and GND to program from 40ns to 310ns of leadingedge blanking of the current sense signal on CS for theLTC3723-1. A ±1% tolerance resistor is recommended.The LTC3723-2 has a fixed blanking time of approximately80ns. The nominal voltage on RLEB is 2V. If leading edgeblanking is not required, tie RLEB to VREF to disable.

FB (Pin 13/Pin 13): Error Amplifier Inverting Input. This isthe voltage feedback input for the LTC3723. The nominalregulation voltage at FB is 1.2V.

LTC3723-1/LTC3723-2

7372312f

PROGRAMMABLEDEAD-TIME

PROGRAMMABLESYNCHRONOUS

TURN-OFF DELAYDRVA

DRVB

SDRA

SDRB

372312 TD01

CURRENTSENSE

OR CT RAMP

PWMCOMPARATOR

(–)

TI I G DIAGRA

WU W

DESCRIPTIO S

U

PI

U

(LTC3723-1/LTC3723-2)

SS (Pin 14/Pin 14): Soft-Start/Restart Delay CircuitryTiming Capacitor. A capacitor from SS to GND provides acontrolled ramp of the current command (LTC3723-1) orduty cycle (LTC3723-2). During overload conditions, SS isdischarged to ground initiating a soft-start cycle. SScharging current is approximately 13µA. SS will charge upto approximately 5V in normal operation. During a con-stant overload current fault, SS will oscillate at a lowfrequency between approximately 0.5V and 4V.

UVLO (Pin 15/Pin 15): Input to Program System Turn-Onand Turn-Off Voltages. The nominal threshold of the UVLOcomparator is 5.0V. UVLO is connected to the main DCsystem feed through a resistor divider. When the UVLO

threshold is exceeded, the LTC3723-1/LTC3723-2 com-mences a soft-start cycle and a 10µA (nominal) current isfed out of UVLO to program the desired amount of systemhysteresis. The hysteresis level can be adjusted by chang-ing the resistance of the divider. UVLO can also be used toterminate all switching by pulling UVLO down to less than4V. An open drain or collector switch can perform thisfunction without changing the system turn on or turn offvoltages.

SPRG (Pin 16/Pin 16): A resistor is connected betweenSPRG and GND to set the turn off delay for the synchro-nous rectifier driver outputs. The nominal voltage onSPRG is 2V.

LTC3723-1/LTC3723-2

8372312f

BLOCK DIAGRA S

W

R Q

S

Q

T 1.5A SINK

1A SOURCE

DRVA

Q

RQ

S

6

DRVB4

1.5A SINK

1A SOURCE

SDRB2

SDRA3SYNC

RECTIFIERDRIVELOGIC

FAULTLOGIC

OSCILLATOR

SLOPECOMPENSATOR

PULSE-BY-PULSECURRENT LIMIT

300mV 372312 BD01

SPRG

16

CT

8

DPRG

9

–

+

PULSE WIDTHMODULATOR

ERRORAMPLIFIER

+

–

SHUTDOWNCURRENT LIMIT

VREF

13µA

50k

14.9k

600mV –

+

–

+

BLANK

RLEB 12 7

CS 10

SS 14

COMP

1.2V

11

FB 13

+

–

SYSTEMUVLO

VCC

VCCGOOD

10µA

5V –

+

+

–650mV

UVLO

15

REF, LDO1.2V

5V

REF GOOD

VREF

1

VCC UVLO

10.25V “ON”6V “OFF”

VCC

5

GND

LTC3723-1 Block Diagram

LTC3723-1/LTC3723-2

9372312f

R Q

S

Q

T 1.5A SINK

1A SOURCE

DRVA

Q

RQ

S

6

DRVB4

1.5A SINK

1A SOURCE

SDRB2

SDRA3SYNC

RECTIFIERDRIVELOGIC

OUTPUTDRIVELOGIC

FAULTLOGIC

OSCILLATOR

PULSE-BY-PULSECURRENT LIMIT

300mV 372312 BD02

SPRG

16

DPRG9

CT

8

–

+

PULSE WIDTHMODULATOR

ERRORAMPLIFIER

+

–

SHUTDOWNCURRENT LIMIT

VREF

13µA

50k

600mV –

+

BLANK

7

CS 10

SS 14

COMP

1.2V

11

FB 13

+

–

SYSTEMUVLO

VCC

VCCGOOD

10µA

5V –

+

+

–650mV

UVLO

15

REF, LDO1.2V

5V

REF GOOD

VREF

1

VCC UVLO

10.25V “ON”6V “OFF”

VCC

5

GND

RAMP 9

–

+

BLOCK DIAGRA S

W

LTC3723-2 Block Diagram

LTC3723-1/LTC3723-2

10372312f

–

+TURN-ON OUTPUT

2.5V

+

–V 2V

10µA

VREF

DPRGRDPRG

372312 F01

200kOPTIONAL

Please refer to the detailed Block Diagrams for this discus-sion. The LTC3723-1 and LTC3723-2 are synchronousPWM push-pull controllers. The LTC3723-1 operates withpeak pulse-by-pulse current mode control while theLTC3723-2 offers voltage mode control operation. Theyare best suited for moderate to high power isolated powersystems where small size and high efficiency are required.The push-pull topology delivers excellent transformerutilization and requires only two low side power MOSFETswitches. Both controllers generate 180° out of phase0% to <50% duty cycle drive signals on DRVA and DRVB.The external MOSFETs are driven directly by these power-ful on-chip drivers. The external MOSFETs typically con-trol opposite primary windings of a centertapped powertransformer. The centertap primary winding is connectedto the input DC feed. The secondary of the transformer canbe configured in different synchronous or nonsynchronousconfigurations depending on the application needs.

The duty ratio is controlled by the voltage on COMP. Aswitching cycle commences with the falling edge of theinternal oscillator clock pulse. The LTC3723-1 attenuatesthe voltage on COMP and compares it to the current sensesignal to terminate the switching cycle. The LTC3723-2compares the voltage on COMP to a timing ramp toterminate the cycle. The LTC3723-2’s CT waveform can beused for this purpose or separate R-C components can beconnected to RAMP to generate the timing ramp. If thevoltage on CS exceeds 300mV, the present cycle is termi-nated. If the voltage on CS exceeds 600mV, all switchingstops and a soft-start sequence is initiated.

The LTC3723-1 / LTC3723-2 also provide drive signals forsecondary side synchronous rectifier MOSFETs. Synchro-nous rectification improves converter efficiency, espe-cially as the output voltages drop. Independent turn-offcontrol of the synchronous rectifiers is provided via SPRGin order to optimize the benefit of the synchronous recti-fiers. A resistor from SPRG to GND sets the desired turnoff delay.

A host of other features including an error amplifier,system UVLO programming, adjustable leading edge blank-ing, slope compensation and programmable dead-timeprovide flexibility for a variety of applications.

OPERATIOU

Programming Driver Dead-Time

The LTC3723-1/LTC3723-2 controllers include a featureto program the minimum time between the output signalson DRVA and DRVB commonly referred to as the driverdead-time. This function will come into play if the control-ler is commanded for maximum duty cycle. The dead-timeis set with an external resistor connected between DPRGand VREF (see Figure 1). The nominal regulated voltage onDPRG is 2V. The external resistor programs a currentwhich flows into DPRG. The dead-time can be adjustedfrom 90ns to 300ns with this resistor. The dead-time canalso be modulated based on an external current sourcethat feeds current into DPRG. Care must be taken to limitthe current fed into DPRG to 350µA or less. An internal10µA current source sets a maximum deadtime if DPRG isfloated. The internal current source causes the programmeddeadtime to vary non-linearly with increasing values ofRDPRG (see typical performance characteristics). An ex-ternal 200k resistor connected from DPRG to GND willcompensate for the internal 10µA current source andlinearize the deadtime delay vs RDPRG characteristic.

Powering the LTC3723-1/LTC3723-2

The LTC3723-1/LTC3723-2 utilize an integrated VCC shuntregulator to serve the dual purposes of limiting the voltageapplied to VCC as well as signaling that the chip’s biasvoltage is sufficient to begin switching operation (undervoltage lockout). With its typical 10.2V turn-on voltageand 4.2V UVLO hysteresis, the LTC3723-1/LTC3723-2 istolerant of loosely regulated input sources such as anauxiliary transformer winding. The VCC shunt is capable ofsinking up to 40mA of externally applied current. TheUVLO turn-on and turn-off thresholds are derived from aninternally trimmed reference making them extremely ac-curate. In addition, the LTC3723-1/LTC3723-2 exhibits

Figure 1. Delay Timeout Circuitry

LTC3723-1/LTC3723-2

11372312f

very low (145µA typ) start-up current that allows the useof 1/8W to 1/4W trickle charge start-up resistors.

The trickle charge resistor should be selected as follows:RSTART(MAX) = VIN(MIN) – 10.7V/250µA

Adding a small safety margin and choosing standardvalues yields:

APPLICATION VIN RANGE RSTART

DC/DC 36V to 72V 100k

Off-Line 85V to 270VRMS 430k

PFC Preregulator 390VDC 1.4M

VCC should be bypassed with a 0.1µF to 1µF multilayerceramic capacitor to decouple the fast transient currentsdemanded by the output drivers and a bulk tantalum orelectrolytic capacitor to hold up the VCC supply before thebootstrap winding, or an auxiliary regulator circuit takesover.

CHOLDUP = (ICC + IDRIVE) • tDELAY/3.8V(minimum UVLO hysteresis)

Regulated bias supplies as low as 7V can be utilized toprovide bias to the LTC3723-1/LTC3723-2. Refer toFigure 2 for various bias supply configurations.

Figure 2. Bias Configurations

372312 F02

12V ±10%

1.5k

VCC

VIN

VCC

CHOLD

1N52263V

1µF 1µF

VBIAS < VUVLO

RSTART1N914

+

Figure 3. System UVLO Setup

ON OFF RBOTTOM

RTOP

UVLO

372312 F03

OPERATIOU

UVLO. The amount of DC feed hysteresis provided by thiscurrent is: 10µA • RTOP, (Figure 3). The system UVLOthreshold is: 5V • (RTOP + RBOTTOM)/RBOTTOM. If thevoltage applied to UVLO is present and greater than 5Vprior to the VCC UVLO circuitry activation, then the internalUVLO logic will prevent output switching until the follow-ing three conditions are met: (1) VCC UVLO is enabled, (2)VREF is in regulation and (3) UVLO pin is greater than 5V.

UVLO can also be used to enable and disable the powerconverter. An open drain transistor connected to UVLO asshown in Figure 3 provides this capability.

Programming Undervoltage Lockout

The LTC3723-1/LTC3723-2 provides undervoltage lock-out (UVLO) control for the input DC voltage feed to thepower converter in addition to the VCC UVLO functiondescribed in the preceding section. Input DC feed UVLO isprovided with the UVLO pin. A comparator on UVLOcompares a divided down input DC feed voltage to the 5Vprecision reference. When the 5V level is exceeded onUVLO, the SS pin is released and output switching com-mences. At the same time a 10µA current is enabled whichflows out of UVLO into the voltage divider connected to

Off-Line Bias Supply Generation

If a regulated bias supply is not available to provide VCCvoltage to the LTC3723-1/LTC3723-2 and supportingcircuitry, one must be generated. Since the power require-ment is small, approximately 1W, and the regulation is notcritical, a simple open-loop method is usually the easiestand lowest cost approach. One method that works well isto add a winding to the main power transformer, and postregulate the resultant square wave with an L-C filter (seeFigure 4a). The advantage of this approach is that itmaintains decent regulation as the supply voltage varies,and it does not require full safety isolation from the inputwinding of the transformer. Some manufacturers includea primary winding for this purpose in their standard

Figure 4a. Auxiliary Winding Bias Supply

372312 F04a

+

VCCVIN

CHOLD 1µF

RSTART

2k15V*

*OPTIONAL

LTC3723-1/LTC3723-2

12372312f

OPERATIOU

product offerings as well. A different approach is to add awinding to the output inductor and peak detect and filterthe square wave signal (see Figure 4b). The polarity of thiswinding is designed so that the positive voltage squarewave is produced while the output inductor is freewheel-ing. An advantage of this technique over the previous isthat it does not require a separate filter inductor and sincethe voltage is derived from the well-regulated outputvoltage, it is also well controlled. One disadvantage is thatthis winding will require the same safety isolation that isrequired for the main transformer. Another disadvantageis that a much larger VCC filter capacitor is needed, sinceit does not generate a voltage as the output is first startingup, or during short-circuit conditions.

Figure 4b. Output Inductor Bias Supply

372312 F04bVCC

VOUT

VIN

CHOLD

RSTART +

1µF

LOUT

ISO BARRIER

Programming the LTC3723-1/LTC3723-2 Oscillator

The high accuracy LTC3723-1/LTC3723-2 oscillator cir-cuit provides flexibility to program the switching fre-quency and slope compensation required for currentmode control (LTC3723-1). The oscillator circuit pro-duces a 2.35V peak-to-peak amplitude ramp waveform onCT. Typical maximum duty cycles of 49% are possible. Theoscillator is capable of operation up to 1MHz by thefollowing equation:

CT = 1/(14.8k • FOSC)

Note that this is the frequency seen on CT. The outputdrivers switch at 1/2 of this frequency. Also note thathigher switching frequency and added driver dead-timevia DPRG will reduce the maximum duty cycle.

The LTC3723-1/LTC3723-2 can be synchronized to anexternal frequency source such as another PWM chip. In

Single-Ended Operation

In addition to push-pull and full-bridge topologies, single-ended topologies such as the forward and flyback con-verter can benefit from the many advanced features of theLTC3723. In Figure 6, the LTC3723 is used with theLTC4440, 100V high side driver to implement a two-transistor forward converter. DRVB is used which limitsthe converter’s maximum duty cycle to 50% (less pro-grammable driver dead time).

LTC3723

CTfOSC < fEXT < 1.25 • fOSC

fSW = fOSC/2 fOSC ≅

68pF

CT

372312 F05

390Ω BAT54210µA

2.56V • CT

EXTERNALFREQUENCY

SOURCE

Figure 5. Synchronization from External Source

Figure 6. Two-Transistor Forward Converter (Duty Cycle < 50%)

210µA2 • 2.56V • CT

LTC3723

DRVB

CT GND

CT

IN

TO SYNCHRONOUSSECONDARY MOSFET

TSLTC4440

372312 F06

GND

TG

•

SDRB

VIN

fSW ≅

–VIN

Figure 5, the leading edge of an external pulse is used toterminate the natural clock cycle. If the external frequencyis higher than the oscillator frequency, the internal oscil-lator will synchronize with the external input frequency.

LTC3723-1/LTC3723-2

13372312f

The 50% duty-cycle limit is overcome with the circuitshown in Figure 7. Operation is similar to external syn-chronization, except DRVA output is used to terminate itsown clock cycle early. Switching period is now equal to theoscillator period plus programmable driver dead time.Maximum on time is equal to oscillator period minusdriver dead time.

Although near 100% duty cycle operation may be ofbenefit with non-isolated converters, it is often desirableto limit the duty cycle of single-ended isolated converters.Instead of immediately ending the unused clock’s output,Figure 8 uses a transistor to switch in additional timingcapacitor charge current. This allows one to preset themaximum duty.

Voltage Mode with LTC3723-2

Figure 9 shows how basic connections differ betweencurrent mode LTC3723-1 and voltage mode LTC3723-2.Oscillator may be used as the ramp input or the LTC3723-2 includes an internal 10mA ramp discharge useful whenimplementing voltage feedforward. Open loop control inwhich the duty cycle varies inversely proportional to inputvoltage is shown in Figure 10.

OPERATIOU

LTC3723-1

DRVA

CT

68pF

CT

372312 F07

DRVB

390Ω BAT54

fV C

ATDPRG

D fV C

ATDPRG

SWT

MAX SWT

≅

µ+

⎛⎝⎜

⎞⎠⎟

≅µ

⎛⎝⎜

⎞⎠⎟

12 56

210

2 56210

. •

. •–

Figure 7. LTC3723-1 > 50% Duty Cycle

LTC3723-1

DRVB

CT

CT

TO SYNCHRONOUSSECONDARY MOSFET

372312 F08

•

SDRBDRVA

VREF

–VIN

VIN

50k

RMMBT2369

f

V CA A R

D fV C

ATDPRG

SW

T

MAX SWT

≅

µ+

µ + ( )⎛

⎝⎜⎞

⎠⎟

≅µ

⎛⎝⎜

⎞⎠⎟

1

2 561

2101

210 3

2 56210

. •/

. •–

Figure 8. LTC3723-1 One-Switch Forward or Flyback Converter(Maximum Duty Cycle 50% to 100%)

Figure 9. LTC3723-1 Current Mode and LTC3723-2 VoltageMode Connections

Figure 10. LTC3723-2 Open Loop Control (Duty Cycle isInversely Proportional to Input Voltage)

98 11

13

372312 F10

CT

TO INPUTVOLTAGE

LTC3723-2

RAMPCTFBCOMP

RDPRG

98 121

372312 F09

CT

TO INPUTVOLTAGE

LTC3723-2

RAMPCT DPRGVREF

RDPRG

128 19

CT RLEB

LTC3723-1

RLEBCT VREFDPRG

RDPRG

89 121

CT

LTC3723-2

CTRAMP DPRGVREF

LTC3723-1/LTC3723-2

14372312f

OPERATIOU

The LTC3723-1 derives a compensating slope currentfrom the oscillator ramp waveform and sources thiscurrent out of CS. This function is disabled in theLTC3723-2. The desired level of slope compensation isselected with an external resistor connected between CSand the external current sense resistor, (Figure 11).

Current Sensing and Overcurrent Protection

Current sensing provides feedback for the current modecontrol loop and protection from overload conditions. TheLTC3723-1/LTC3723-2 are compatible with either resis-tive sensing or current transformer methods. Internallyconnected to the LTC3723-1/LTC3723-2 CS pin are twocomparators that provide pulse-by-pulse and overcurrentshutdown functions respectively, (Figure 12).

The pulse-by-pulse comparator has a 300mV nominalthreshold. If the 300mV threshold is exceeded, the PWMcycle is terminated. The overcurrent comparator is setapproximately 2x higher than the pulse-by-pulse level. Ifthe current signal exceeds this level, the PWM cycle isterminated, the soft-start capacitor is quickly dischargedand a soft-start cycle is initiated. If the overcurrent condi-tion persists, the LTC3723-1/LTC3723-2 halts PWM op-eration and waits for the soft-start capacitor to charge upto approximately 4V before a retry is allowed. The soft-start capacitor is charged by an internal 13µA currentsource. If the fault condition has not cleared when soft-start reaches 4V, the soft-start pin is again discharged anda new cycle is initiated. This is referred to as hiccup modeoperation. In normal operation and under most abnormalconditions, the pulse-by-pulse comparator is fast enoughto prevent hiccup mode operation. In severe cases, how-ever, with high input voltage, very low RDS(ON) MOSFETsand a shorted output, or with saturating magnetics, theovercurrent comparator provides a means of protectingthe power converter.

Leading Edge Blanking

The LTC3723-1/LTC3723-2 provides programmable lead-ing edge blanking to prevent nuisance tripping of thecurrent sense circuitry. Leading edge blanking relieves thefiltering requirements for the CS pin, greatly improving theresponse to real overcurrent conditions. It also allows theuse of a ground referenced current sense resistor ortransformer(s), further simplifying the design. With asingle 10k to 100k resistor from RLEB to GND, blankingtimes of approximately 40ns to 320ns are programmed. Ifnot required, connecting RLEB to VREF can disable leadingedge blanking. Keep in mind that the use of leading edgeblanking will slightly reduce the linear control range for thepulse width modulator.

Figure 12. Current Sense/Fault Circuitry Detail

+

–

+

–

OVERLOADCURRENT LIMIT

300mV

600mV

UVLOENABLE

UVLOENABLE

R

S Q

R

S Q

Q

QS

Q PWMLOGIC

H = SHUTDOWNOUTPUTS

CS

RCS

+

–

+

–

CSS

SS

0.4V

4.1V

372312 F12

PULSE BY PULSECURRENT LIMIT

PWMLATCH

PWM

13µA

Figure 11. Slope Compensation Circuitry

SWITCHCURRENT

CURRENT SENSEWAVEFORM

V(CT)33k

I = CSCT

33kADDEDSLOPE

RSLOPE

RCS

372312 F11

LTC3723

LTC3723-1/LTC3723-2

15372312f

OPERATIOU

High Current Drivers

The LTC3723-1/LTC3723-2 high current, high speed driv-ers provide direct drive of external power N-channelMOSFET switches. The drivers swing from rail to rail. Dueto the high pulsed current nature of these drivers (1.5Asink, 1A source), care must be taken with the board layoutto obtain advertised performance. Bypass VCC with a 1µFminimum, low ESR, ESL ceramic capacitor. Connect thiscapacitor with minimal length PCB leads to both VCC andGND. A ground plane is highly recommended. The driveroutput pins (DRVA, DRVB) connect to the gates of theexternal MOSFET switches. The PCB traces making theseconnections should also be as short as possible to mini-mize overshoot and undershoot of the drive signal.

Synchronous Rectification

The LTC3723-1/LTC3723-2 produces the precise timingsignals necessary to control secondary side synchronousrectifier MOSFETs on SDRA and SDRB. Synchronousrectifiers are used in place of Schottky or silicon diodes onthe secondary side to improve converter efficiency. AsMOSFET RDS(ON) levels continue to drop, significant effi-ciency improvements can be realized with synchronousrectification, provided that the MOSFET switch timing isoptimized. Synchronous rectification also provides bipo-lar output current capability, that is, the ability to sink aswell as source current.

Programming the Synchronous RectifierTurn-Off Delay

The LTC3723-1/LTC3723-2 controllers include a featureto program the turn-off edge of the secondary side syn-chronous rectifier MOSFETs relative to the beginning of a

new primary side power delivery pulse. This feature pro-vides optimized timing for the synchronous MOSFETswhich improves efficiency. At higher load currents itbecomes more advantageous to delay the turn-off of thesynchronous rectifiers until the beginning of the newpower pulse. This allows for secondary freewheelingcurrent to flow through the synchronous MOSFET channelinstead of its body diode.

The turn-off delay is programmed with a resistor fromSPRG to GND, (Figure 13). The nominal regulated voltageon SPRG is 2V. The external resistor programs a currentwhich flows out of SPRG. The delay can be adjusted fromapproximately 20ns to 200ns, with resistor values of 10kto 200k. Do not leave SPRG floating. The amount of delaycan also be modulated based on an external currentsource that sinks current out of SPRG. Care must be takento limit the current out of SPRG to 350µA or less.

–

+TURN-OFF SYNC OUT

372312 F13

+

–V 2V

SPRG

RSPRG

Figure 13. Synchronous Delay Circuitry

LTC3723-1/LTC3723-2

16372312f

L6 0

.65µ

H

1µF

V OUT

V EV F

–VOU

T

–VOU

T

8.5V

100Ω

C4 3.3µ

F50

V

390p

F

1µF

100Ω

2k1/

4WQ1

D69.

1V

C1, C

2, C

347

0µF

6.3V

×3Si

7892

DP ×3Si

7892

DP ×3

1 8

49

11

V F

V F

5

3723

12 T

A02

V OUT

–VOU

T

D147

0Ω 1W

D2

100k

1k

T21(

1.5m

H):0

.5

T19T

(150

µH):9

T:7T

:1T:

1T

••

0.1µ

F

330p

F

C6 2.2n

F25

0V

+

C5 68µF

20V

+

121187109

2 4 5 631

22Ω

360Ω

L4 1mH

D4

D5

–VOU

T

V OUT

330Ω

47Ω

0.68

µF

D7

1µF,

100

V TD

K C3

225X

7R2A

105M

C1-C

3: S

ANYO

6TP

B470

MC4

: TDK

C32

25X7

R1H3

35M

C5: A

VX T

PSE6

86M

020R

0150

C6: M

URAT

A DE

2E3K

H222

MB3

BD1

, D2:

DIO

DES

INC.

ES1

AD4

, D5:

BAS

21D6

: MM

BD52

39B

D7: B

AT54

L4: C

OILC

RAFT

DO1

608C

-105

L5: V

ISHA

Y IH

LP-2

525C

Z-01

L6: P

ULSE

PA1

294.

650

Q1: F

ZT69

0BQ2

: FM

MT3

904

R1, R

2: IR

C LR

C-LR

2512

-01-

R060

-GT1

: EFD

25 T

RANS

POW

ER T

TI86

96T2

: PUL

SE P

A078

5

Q2

Si74

50DP

Si74

50DP

80Ω

1W

100p

F20

0V

80Ω

1W

100p

F20

0V

470Ω

R1 0.06Ω

1.5W

R2 0.06Ω

1.5W

L5 1µH

1µF

100V

×3

1µF

100V

V IN

V IN

–VIN

3

42

610

65

18

19

1413

712

168

3 11

5 15

6

5

1 2

V OUT

10V

8.5V

787Ω

100Ω 22

0pF

4.99

k1/

4W

270Ω

2.49

k

0.02

2µF

47nF

–VOU

T

GND-

FV+ GND-

S

COLL

REF

LT14

31CS

8

SYNC

PVCC

CSF+

LTC3

901E

GN

MOC

207

LTC3

723E

GN-1

V REF

DPRG

SSFB

GND

R LEB

SPRG

C T

DRVB

SDRB

SDRA

COM

P

V CC

UVLODR

VACS

820Ω

150k

30k

5V33

k

10k

0.47

µF68

nF22

0pF

1µF

100Ω

1/4W

10V

66.5

k

V IN

5V

383k

75k

124.99

k

CSF–

14 84

1013

MF

15

MF

6

V E

4.99

k1/

4W

CSE+

54.99

k

40.2

kCS

E–

GND

PGND

GND

PGND

7

TIM

ER

2

ME

316

1

ME

V CC

1µF

••

••

•

165W

, 36V

to 7

2V to

3.3

V at

50A

Isol

ated

Pus

h-Pu

ll Co

nver

ter

TYPICAL APPLICATIO S

U

LTC3723-1/LTC3723-2

17372312f

TYPICAL APPLICATIO S

U

5

46

A

A

10V

V IN

15

9 174k

1

0.47

µF

1µF

V REF

C T

220p

F10

nF

T2

T1EF

D20

1.13

k

21.5

k1.

5k

813

Si74

56DP

L4 1mH

68µF 20V

••

10

818

54

16

10k

33k

100Ω

1/4W

66.5

k

127

14

560Ω

383k

30k

SYNC

TIM

ERLT

C390

0ES8

6

7

1nF

0.47

µF

3723

12 T

A03

V OUT

+

D1 4.3V

V OUT

FG

GND

V CC

5

909Ω

26.1

kCS

+

CS+

CS+

FG

FG

CG

V OUT

V OUT

CS–

12

CG

34

Si74

56DP

L14.

7µH

52 3

10V

BAS2

1

BAS2

1

•

1 4

•• 6

+

Si74

50DP

1µF

100V

×2

V IN

V IN

–VIN

1.5n

F20

0V

1µF

100V

47µF

16V

×2

+1.

5nF

10µF

25V

10k

0.1µ

F0.

1µF

220p

F

6

2

2.2n

F25

0V 220p

F

11

5

1 25 6

MOC

207

1 2

4V I

N GND

3

OC

COM

P

OPTO

FBLT

4430

ES61.

00k

0.03

Ω1W 15

8K

1.78

K

120p

F

L2 15µH

3085

EFFICIENCY (%)

8789919395

4050

60OU

TPUT

POW

ER (W

)70

80

48V I

N

24Ω

1/4W

12Ω

1/2W

Si74

56DP

–VOU

T

Si74

56DP

7 8

47µF

16V

×2

+22

0pF

220p

F

L3 33µH

24Ω

1/4W

12Ω

1/4W

V REF

CG

C T

•

2.7k

2.7k

MM

BD91

4M

MBD

914

8.66

k

MM

BT23

6950

k

1µF,

100

V TD

K C3

225X

7R2A

105M

(121

0)10

µF, 2

5V T

DK C

4532

X5R1

E106

M47

µF, 1

6V S

ANYO

16T

QC47

MD1

: MM

BZ52

29B

L1: C

OILC

RAFT

DO1

813P

-561

HCL2

: TDK

SLF

1257

5T-1

50M

4R7

L3: T

DK S

LF10

145T

-330

M1R

6L4

: COI

LCRA

FT D

O160

8C-1

05T1

: PUL

SE P

A104

0T2

: PUL

SE P

A078

5 (1

:0.5

T)

LTC3

723E

GN-1

DRVB

CS

COM

P

SDRB

V CC

UVLODR

VA

DPRG

V REF

SPRG

GND

SSFB

C TRL

EB

750Ω

22nF

V REF

V REF

680p

F

22nF

15nF

470p

F

4.7n

F

1k

LTC3

723-

1 36

V IN

to 7

2VIN

to 1

2V/5

A an

d –1

2V/1

.6A

Forw

ard

Conv

erte

r

LTC3723-1/LTC3723-2

18372312f

TYPICAL APPLICATIO S

U

5

46

AB

12V

V IN

15LT

C372

3EGN

-1

DRVB

SDRB

SDRA CO

MPCS

V CC

UVLO

9 150k

1

0.47

µF

1µF

DRVA

DPRG

V REF

SPRG

GND

SSFB

C T

330p

F

22nF

100k

D8 10V

68nF

270p

F

T2

1(1.

5mH)

:0.5

T14T

:6T(

65µH

MIN

):6T:

2T:2

T

243k

2.49

k

9.53

k10

k

750Ω

1k

100Ω

1/4W

813

3

Si73

70DP ×2

L4 1mH

C368

µF 20V

V FD2

••

32

819

54

16

10k

33k

200Ω

1/4W

R1 0.03

Ω1.

5W

66.5

k

RLEB 12

714

220p

F

22nF

100Ω

665Ω

1k86

6Ω

6.19

k1/

4W

1.5n

F

464k

30k

1/4W

SYNC

PVCC

CSF+

V F

LTC3

901E

GN

CSF–

8

1112

1

410

137

22nF

1µF

4.7µ

F

3723

12 T

A04

–VOU

TV O

UT

–VOU

T

D7 10V

V OUT

MF

MF2

GND

PGND

GND2

PGND

2TI

MERV C

C

470p

F

1415

1k86

6Ω

42.2

k1k

100Ω

6.19

k1/

4W

CSE+

V E–V

OUT

V OUT

V F

V OUT

12V/

20A

–VOU

T

CSE–

65

ME

ME2

23

16

Si73

70DP ×2

Si78

52DP

Si78

52DP

L50.

56µH

112 4

12V

D5 D6

3 5 1 6

•• • •

•9 7

V E

+

0.1µ

F

Si78

52DP

1

6 5

4

B

2

A

D3

LTC4

440E

S6BO

OST

INP

TGTS

GNDV C

C

12V

3

0.1µ

F

Si78

52DP

1

6 5

42

B

D4

LTC4

440E

S6BO

OST

INP

TGTS

GNDV C

C

12V

1µF

100V

×3

V IN

V IN

–VIN

42V

TO 5

6V1µ

F10

0V

C1, C

247

µF16

V×2

+

1µF

1µF

100V

1k 1/4W

1µF,

100

V TD

K C3

225X

7R2A

105M

C1,C

2: S

ANYO

16T

QC47

MC3

: AVX

TPS

E686

M02

0R01

50C4

: MUR

ATA

GHM

3045

X7R2

22K-

GCD2

: DIO

DES

INC.

ES1

BD3

-D6:

BAS

21D7

, D8:

MM

BZ52

40B

L4: C

OILC

RAFT

DO1

608C

-105

L5: C

OILC

RAFT

DO1

813P

-561

HCL6

: PUL

SE P

A129

4.13

2 OR

PA

NASO

NIC

ETQP

1H1R

0BFA

R1, R

2: IR

C LR

C251

2-R0

3GT1

: PUL

SE P

A080

5.00

4T2

: PUL

SE P

A078

5

6

10

I SNS

I SNS

0.1µ

F

11

5

1 21

MOC

207

C4 2.2n

F25

0V

0.1µ

F3

65

8

GND-

FV+ GND-

S

COLL

REF

LT14

31CS

8

A

1.5k

22Ω

4.7Ω

4.7Ω

R2 0.03

Ω1.

5W

V E

470p

F10

0V

L61.

25µH

10Ω

1W

693

EFFICIENCY (%)

94959697

810

12LO

AD C

URRE

NT (A

)14

1618

20

42V I

N

48V I

N

56V I

N

MM

BT39

04

•

LTC3

723-

1 24

0W 4

2VIN

to 5

6VIN

to 1

2V/2

0A Is

olat

ed 1

/4Br

ick

(2.3

" × 1

.45"

)

LTC3723-1/LTC3723-2

19372312f

PACKAGE DESCRIPTIO

U

GN Package16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

GN16 (SSOP) 0204

1 2 3 4 5 6 7 8

.229 – .244(5.817 – 6.198)

.150 – .157**(3.810 – 3.988)

16 15 14 13

.189 – .196*(4.801 – 4.978)

12 11 10 9

.016 – .050(0.406 – 1.270)

.015 ± .004(0.38 ± 0.10)

× 45°

0° – 8°TYP.007 – .0098

(0.178 – 0.249)

.0532 – .0688(1.35 – 1.75)

.008 – .012(0.203 – 0.305)

TYP

.004 – .0098(0.102 – 0.249)

.0250(0.635)

BSC

.009(0.229)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 ± .0015

.045 ±.005

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES(MILLIMETERS)

NOTE:1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

5

46

A B

12VVIN

15LTC3723EGN-1

DRVB SDRB SDRA

COMP

CSVCC

UVLO

9150k

1

0.47µF

1µF

DRVA

DPRG VREFSPRGGND SSFB CT

330pF68nF

270pF

T2

T129.46mm × 25.4mm × 10.2mm PLANAR

24.9k

813

3

HAT2169×2

L31mH

68µF20V

VF

• •

32

8

1 9

5

4

16

10k

33k

100Ω1/4W

R10.015Ω1.5W

66.5k

RLEB

127 14

220pF

100Ω

2.67k 2.67k

1.27k

4.53k

100pF

464k

30k1/4W

SYNC PVCC

CSF+

VF

LTC3901EGN

CSF–

8

11 12

1

4 10 13 71µF

4.7µF

372312 TA05

–VOUT

D110V

+VOUT

MF MF2

GND PGND GND2 PGND2 TIMER

VCC

470pF

14 15

1.27k

33.2k

1k

4.53k

CSE+

VE–VOUT

+VOUT

+VOUT

–VOUT

VF

+VOUT

–VOUT

CSE–6 5

ME ME2

2 3 16

HAT2169×2

L10.56µH

112

4

12V BAS21

ES1B

ES1B

BAS21

3

5

1

6

••

••

•

9

7

VE

+

0.1µFSi7370DP

1

6

5

4

B

2

A

BAS21

LTC4440ES6BOOSTINP

TGTSGND

VCC

12V

3

0.1µFSi7370DP

Si7370DP Si7370DP

1

6

5

42

B

BAS21

LTC4440ES6BOOSTINP

TGTSGND

VCC

12V1µF100V×3

VIN

VIN

–VIN

1µF100V

22µF25V×3

1µF, 100V TDK C3225X7R2A105M4.7µF, 25V TDK C4532X7R1E475M22µF, 25V TDK C4532X7R1E226MD1: MMBZ5240BD2: MMBZ5242BL1: COILCRAFT DO1813P-561HCL2: PULSE PA0513.441L3: COILCRAFT DO1608C-105T1: PULSE PA0901.004 (4:4:4:4CT)T2: PULSE PA0785 (1:0.5T)

10

ISNS

ISNS

0.1µF

4.7µF25V2x

11

A

100Ω

22Ω

4.7Ω4.7Ω

2.2nF250V

VE

1nF100V

0.33µF100V

L20.44µH

10Ω1W

57

8

9

OUTP

UT V

OLTA

GE (V

)

10

11

12

13

10 15LOAD CURRENT (A)

2520

42VIN

48VIN

53VIN

MMBT3904

•

D212V

MMBT3904

1.2k0.5W

591

92

93EFFI

CIEN

CY (%

)

94

95

96

97

10 15LOAD CURRENT (A)

2520

42VIN

48VIN

53VIN

5.1Ω1/4W

TYPICAL APPLICATIO S

U

LTC3723-1 300W 42VIN to 56VIN to 12V/25A Isolated Bus Converter

LTC3723-1/LTC3723-2

20372312f

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003

LT 1105 PRINTED IN USA

RELATED PARTSPART NUMBER DESCRIPTION COMMENTSLT®1952 Single Switch Synchronous Forward Controller High Efficiency, Adjustable Volt-Second Clamp, True PWM Soft-StartLTC3705/LTC3706/ Isolated Power Supply DC/DC Converter Chipset Simple as Buck Circuit, No Opto-Coupler, Fast Transient Response,LTC3725/LTC3726/ PolyPhase® Operation Capability, Scalable for Higher PowerLTC3722-1/LTC3722-2 Dual Mode Phase Modulated Full-Bridge Controllers ZVS Full-Bridge ControllersLT3804 Secondary-Side Dual Output Controller with Opto Driver Regulates Two Secondary Outputs; Optocoupler Feedback Driver and

Second Output Synchronous Driver ControllerLTC3901 Secondary-Side Synchronous Driver for Push-Pull and Drives N-Channel Synchronous MOSFETs, Programmable Timeout,

Full Bridge Converters Reverse Current LimitLT4430 Secondary-Side Optocoupler Driver Overshoot Control on Start-Up and Short-Circuit Recovery,

600mV Reference, ThinSOT™ PackageLTC4440 High Speed High Voltage High Side Gate Driver 80V Operation, 100V Tolerant, 1.5Ω Pull-Down, 2.4A Pull-UpPolyPhase is a registered trademark of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation.

TYPICAL APPLICATIO

U

LTC3723-1 100W, 36VIN to 72VIN to 3.3V/30A Isolated Forward Converter

1

VB

5

46

A

A

10VVIN

15LTC3723EGN-1

DRVB CS

COMP

SDRB

VCC

UVLO

9150k

1

0.47µF

1µF

DRVA

DPRG VREF

VREF

SPRGGND SS FBCT

CT

220pF68nF

T2

T123.4mm × 20.1mm × 9.4mm PLANAR

6.04k

27.4k

8 13

L31mH

68µF20V

• •

10 8

1 8

5

4

16

10k

33k

150Ω1/4W

66.5k

RLEB

820Ω

127 14

560Ω

100pF

383k

30kSYNC TIMERLTC3900ES8

6

7

1nF 0.47µF25V

372312 TA06

VOUT

VOUT

VIN

–VOUT

FG

GND

VCC

5

562Ω

845Ω

26.1kCS+

VB

VX

VX

VOUT

CS–1 2

CG

3 4

L10.33µH

10V BAS21

BAS21

35

24

••

1

6

•+

Si7450DP

1µF100V×2

VIN

VIN

–VIN

2.2nF630V

1µF100V

6

2

220pF

2.2nF250V

11

5

1

26

MOC207

2

4

GND

3

OCOPTOFBLT4430ES6

VIN

1.00k15Ω1/4W

0.03Ω1W

120K

820Ω

120pF

4.7nF

586

EFFI

CIEN

CY (%

)

87

89

91

88

90

92

93

94

10 15 20LOAD CURRENT (A)

25 30

48VIN

Si7336ADP×2

–VOUT

–VOUT

VOUT

Si7336ADP×2

7

8

470µF6.3V

+

L20.85µH

VREFVREF

VREF

CT

•

10

11

•

B0540W

B0540W

8.66k

MMBT236950k

1µF, 100V TDK C3225X7R2A105M (1210)100µF, 6.3V TDK C3225X5R0J107M (1210)2.2nF, 630V TDK C3216JB2J222K470µF, 6.3V SANYO 6TPD470MD1: MMBZ5240BL1: COILCRAFT DO1813P-331HCL2: PULSE PA1292.910L3: COILCRAFT DO1608C-105T1: PULSE PA810.007 (7:6:6:1:1:1T)T2: PULSE PA0184 (1:1T)

D110V

5COMP

330Ω4.7nF

47nF

470pF

1k

10nF

330Ω

2.2nF

100µF6.3V

×25.1Ω1/2W2.2nF

5.1Ω1/2W

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.:

LTC3723EGN-1 LTC3723EGN-2#TR LTC3723EGN-2 LTC3723EGN-2#TRPBF LTC3723EGN-2#PBF

LTC3723EGN-1#PBF LTC3723EGN-1#TRPBF LTC3723EGN-1#TR