Logic Design II (17.342) Spring 2012 Lecture Outlinefaculty.uml.edu/dbowden/ClassPages/2012_Spring_CSO/17-342/Ref... · A Sequential Parity Checker ... – The state graph for a Mealy

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Logic Design II (17.342)

Spring 2012

Lecture Outline

Class # 05

February 23, 2012

Dohn Bowden

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Today’s Lecture

• Analysis of Clocked Sequential Circuits … Chapter 13

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Course Admin

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Administrative

• Admin for tonight … – Syllabus review

• Lab #1 is due TONIGHT … February 23rd • Exam # 1 … NEXT WEEK … March 1st

– Covers … Chapters 11 and 12 » Intro to sequential circuits » Latches and flip-flops » Registers and Counters

– Open book/open notes exam

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Syllabus Review

Week Date Topics Chapter Lab Report Due

1 01/26/12 Review of combinational circuits 1-10

2 02/02/12 Intro to sequential circuits. Latches and flip-flops 11

3 02/09/12 Registers and Counters 12

4 02/16/12 Registers and Counters … continued 12

5 02/23/12 Analysis of Clocked Sequential Circuits 13 1

6 03/01/12 Examination 1

7 03/08/12 Derivation of State Graphs and Tables 14

X 03/15/12 NO CLASSES – Spring Break

8 03/22/12 Reduction of State Tables State Assignments 15 2

9 03/29/12 Sequential Circuit Design 16

10 04/05/12 Circuits for Arithmetic Operations 18

11 04/12/12 Examination 2 3

12 04/19/12 State Machine Design with SM Charts 19

13 04/26/12 Course Project – Build/Troubleshoot in Lab Project 4

14 05/03/12 Final Exam/Course Project Brief & Demo Demo

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Questions?

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Chapter 13 …

ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS

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Objectives

Objectives

1. Analyze a sequential circuit by signal tracing

2. Given a sequential circuit … write the next-state equations for the flip-flops … and … derive the state graph or state table – Using the state graph … determine the state sequence and

output sequence for a given input sequence

3. Explain the difference between … a Mealy machine … and … a Moore machine

4. Given a state table … construct the corresponding state graph … and … conversely

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Objectives

5. Given a sequential circuit or a state table and an input sequence … – Draw a timing chart for the circuit

– Determine the output sequence from the timing chart …

neglecting any false outputs

6. Draw a general model for a clocked Mealy … or … Moore sequential circuit … – Explain the operation of the circuit in terms of these models

– Explain why a clock is needed to ensure proper operation of the

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Analysis of Clocked Sequential Circuits


• Counter designs thus far … were … – Fixed sequence of states – No inputs other than a clock pulse that causes the state to

change

• Will now consider sequential circuits that have additional inputs – Circuit outputs and flip-flop states will now depend on the input

sequence which is applied to the circuit

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• Flip-flop state and output sequence can be determined by … – Signal tracing (small circuits)

– Construction of state graph or state table

• The output and state sequences can be determine

• Also they are useful for the design of sequential circuits

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A Sequential Parity Checker


• Parity bit …

– An extra bit added for purposes of error detection when binary data is transmitted or stored

• Odd parity … the total number of 1 bits in the block … including the parity bit … is odd

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Example


• Example … if data is being transmitted in groups of 7 bits … an eighth bit can be added to each group of 7 bits to make the total number of 1′s in each block of 8 bits an odd number …

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Design a Parity Checker Circuit


• Design a parity checker such that … – Serial data input – Clock input – Output of the circuit should be Z = 1 if the total number of 1

inputs received is odd – Z = 0 indicates that an error in transmission has occurred

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• Design a parity checker … – Block diagram

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• Design a parity checker … – X is read at the time of the active clock edge – X input must be synchronized with the clock so that it assumes

its next value before the next active clock edge • Clock required to distinguish consecutive 0's or 1's on the X

input

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• Design a parity checker … – X is read at the time of the active clock edge – X input must be synchronized with the clock so that it assumes

its next value before the next active clock edge • Clock required to distinguish consecutive 0's or 1's on the X

input • Typical input and output waveforms

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• Design a parity checker … – Typical input and output waveforms

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• Design a parity checker … – Construct a state graph … – Circuit must "remember" whether the total number of 1 inputs

received is even or odd … • Therefore … two states are required

– Designate these states as S0 … even … and S1 … odd number of 1 's received

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• Design a parity checker … – Construct a state graph … – Circuit must "remember" whether the total number of 1 inputs

received is even or odd … • Therefore … two states are required

– Designate these states as S0 … even … and S1 … odd number of 1 's received

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• Design a parity checker … – Start in state S0 … initially zero 1's have been received

• If the circuit is in state S0 … even number of 1's received … and … X = 0 is received …

– The circuit must stay in S0 because the number of 1's received is still even

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• Design a parity checker … – If … X = 1 is received … the circuit goes to state S1 because the

number of 1's received is then odd

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• Design a parity checker … – If … in state S1 … odd number of 1's received … – A zero input causes no state change – A one causes a change to S0 because the number of 1's received

is then even

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• Design a parity checker … – Z should be 1 whenever the circuit is in state S1 … odd number

of 1's received – The output is listed below the state on the state graph

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• Design a parity checker … – Create a State Table from the State Graph …

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• Design a parity checker … – Create a State Table from the State Graph …

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• Design a parity checker … – If the present state is S0 …

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• The output is Z = 0

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• The output is Z = 0 … and … • If the input is X= 1 …

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• The output is Z = 0 … and … • If the input is X= 1 … the next state will be S1

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• Design a parity checker … – Only two states … therefore a single flip-flop (Q) is needed – Use a T Flip-flop

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• Design a parity checker … – Q = 0 correspond to S0 – Q = 1 correspond to S1

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– Table shows the next state of flip-flop Q as a function of the present state and X

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– For T flip-flop … T = 1 whenever Q and Q+ differ

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– For T flip-flop … T = 1 whenever Q and Q+ differ – T input must be 1 whenever X= 1

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• Design a parity checker … – When X = 1 … the flip-flop changes state after the falling edge

of the clock

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• Design a parity checker … – Final value of Z is 0 …

• Because an even number of 1 's was received

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• Design a parity checker … – If … the final value of Z = 1 …

• The flip-flop would need to be reset prior to next sequence

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Analysis by Signal Tracing

and Timing Charts

Analysis by Signal Tracing and Timing Charts

• We can analyze clocked sequential circuits to find the output sequence resulting from a given input sequence by … – Tracing 0 and 1 signals through the circuit

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• The basic procedure to analyze the circuit is … 1. Assume an initial state of the flip-flops …

All flip-flops reset to 0 unless otherwise specified

2. For the first input in the given sequence … determine the circuit output(s) … and … flip-flop inputs

3. Determine the new set of flip-flop states after the next active clock edge

4. Determine the output(s) that corresponds to the new states

5. Repeat … 2 … 3 … and … 4 for each input in the sequence 46


• For the analysis … – Construct a timing chart which shows the relationship between

the …

• Input signal … the clock … the flip-flop states … and the circuit output

– The circuit output may change at the time the flip-flops change state … or … at the time the input changes

• Depends on the type of circuit

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Types of Clocked Sequential Circuits

Types of Clocked Sequential Circuits

• Two types of clocked sequential circuits … – First … the output depends only on the present state of the flip-

flops

– Second … those in which the output depends on both the …

• Present state of the flip-flops … and …

• On the value of the circuit inputs

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Moore Machine

Moore Machine

• Moore machine … – Output of a sequential circuit is a function of the present state

only

– Two examples …

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Moore Machine

• Moore machine … – The state graph for a Moore machine has the output associated

with the state

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Mealy Machine

Mealy Machine

• Mealy machine … – Output is a function of both the present state and the input

– Example …

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Mealy Machine

• Mealy machine … – The state graph for a Mealy machine has the output associated

with the arrow going between states

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Example Moore Circuit Analysis

Moore Circuit Analysis

• Analyze the circuit below … input sequence X = 01101 … Initial state is A = B = 0 … and … all state changes occur after the rising edge of the clock … X input is synchronized with the clock so that it assumes its next value after each rising edge

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• Analyze the circuit below … input sequence X = 01101 … Initial state is A = B = 0

• Z is a function only of the present state … Z = A B … output will only change when the state changes … Moore Circuit!

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• RECALL … The basic procedure to analyze the circuit is … 1. Assume an initial state of the flip-flops …

All flip-flops reset to 0 unless otherwise specified

2. For the first input in the given sequence … determine the circuit output(s) … and … flip-flop inputs

3. Determine the new set of flip-flop states after the next active clock edge

4. Determine the output(s) that corresponds to the new states

5. Repeat … 2 … 3 … and … 4 for each input in the sequence 59



• Initially … X = 0 … so DA = 1 … and … DB = 0 • The state will change to A = 1 and B = 0 after the first rising clock

edge

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• When the circuit is reset to its initial state … A = B = 0 … the initial output is Z = 0 … because this initial 0 is not in response to any X input … it should be ignored

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• Analyze the circuit below … input sequence X = 01101 • Then X changes to 1 ... so DA = 0 … DB = 1 and the state changes

to AB = 01 after the second rising clock edge

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• Analyze the circuit below … input sequence X = 01101 • After the state change … X remains 1 … so DA = DB = 1 … and the

next rising edge causes the state to change to 11

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• Analyze the circuit below … input sequence X = 01101 • When X changes to 0 … DA = 0 and DB = 1 … and the state

changes to AB = 01 on the fourth rising edge

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• Analyze the circuit below … input sequence X = 01101 • Then … with X= 1 … DA= DB = 1 … so the fifth rising clock edge

causes the state to change to AB = 11

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• Analyze the circuit below … input sequence X = 01101 • The resulting output sequence … Z = 11010

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Example Mealy Circuit Analysis

Mealy Circuit Analysis

• Analyze the circuit below … input sequence X= 10101 • The input is synchronized with the clock so that input changes

occur after the falling edge

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• Analyze the circuit below … input sequence X= 10101 • The output depends on both the input .. X … and the flip-flop

states … A … and … B … so … Z … may change either when the input changes or when the flip-flops change state

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• Analyze the circuit below … input sequence X= 10101 • Initially … flip-flop states are … A = 0 … B = 0 … If X= 1 … the

output is Z = 1 … and … JB = KA = 1

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• Analyze the circuit below … input sequence X= 10101 • After the falling edge of the first clock pulse … B changes to 1 … so

Z changes to 0 … If the input is changed to X = 0 … Z will change back to 1

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• Analyze the circuit below … input sequence X= 10101 • Flip-flop inputs = 0 ... so no state change occurs with the second

falling edge … When X is changed to 1 … Z becomes 0 … and … JA = KA = JB = 1

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• Analyze the circuit below … input sequence X= 10101 • A changes to 1 on the third falling clock edge … Z changes to 1

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• Analyze the circuit below … input sequence X= 10101 • X is changed to 0 … Z becomes 0 … and no state change occurs

with the fourth clock pulse

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• Analyze the circuit below … input sequence X= 10101 • X is changed to 0 … Z becomes 0 … and no state change occurs

with the fourth clock pulse

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• Analyze the circuit below … input sequence X= 10101 • X is changed to 1 … Z becomes 1 … Because

JA = KA = JB = KB = 1 … the fifth clock pulse returns the circuit to the initial state

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• For Mealy circuits … After the circuit has changed state and before the input is changed … the output may temporarily assume an incorrect value … which we call a false output

• False value arises when … the circuit has assumed a new state but the old input associated with the previous state is still present

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False Outputs

• Moore circuit can change slate only when the Flip-flops change state and not when the input changes … therefore … – No false outputs can appear in a Moore circuit

• False outputs are often referred to as glitches and spikes

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State Tables and Graphs


• Previous analysis works for small circuits and short input sequences

• However … the construction of state tables and graphs provides a more systematic approach which is useful for the analysis of larger circuits and which leads to a general synthesis procedure for sequential circuits

• State table specifies the … next state … and … output of a sequential circuit in terms of …

– Its present state and input

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The following method can be used to construct the state table …

1. Determine the flip-flop input equations and the output equations from the circuit

2. Derive the next-state equation for each flip-flop from its input equations … using one of the following relations …

• D flip-flop Q+ = D (13-1)

• D-CE flip-flop Q+ = D•CE + Q•CE′ (13-2)

• T flip-flop Q+ = T Q (13-3)

• S-R flip-flop Q+ = S + R′Q (13-4)

• J-K flip-flop Q+ = JQ′ + K′Q (13-5)

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3. Plot a next-state map for each flip-flop

4. Combine these maps to form the state table • Such a state table … which gives the next state of the flip-

flops as a function of their present state and the circuit inputs … is frequently referred to as a transition table

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Example State Tables and Graphs


• Example … derive the state table for the circuit below …

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• Example con’t … derive the state table for the circuit below …

Moore sequential circuit …

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1. The flip-flop input equations and output equation are…

DA = X B′ DB = X + A Z = A B

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2. The next-state equations for the flip-flops are

A+ = X B′ B+ = X + A

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3. The corresponding maps are …

A+ = X B′ B+ = X + A

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• Recall … the next-state map for each flip-flop are combined to form the state table (transition table) …

• The state table … gives … – The next state of the flip-flops as a function of their

present state and the circuit inputs

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4. Combine the state maps to form the transition table … which gives the next state of both flip-flops (A+B+) as a function of the present state and input

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A+B+ AB X=0 X=1 Z 00 10 01 0 01 00 11 1 11 01 11 0 10 11 01 1



4. con’t … the output function Z is then added to the table … in this example … the output depends only on the present state of the flip-flops and not on the input … so only a single output column is required Z = A B

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A+B+ AB X=0 X=1 Z 00 10 01 0 01 00 11 1 11 01 11 0 10 11 01 1



4. Let AB = 00 correspond to circuit state S0 … 01 to S1 … 11 to S2 … and … 10 to S3

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A+B+ AB X=0 X=1 Z 00 10 01 0 01 00 11 1 11 01 11 0 10 11 01 1

Present Next State Present State X = 0 X = 1 Output(Z)

S0 S3 S1 0 S1 S0 S2 1 S2 S1 S2 0 S3 S2 S1 1



4. Let AB = 00 correspond to circuit state S0 … 01 to S1 … 11 to S2 … and … 10 to S3

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A+B+ AB X=0 X=1 Z 00 10 01 0 01 00 11 1 11 01 11 0 10 11 01 1


S0 S3 S1 0 S1 S0 S2 1 S2 S1 S2 0 S3 S2 S1 1



4. Construct State Graph …

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S0 S3 S1 0 S1 S0 S2 1 S2 S1 S2 0 S3 S2 S1 1



4. Each node represents a state of the circuit …

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S0 S3 S1 0 S1 S0 S2 1 S2 S1 S2 0 S3 S2 S1 1



4. Each node represents a state of the circuit … corresponding output is placed in the circle below the state symbol …

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S0 S3 S1 0 S1 S0 S2 1 S2 S1 S2 0 S3 S2 S1 1



4. Each node represents a state of the circuit … corresponding output is placed in the circle below the state symbol … the arc joining two nodes is labeled with the value of X … which will cause a state change between these nodes

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S0 S3 S1 0 S1 S0 S2 1 S2 S1 S2 0 S3 S2 S1 1


• Example … FINAL … derive the state table for the circuit below …

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S0 S3 S1 0 S1 S0 S2 1 S2 S1 S2 0 S3 S2 S1 1

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• Example … derive the state table for the circuit below …

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Mealy sequential circuit …

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1. The flip-flop input equations and output equation are…

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2 ... We can construct the next-state and output equations from the circuit diagram …

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2 ... We can construct the next-state and output equations from the circuit diagram …

A+ = JAA′ + K′AA = XBA′ + X′A

B+ = JBB′ + K′BB = XB′ + (AX)′B = XB′ + X′B + A′B

Z = X′A′B + XB′ + XA

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3. The corresponding maps are …

A+ = JAA′ + K′AA = XBA′ + X′A

B+ = JBB′ + K′BB = XB′ + (AX)′B = XB′ + X′B + A′B

Z = X′A′B + XB′ + XA

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4. con’t … Combine the state maps to form the transition table …

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4. con’t … Let AB = 00 correspond to circuit state S0 … 01 to S1 … 11 to S2 … and … 10 to S3

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4. con’t … Construct State Graph … input/output

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• Example … FINAL … derive the state table for the circuit below …

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Serial Adder Analysis

• Analyze the operation of a serial adder … that adds two n-bit binary numbers xi … and … yi

• Serial adder is similar to the parallel adder … except that the binary numbers are fed in serially … one pair of bits at a time … and … the sum is read out serially … one bit at a time

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• Analyze the operation of a serial adder …

• First … x0 and y0 are fed in … a sum digit s0 is generated … and the carry c1 is stored

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• Analyze the operation of a serial adder …

• At the next clock time … x1 and y1 are fed in and added to c1 to give the next sum digit s1 and the new carry c2 … which is stored

• This process continues until all bits have been added

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• Analyze the operation of a serial adder … • A full adder is used to add the xi, yi and ci bits to form ci+1 and si

• A D flip-flop is used to store the carry (ci+1) on the rising edge of

the clock. The xi and yi inputs must be synchronized with the clock

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• Analyze the operation of a serial adder … timing diagram for the serial adder … Example … add 10011 + 00110 to give a sum of 11001 and a final carry of 0

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• Analyze the operation of a serial adder … truth table for the full adder …

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• Analyze the operation of a serial adder … construct a state graph …

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Example Mealy Sequential Circuit

With Two Inputs/Outputs

Mealy Sequential Circuit With Two Inputs/Outputs

• State table for a Mealy sequential circuit with two inputs and two outputs … along with corresponding state graph

• The notation 00,01/00 on the arc from S3 to S2 means … if … X1 = X2 = 0 or X1 = 0 and X2 = 1 … then Z1 = 0 and Z2 = 0

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Construction and Interpretation of Timing Charts


• Several important points concerning the construction and interpretation of timing charts are … 1. When constructing timing charts … note that a state change

can only occur after the rising (or falling) edge of the clock

2. The input will normally be stable immediately before and after the active clock edge

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3. For a Moore circuit … The output can change only when the state changes For a Mealy circuit … The output can change when the input changes as well as when the state changes A false output may occur between the time the state changes and the time the input is changes to its new value

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4. False outputs are difficult to determine from the state graph … So use either signal tracing through the circuit … or … Use the state table when constructing timing charts for Mealy circuits

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5. When using a Mealy state table for constructing timing charts … the procedure is as follows …

(a) For the first input … read the present output and plot it

(b) Read the next state and plot it … following the active edge of the clock pulse

(c) Go to the row in the table which corresponds to the next state and read the output under the old input column and plot it … this may be a false output

(d) Change to the next input and repeat steps (a) … (b) … and … (c)

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6. For Mealy circuits … the best time to read the output is just before the active edge of the clock … Because the output should always be correct at that time A “false” output may occur after the state has changed and before the input has changed

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Example

Example

• The following example shows the relationships among the …

– State graph …

– State table

– Circuits … and …

– Timing chart

• The input sequence is …

X = 0 1 0

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FINAL X = 0 1 0 Z = 1 1 0

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PREVIEW Synthesis Procedure

PREVIEW --- Synthesis Procedure

• The synthesis procedure for sequential circuits … – Opposite of the procedure used for analysis

• Starting with the specifications for the sequential circuit to be synthesized …

– A state graph is constructed – This graph is then translated to a state table … and … – The flip-flop output values are assigned for each state – The flip-flop input equations are then derived – The logic diagram for the circuit is drawn

– Will be discussed in Chapters 14 - 16

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General Models for Sequential Circuits


• A sequential circuit can be divided conveniently into two parts …

– The flip-flops which serve as memory for the circuit … and …

– The combinational logic which realizes the input functions for the flip-flops … and … the output functions

• The combinational logic may be implemented with …

– Gates

– With a ROM … or …

– With a PLA 151


• This circuit is a general model for a clocked Mealy sequential circuit with … – m inputs … n outputs … and

… k clocked D flip-flops used as memory

• This model emphasizes the presence of feedback in the sequential circuit because the flip-flop outputs are fed back as inputs to the combinational subcircuit

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Clock Synchronization


• The clock synchronizes the operation of the flip-flops and prevents timing problems

• Gates in the combinational subcircuit have finite propagation delays – Finite time is required before the flip-flop inputs reach their final

values

• Gate delays are not all the same

• If the next active clock edge does not occur until all flip-flop input signals have reached their final steady-state values … – The unequal gate delays will not cause any timing problems

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• All flip-flops which must change state do so at the same time in response to the active edge of the clock

• When the flip-flops change state … – The new flip-flop outputs are fed back into the combinational

subcircuit

• No further change in the flip-flop states can occur until the next clock pulse

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Minimum Clock Period (Sequential Circuit)

Minimum Clock Period - Sequential Circuit

• We can determine the fastest clock speed … which is also the minimum clock period … from the general model of the Mealy circuit

• Following the active edge of the clock … the flip-flops change state … and the flip-flop output is stable after the propagation delay (tp)

• The new values of Q then propagate through the combinational circuit so that the D values are stable after the combinational circuit delay (tc)

• Then … the flip-flop setup time (tsu) must elapse before the next active clock edge

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• Thus … the propagation delay in the flip-flops … the propagation delay in the combinational subcircuit … and … the setup time for the flip-flops determine how fast the sequential circuit can operate … and … the minimum clock period is …

• tclk (min) = tp + tc + tsu

• This assumes that the X inputs are stable no later than tc + tsu before the next active clock edge … If this is not the case … then we must calculate the minimum clock period by …

• tclk (min) = tx + tc + tsu

• Where tx is the time after the active clock edge at which the X inputs are stable

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General Model Clocked Moore Circuit

General Model - Clocked Moore Circuit

• The general model for the clocked Moore circuit is similar to the clocked Mealy circuit …

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• The output subcircuit is drawn separately … as the output is only a function of the present state of the flip-flops and not a function of the circuit inputs …

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• The Moore circuit is similar to that of the Mealy except … when inputs applied … resulting outputs do not appear until after the clock causes the flip-flops to change state …

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• For sequential circuits with multiple inputs and outputs … symbols represent each combination of input and output values

• Example below …

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• Let X = 0 represent input combination X1X2 = 00 • Let X= 1 represent X1X2 = 01 … etc • Same representation with Z …

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• With these representations … we can specify the behavior of any sequential circuit in terms of … – A single input variable X … and …

– A single output variable Z

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• Table below specifies two functions … the next-state function … and … the output function

• The next-state function … designated (delta) gives the next state of the circuit … the state after the clock pulse … in terms of the present state (S) … and … the present input (X) …

S+ = (S, X)

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• The output function … designated λ (lambda) … gives the output of the circuit (Z) in terms of the present state (S) and input (X) …

Z = λ (S, X)

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• Values of S+ and Z can be determined from the state table …

• From the table …

Next State … Output …

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Lab

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LABS

• Lab #1 is due TONIGHT … February 23rd

• Lab #2 will be available on March 8th – Due date MAY change from current due date on the syllabus

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Next Week …

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Next Week Topics

• Exam #1

• In two weeks … Chapter 14 … Derivation of State Graphs and Tables

• Pages 427 –

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Home Work

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Homework

1. Exam #1 preparation

2. Read …

– Due in two weeks … Chapter 14 … Derivation of State Graphs and Tables

– Pages 427 –

Documents

Logic Design II (17.342) Spring 2012 Lecture Outlinefaculty.uml.edu/dbowden/ClassPages/2012_Spring_CSO/17-342/Ref... · A Sequential Parity Checker ... – The state graph for a Mealy