Logic Design I (17.341) Fall 2011 Lecture Outlinefaculty.uml.edu/dbowden/ClassPages/2011_Fall_KCS/17-341/Ref_Documents... · 1 Logic Design I (17.341) Fall 2011 Lecture Outline Class

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Logic Design I (17.341)

Fall 2011

Lecture Outline

Class # 11

November 28, 2011

Dohn Bowden

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Today’s Lecture

• Administrative

• Main Logic Topic

• Homework

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CourseAdmin

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Administrative

• Admin for tonight …

– Syllabus Review

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Syllabus

• Syllabus

– Lecture changes … see syllabus

– Lab due dates …

• Lab #1 Due tonight … 11/28/11• Lab #2 Due … 12/12/11

– Exam #3 is next week … 12/05/11

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Syllabus ReviewWeek Date Topics Chapter Lab Report Due

1 09/12/11 Introduction to digital systems and number systems 1

2 09/19/11 Binary Codes and Boolean Algebra 2

3 09/26/11 Boolean Algebra (continued) 3

4 10/03/11 Examination 1

X 10/10/11 No Class - Holiday

5 10/17/11 Application of Boolean Algebra 4

6 10/24/11 Karnaugh Maps and 5

7 10/31/11 Multi-Level Gate Circuits and Lab lecture 7


9 11/14/11 Combinational Circuit Design and Simulation Using Gates

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10 11/21/11 Multiplexers, Decoders. Encoder, and start PLD 9

11 11/28/11 Programmable Logic Devices 10 1


13 12/12/11 Introduction to VHDL and Final Review 2

14 12/19/11 Final Exam

Exam #2

• Will be returned at the end of class tonight

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Questions?

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Chapter 9 …

MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC

DEVICES

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Programmable Logic Devices


• A programmable logic device … or … PLD …

– A general name for a digital integrated circuit capable of being programmed to provide a variety of different logic functions

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• For digital system is designed using a PLD …

– Changes in the design can easily be made by …

• Changing the programming of the PLD …

– Without having to change the wiring in the system

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Programmable Logic Arrays


• Programmable logic array … PLA

• Performs the same basic function as a ROM

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• A PLA with n inputs and m outputs can realize m functions of nvariables

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• The internal organization of the PLA is different from that of the ROM in that …

– The decoder is replaced with an AND array which realizes selected product terms of the input variables

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• The OR array …

– ORs together the product terms needed to form the output functions …so …

• A PLA implements a sum-of-products expression

• A ROM directly implements a truth table

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• PLA which realizes the same functions as the ROM we discussed last time … larger images on next two slides

ROM PLA

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• ROM

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• PLA … Three Inputs … Five Product Terms … and … Four Outputs

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• Product terms are formed in the AND array by connecting switching elements at appropriate points in the array

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• To form A’ B’ … – Switching elements are used to connect the first word line with

the A’ … and … B’ lines• Switching elements are

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<Unknown User>

Pencil


• Switching elements are connected in the OR array to select the product terms needed for the output functions

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• Example … because F0 = A’B’ + AC’ …– Switching elements are used to connect the A’ B’ … and … AC’

lines to the F0 line

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• The connections in the AND … and … OR arrays of this PLA make it equivalent to the AND- OR array below

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• The contents of a PLA can be specified by a PLA table …

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• The input side of a PLA table defines the product terms generated by the AND array …

• 0 indicates a complemented variable1 indicates an uncomplemented variable− indicates a missing variable

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• The output side of a PLA table specifies which product terms are ORed together to form the output functions …

• 0 indicates a product term is not present1 indicates a product term is present

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• Unlike a truth table … zero … one … or more rows in a PLA table can be selected at the same time

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• Table below specifies the shown PLA

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Example …


• Example … Realize the following using a PLA …

f1 = a’bd + abd + ab’c’ +b’c f2 = c + a’bd f3 = bc + ab’c’ + abd

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• Construct a PLA Table …

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• Develop PLA Structure …

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• Four inputs …

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• Six product terms …

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• Three outputs …

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• A dot represents a switching element …

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Programmable Array Logic


• Programmable Array Logic … PAL

• The PAL is a special case of the PLA in which …

– The AND array is programmable and the OR array is fixed

• Because only the AND array is programmable …

– The PAL is less expensive than the more general PLA … and …

• The PAL is easier to program

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• The following two symbols are logically equivalent …

• A buffer is used since each PAL input drives many AND gate outputs

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• Gates below are equivalent …

• Connections to the AND gate inputs in a PAL are represented by …

– A … X’s

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Example …


• Example … Using a PAL … realize the function … I1I’2 + I’1I2

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Unlike PLAs … the AND terms cannot be shared amongst two or more OR gates … therefore …

Simplify logic equations

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Example …


• Example … Using a PAL … implement a full adder

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• Example … Using a PAL … implement a full adder

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Sum = X’Y’Cin + X’YC’in + XY’C’in + XYCin

Cout = XCin + YCin + XY

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Complex Programmable Logic Devices


• As integrated circuit technology continues to improve …

– More and more gates can be placed on a single chip

• This has allowed the development of …

– Complex programmable logic devices … CPLDs ...

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• Instead of a single PAL or PLA on a chip …

– Many PALs or PLAs can be placed on a single CPLD chip and interconnected

• When storage elements such as flip-flops are also included on the same integrated circuit (IC) …

– A small digital system can be implemented with a single CPLD

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• For example … the following is the basic architecture of …

– Xilinx XCR3064XL CPLD

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• This CPLD has … four function blocks– Each block has 16 associated macrocells … MC1 … MC2 . . .

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• Each function block is a programmable AND- OR array that is configured as a PLA

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• Each macrocell contains a flip- flop and multiplexers that route signals from the function block to the input-output (I/O) block or to the interconnect array (IA)

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<Unknown User>

Pencil


• The IA selects signals from the macrocell outputs or I/O blocks and connects them back to function block inputs

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• Thus … a signal generated in one function block can be used as an input to any other function block

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• The I/O blocks provide an interface between the bi-directional I/O pins on the IC and the interior of the CPLD

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CPLD Function Block and Macrocell

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Signals generated in a PLA can be routed to an I/O pin through a macrocell

<Unknown User>

Pencil

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Field-Programmable Gate Arrays


• Field-Programmable Gate Array … FPGA

– Is an IC that contains an array of identical logic cells with programmable interconnections

• The user can program the functions realized by each logic cell and the connections between the cells

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• The interior of the FPGA consists of …

– An array of logic cells … also called configurable logic blocks … CLBs

• The array of CLBs is surrounded by a ring of I/O interface blocks

• The I/O blocks connect the CLB signals to IC pins

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Layout of a Typical FPGA

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Simplified Configurable Logic Block (CLB)

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Two function generators … implemented as lookup tables … LUT


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Two flip- flops


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Multiplexers for routing signals within the CLB


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Each function generator has four inputs and can implement any function of up to four variables.


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The function generators are A four-input LUT … essentially a reprogrammable ROM with 16 1-bit words

This ROM stores the truth table for the function being generated.


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The H multiplexer selects either F or G depending on the value of H1

<Unknown User>

Pencil


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The CLB has two combinational outputs … X and Y


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Two flip- flop outputs … XQ and YQ


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The X and Y outputs and the flip-flop inputs are selected by programmable multiplexers

The select inputs to these MUXes are programmed when the FPGA is configured

Implementation of a Lookup Table (LUT)

• A four-input LUT is essentially a reprogrammable ROM with 16 1-bit words

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abcd F 0000 0 0001 1

• • • • • •

1111 1

Implementation of a Lookup Table (LUT)

• Implementation of a function generator with inputs a, b, c, d• The numbers in the squares represent the bits stored in the LUT• These bits enable particular minterms• A function with only one minterm or with as many as 15 minterms

requires a single function generator … because it’s a truth table

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abcd F 0000 0 0001 1

• • • • • •

1111 1

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Shannon′s Expansion Theorem


• In order to implement a switching function of more than four variables using 4-variable function generators …

– The function must be decomposed into subfunctions where each subfunction requires only three variables

• For example, we can expand a function of the variables a, b, c, and d about the variable a:

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• Example … we can expand a function of the variables a, b, c, and dabout the variable a …

f (a, b, c, d) = a'f (0, b, c, d) + a f (1, b, c, d) = a'f0 + a f1

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<Unknown User>

Pencil


• Example … we can expand a function of the variables a, b, c, and dabout the variable a …

f (a, b, c, d) = a'f (0, b, c, d) + a f (1, b, c, d) = a'f0 + a f1

f (a, b, c, d) = c'd'+ a'b'c + bcd + ac'

= a‘ (c'd'+ b’c + bcd) + a(c'd'+ bcd + c‘ )

= a‘ (c'd'+ b'c + cd) + a(c'+ bd) = a'f0 + a f1

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<Unknown User>

Pencil


• Function Expansion Using a Karnaugh Map …

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• The general form of Shannon’s expansion theorem for expanding an n-variable function about the variable xi is

f (x1, x2, . . . , xi−1, xi, xi+1, . . . , xn)= xi′ f (x1, x2, . . . , xi−1, 0, xi+1, . . . , xn) +

xi f (x1, x2, . . . , xi−1, 1, xi+1, . . . , xn)= xi′ f0 + xi f1

• Where f0 is the (n − 1)-variable function obtained by setting xi to 0 in the original function and f1 is the (n − 1)-variable function obtained by setting xi to 1 in the original function

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<Unknown User>

Pencil


• Realization of a 5-Variable Function with Function Generators and a MUX …

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<Unknown User>

Pencil


• Realization of a 6-Variable Function with Function Generators and a MUX …

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G(a, b, c, d, e, f)= a'G0 + aG1

G0 = b'G00 + bG01

G1 = b'G10 + bG11

<Unknown User>

Pencil

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Exam # 2 and Exam # 3

Exam #2

• Pass back Exam #2

• Exam #3 … next week …

– Open Book … open notes

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Lab

Lab

• Lab #1 Due tonight …

– Hard copy before end of night– Electronic by 11:59 PM tonight

• Lab # 2 is due … 12/12/11

• Use Student Logic Number 301

• Lab report criteria is available on the class web page

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Next Week …

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Next Week Topics

• Exam # 3

• In two weeks … Chapter 10 … VHDL

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Home Work

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Homework

1. Study for exam #3

2. Lab #2

3. Read Chapter 10

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References

1. None