Unit 11 1

Flip-Flops

Unit 11

Unit 11 2

Outline․Introduction ․Set-Reset latch ․Gated D latch ․Edge-triggered D Flip-Flop ․Set-Reset Flip-Flop ․J-K Flip-Flop ․T Flip-Flop ․Flip-Flop with additional inputs ․Summary

Unit 11 3

Combinational: Output is a function of present inputs only

Sequential : Output is a function of both present and previous inputs

Circuit “remembers” previous history using

→ Flip-Flop (F/F): with clock input (on clock edge)

→ Latch : with no clock input (or on clock level)

F/F: a memory device with 1 output, or 2 complementary outputs

Introduction (1/3)

Unit 11 4

Timing X

X'

ε1

ε2ε1, ε2 may be very

small but still exist.

x x'

Introduction (2/3)

20ns 20ns

20ns 20ns

A

G2

G1

AB=1 C=0

G1

G2

1us delaydue to wire length

propagation delay in AND

Unit 11 5

Timing in feedback network

One inversion (oscillatory)

Two inversions (stable)

Introduction (3/3)

0 1 1 0 1 0 0 1

(a) Inverter with feedback (b) Oscillation at inverter output

XX

Feedback

Unit 11 6

Set-Reset Latch (SR Latch) (1/9)

S=R=0, Q+=Q

PQ10

S R0 0

PQ01

0 0S R

P=Qʼ

Unit 11 7

Set-Reset Latch (SR Latch) (2/9)

PQ01

S R1 0

PQ0

01

S R1 0

S=1, R=0, Q=1, Q+=1

S=1, R=0, Q=0, Q+=1

Set: S=1, R=0, Q+=1

P=Qʼ

Unit 11 8

Set-Reset Latch (SR Latch) (3/9)

S=0, R=1, Q=0, Q+=0

PQ01

1 0

S R0 1

PQ10

S R0 1

S=0, R=1, Q=1, Q+=0

Reset: S=0, R=1, Q+=0

P=Qʼ

Unit 11 9

R

S

Q

Q

R

S

Q

Q'

Set-Reset Latch (SR Latch) (4/9)

PQ

S R

R

S

Q

P (Qʼ)

Restructured circuit Symbol

Original circuit

Unit 11 10

Set-Reset Latch (SR Latch) (5/9)

S

R

Q ε ε

1 2 gate delays

Reset

Set

Timing diagram

2 1 gate delay 1 2

R

SQʼ

Q0

0

1→0

0→1

0→1

1→0

Unit 11 11

if S = R = 1 0 at the same time,

Q = P(Q')

0 1 0... not allowed

Q 1 first

Q' 1 first undetermined

or

Set-Reset Latch (SR Latch) (6/9)

allowednot inputs10

11

11

110110010110001011000000

(t)Q

tQtQtRtS

S

R

1→0

1→0

P 0 →1 →0 →1

Q 0 →1 →0 →1

0 1

1 1

0 X

0 X

Unit 11 12

statenext :Qstatepresent :Q

11101010

00

1n

n

1

n

n

QQRS

statenext :Qstatepresent :Q

11101010

00

1n

n

1

n

n

QQRS

characteristic equation

t S t R' t Q t or

Q S R'Q (when SR 0 or SR 11)

Q

Set-Reset Latch (SR Latch) (7/9)

00

01

11

10

0 1S(t)

R(t)Q(t)

Unit 11 13

Alternative form using NAND gates

Set-Reset Latch (SR Latch) (8/9)

( ) ( ) Q (t)

1 1 0 01 1 1 11 0 0 01 0 1 00 1 0 10 1 1 1

0 0 0inputs not allowed

0 0 1

S t R t Q t Q t

( ) ( ) Q (t)

1 1 0 01 1 1 11 0 0 01 0 1 00 1 0 10 1 1 1

0 0 0inputs not allowed

0 0 1

S t R t Q t Q t

LS

R

Q

Qʼ

statenext :Qstatepresent :Q

00110001

11

1n

n

1

n

n

QQRS

statenext :Qstatepresent :Q

00110001

11

1n

n

1

n

n

QQRS

Unit 11 14

Usage of SR latch1. As a component in more complex latches and F/Fs2. For debouncing switches

Set-Reset Latch (SR Latch) (9/9)

+V

1

b

a

S

R

Q

S

R

Q

Q

Unit 11 15

Transparent latch since G=1, Q = DGated D Latch

11111011010100011110001011000000

QQDG

11111011010100011110001011000000

QQDG

LD

G

Q

Q’0 0 1 0

1 1 1 0

00 01 11 10

0

1

GD

L

Q

Qʼ

S

R

G

D

Q

D

G

(a) (b)

Unit 11 16

DQ

1100QD

111101010000

n1

nn QQD

Similar to D latch, but changes only to clock edge

Edge-Triggered D Flip-Flop (1/5)

FFQʼ Q

DCkFF

Qʼ Q

DCk

Unit 11 17

Timing diagram of falling edge triggered D F/F

Edge-Triggered D Flip-Flop (2/5)

D

Ck

Q

Unit 11 18

Timing diagram of rising edge triggered D F/F

Edge-Triggered D Flip-Flop (3/5)

CLK = G2

G1

D

P

Q(b) Time analysis

(a) Construction from two gated D latches

D

CLK

D1 Q1

G1

LD2 Q2

G2

L

Unit 11 19

Edge-Triggered D Flip-Flop (4/5)

․Determine the minimum clock period Minimum clock period

=(total delay of gates) + (total delay of F/F)

․Example: suppose that Propagation delay of the inverter = 2ns, Propagation delay of the D F/F = 5ns, Setup time of the D F/F = 3ns,

Determine the minimum clock period of the circuit

Unit 11 20

Edge-Triggered D Flip-Flop (5/5)

(a) Simple flip-flop circuit (b) Setup time not satisfied

(d) Minimum clock period(c) Setup time satisfied

CLK

CLK

CLKCLK

Q

D

Q

D

Q

D

D Q

Unit 11 21

Similar to SR latch, but has an extra clock input and changes only at clock edge

S-R Flip-Flop (1/2)

_111_011110110010110001011000000

QQR S

_111_011110110010110001011000000

QQR S

inputs NOT allowed

0 1

1 1

0 X

0 X

00

01

11

10

0 1SRQ

S Q

R QʼCk

Operation summary:S=R=0 no state changeS=1, R=0 set Q to 1 (after active Ck edge)S=0, R=1 reset Q to 0 (after active Ck edge)S=R=1 not allowed

Unit 11 22

S-R Flip-Flop (2/2)․ Implementation of S-R Flip-Flop

Constructed from two S-R latches and gates Master-slave flip-flop

CLKCLK’

S

RP

Q

At t5 , S=R=0,the state of Qshould not change

We can solve this problem if we only allow the S and R inputs to change while the clock is high(b) Timing analysis

Qʼ

SCk

R

QCLK

S

R

Q

Q’

S1

R1 R2

S2 Q

Qʼ

P

PʼMaster

Slave

(a) Implementation with two latches

Unit 11 23

․Implementation of J-K Flip-Flop

J-K Flip-Flop (1/3)

Qʼ Q

JKFFCk

Q

Qʼ

J

K

CLKS1 S2 QP

PʼR1 R2 QʼSlave

Master

K

J

CLK

Q

QʼCk

FFQ

QʼR

SQ Changes on Rising Edge

Unit 11 24

J-K Flip-Flop (2/3)

0 0 1 1

11 0 0

00 01 11 10

0

1

JKQ

01111011110110010110001011000000

QQKJ

01111011110110010110001011000000

QQKJ

Qʼ Q

JKFFCk

Unit 11 25

J-K Flip-Flop (3/3)

Clock

J

K

Q

J-K flip-flop timing

․Implementation of T (Toggle) Flip-Flop

Unit 11 26

T Flip-Flop (1/3)

Qʼ Q

K JCk

T Clock

Qʼ Q

Ck D

Clock

T

Unit 11 27

T Flip-Flop (2/3)

011101110000

QQT

011101110000

QQT

QT'' TQQTQ QT'' TQQTQ

Qʼ Q

TCkFF

Falling-EdgeTrigger

Unit 11 28

․Timing diagram for T Flip-Flop

T Flip-Flop (3/3)

Falling-Edge Trigger

Ck

T

Q

Unit 11 29

․Flip-Flop with Clear and Preset Inputs

Flip-Flops with Additional Inputs (1/4)

)(11,1,011110110001110

)(00PD

changenoQ

allowednotQClrNreNCk

)(11,1,011110110001110

)(00PD

changenoQ

allowednotQClrNreNCk

Qʼ Q

DCkPreNClrN

Clear Preset

A logic 0 is required to Clear/Preset

Unit 11 30

․Timing diagram for rising-edge trigger D Flip-Flop with Clear and Preset

Flip-Flops with Additional Inputs (2/4)

t1 t2 t3 t4

Q

PreN

ClrN

D

CLK

Unit 11 31

Flip-Flops with Additional Inputs (3/4)

․Gating the Clock Holding existing data even though the data input to the Flip-Flop is

changing Two potential problems:

Gate delays may cause the clock to arrive at some Flip-Flops at different times than at other Flip-Flops, resulting in loss of synchronization

If En changes at the wrong time, the Flip-Flop may trigger due to the change in En instead of due to the change in the clock, resulting in loss of synchronization

(a) Gating the clock

CLKEn Ck

Q

Qʼ

D

․D Flip-Flop with Clock Enable (D-CE Flip-Flop)

CE=0, clock is disabled, Q+=Q CE=1, the F/F acts like a normal D F/F, Q+=D Q+=Q . CEʼ+D . CE

Unit 11 32

Flip-Flops with Additional Inputs (4/4)

(b) D-CE symbol (c) Implementation

Ck

Q

Qʼ

D

CE

Ck

Q

Qʼ

D

CE

01Din

CLK

Unit 11 33

․The characteristic (next-state) equations for latches and F/Fs

Summary (1/3)

Unit 11 34

․Q represents an initial or present state of the Flip-Flop, andQ+ represents the final or next state The interpretation of Q+

For latchQ+ represents the state of the latch a short time after oneof the inputs changes For Flip-FlopQ+ represents the state of the Flip-Flop a short time afterthe active clock edge

Summary (2/3)

Unit 11 35

․Flip-Flops constructed from S-R Flip-Flop

Summary (3/3)

FFCk

S Q

QʼRR

Q

Qʼ

SFF

Ck

DCLK

Q

Qʼ

Q

QʼCLK

J

K

R

Q

Qʼ

SFF

Ck

Q

Qʼ

T

CLK