Logic Circuits I Study Guide for Ch 6-7

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1. The excess-3 code is valuable in some arithmetic circuits because it is self-complementing. 2. The Gray code is valuable in some arithmetic circuits because it is self-complementing. 3. Both the LED and LCD displays emit a reddish light. 4. While the LED display emits light, the LCD unit controls the reflection of light. 5. Vacuum fluorescent displays are very compatible with the 12-V dc power available in automobiles

and the 4000 CMOS series of digital ICs.6. Vacuum fluorescent displays are widely used in solar powered calculators because they operate

well on low power and 1.5 to 5 V dc.7. Liquid-crystal displays are well suited for low light and night operation because they give off a

bright reddish glow.8. LED seven-segment displays are well suited for operation in bright sunlight because they reflect or

control light and do not emit their own light.9. LCD seven-segment displays are well suited for operation in bright sunlight because they reflect or

control light and do not emit their own light.____ 10.

If the grid voltage should drop to 0 V, no segments (plates) of the VF seven-segment display will light.____ 11. While both the LED and VF displays operate on dc voltages, the LCD display is driven by ac

voltages.____ 12. An LED seven-segment display can be driven directly with a 12-V dc power supply with no

limiting resistors.____ 13. An LCD seven-segment display can be driven directly with a 12-V power supply with no limiting

resistors.____ 14. An important electrical characteristic to be specified when ordering a seven-segment LED display

is whether it is a common-anode or common-cathode type.____ 15. The 74147 TTL priority encoder IC has active LOW inputs (1-9) and active LOW outputs (A-D). ____ 16. The 74147 TTL priority encoder IC has active LOW inputs (1-9) and active HIGH outputs (a-g).

____ 17. On the 7447 decoder IC, if only input D is activated, then all outputs will go LOW, lighting the

decimal number 8 on an attached seven-segment LED display.____ 18. On the 7447 decoder IC, if only input d is activated, then all outputs will go HIGH, lighting the

decimal number 0 on an attached seven-segment LED display.____ 19. The 4511 BCD-to-seven-segment decoder/driver IC can only operate on a 5-V dc power supply

when used to drive VF displays.____ 20. While it is common for an LCD display to operate on 5 V, a VF display usually operates on 12 V

dc.____ 21. Flip-flops are wired together to form sequential logic circuits. ____ 22. Flips-flops are wired together to form combinational logic circuits. ____ 23. On a flip-flop, the complementary output (Q1) is always at the same logic state as the normal (Q)

output.____ 24. The complementary output (Q1) of a flip-flop is always at the opposite logic state from the normal

(Q) output.____ 25. To set a flip-flop means to force the normal (Q) output to a 1 or HIGH. ____ 26. To reset a flip-flop means to force the normal (Q) output to a 1 or HIGH. ____ 27. A Schmitt trigger device is most commonly used in wave shaping circuits that square up digital

waveforms so they have faster rise and fall times.____ 28. The input switching threshold of Schmitt trigger devices is the same for both positive-going and

negative-going voltages.____ 29.

The C input on the IEEE logic symbol means a control input which is the clock input to the J-K flip-flop.

____ 30. The Gray code ___ a BCD-type code. a. is b. is not ____ 31. This code is not classified as a BCD type code. a. Gray code

b. 8421 code c. XS3 code d. 4221 code ____ 32. The most popular 7-bit alphanumeric code is _____. a. NASA b. NASAB c. TTL d. ASCII e. CMOS ____ 33. The 74HC4543 CMOS decoder IC translates from a(n) ____ input to a(n) ____ output. a. ASCII, decimal b. Decimal, BCD c. BCD, decimal d. BCD, seven-segment code e. BCD, Gray code ____ 34. The decimal number 36 equals ____ in the 8421 BCD code. a. 0100 0110 b. 0110 0011 c. 0011 0110 d. 0010 0100 e. 0011 0101 ____ 35. The decimal number 18 equals ____ in the XS3 code. a. 0001 1000 b. 1000 0001 c. 0001 0010 d. 0100 1011 e. 0100 1001 ____ 36. The excess-3 code ____ classified as a BCD type code. a. is b. is not ____ 37. A(n) ____ is the electronic device used to convert the decimal input of a calculator to the BCD

code used by the central processing unit. a. Flip-flop b. Translator c. Multiplexer d. Encoder e. Assembler ____ 38. A(n) ___ is the electronic device used to convert the BCD code from the central processing unit of a calculator to the decimal display output. a. Decoder b. Translator c. Multiplexer d. Amplifier e. Assembler

____ 39. Portable digital devices, such as watches and solar-powered calculators, use ____ displays because

of their extremely low power consumption. a. TTL b. NMOS c. LED d. LCD e. Incandescent ____ 40. The liquid-crystal display that shows black characters on a silvery background is the _____ type. a. Dynamic scattering b. Photovoltaic c. Hyper LCD d. Field-effect e. Magneto-optical____ 41.

The part of the VF seven-segment display schematic diagram labels A is called the ____. a. Grid b. Plate c. Cathode, filament, or heater d. Nematic fluid____ 42.

The part of the VF seven-segment display schematic diagram labeled B is called the _____. a. Grid b. Plate c. Cathode, filament, or heater d. Nematic fluid____ 43.

The parts of the VF seven-segment display schematic diagram labeled C are called the ____. a. Grids b. Plates c. Cathodes, filaments, or heaters d. Nematic fluids____ 44.

____ 45.

____ 46.

____ 47.

____ 48.

____ 49.

Which segments (plates) of the VF seven-segment display glow in this circuit? a. Segments f and g b. All segments c. Segments a, d, e, f, and g d. Segments b and c The seven-segment display that emits a reddish glow is the ____ type. a. Incandescent b. Gas-discharge tube c. Vacuum fluorescent d. Light-emitting diode (LED) e. Liquid-crystal display (LCD) The seven-segment display that emits a green glow when lit and is very compatible with the 12-V dc power in an automobile is the _____ type. a. Incandescent b. Light-emitting diode (LED) c. Vacuum fluorescent (VF) d. Liquid-crystal display (LCD) On the 74147 TTL encoder IC, if only input 7 is activated with a LOW, active LOW output(s) ____ will be activated. a. D and C b. C and B c. B and A d. D e. C, B and A On the 74147 TTL encoder, if both inputs 2 and 6 have LOW inputs, only input ____ will be activated because of the IC's priority feature. a. 2 b. 4 c. 6 d. 8 e. 0 The 74147 TTL encoder IC has active ___ inputs (1-9). a. HIGH

b. LOW ____ 50. The 74147 TTL encoder IC has active _____ outputs (A-D). a. HIGH b. LOW ____ 51. The 7447 BCD-to-seven-segment TTL decoder/driver IC has active ____ inputs (A-D) and active

____ 52.

____ 53.

____ 54.

____ 55.

____ 56.

____ 57.

_____ outputs (a-g). a. HIGH, HIGH b. HIGH, LOW c. LOW, LOW d. LOW, HIGH The 7447 TTL IC is used in conjunction with seven limiting resistors and a(n) ____ seven-segment LED display to translate a BCD number to a decimal number. a. Common-anode b. Common-cathode c. Common-collector d. Common-zener The _____ decoder/driver IC was used to drive seven-segment LED displays in this chapter. a. 4511 b. 7447 c. 7474 d. 74121 e. 74HC4543 The ______ decoder/driver IC was used to drive seven-segment LCD displays in this chapter. a. 4511 b. 7447 c. 7474 d. 74121 e. 74HC4543 The____ decoder/driver IC was used to drive seven-segment VF displays in this chapter. a. 4511 b. 7447 c. 7474 d. 74121 e. 74HC4543 A 100-Hz square-wave clock signal must be sent to the common pin of a seven-segment LCD display and the ____ input t the 74HC4543 decoder/LCD driver IC. a. BCD b. BI c. Latch d. LE e. Phase A segment of an LCD display is said to be driven or activated by a(n) ___ square-wave signal. a. DC b. In-phase c. Out-of-phase

____ 58. We used seven limiting resistors between the _____ BCD-to-seven-segment decoder IC and a

____ 59.

____ 60.

____ 61.

____ 62.

____ 63.

____ 64.

common-anode seven segment LED display. a. 4511 b. 7400 c. 7447 d. 7474 e. 74HC4543 This BCD-to-seven-segment decoder/driver IC is manufactured using bipolar technology. a. 4511 b. 7400 c. 7447 d. 74HC4543 The 74147 TTL encoder IC translates from a(n) ____ input to a(n) _____ output. a. ASCII, decimal b. Decimal, BCD c. BCD, decimal d. BCD, seven-segment code The 7447 TTL decoder IC translates from a(n) ____ input to a (n) _____ output. a. ASCII, decimal b. Decimal, BCD c. BCD, decimal d. BCD, seven-segment code The 4511 CMOS decoder IC translates from a(n) ____ input to a(n) ____ output. a. ASCII, decimal b. Decimal, BCD c. BCD, decimal d. BCD, seven-segment code e. BCD, gray code The basic building block of combinational logic circuits is the ____. a. Flip-flop b. Flash memory cell c. Logic gate d. Rectifier e. Timer The basic building block of sequential logic circuits is the ______. a. Amplifier b. Flip-flop c. Rectifier d. Multiplexer e. Timer

____ 65.

This R-S flip-flop has active ____ inputs. a. HIGH b. LOW c. Synchronous____ 66.

During time period t1, the R-S flip-flop is in the ____ mode of operation. a. Hold b. Reset c. Set____ 67.

During time period t2, the R-S flip-flop is in the ____ mode of operation. a. Hold b. Reset c. Set____ 68.

During time period t3, the R-S flip-flop is in the ____ mode of operation. a. Hold b. Reset c. Set____ 69.

During time period t1, the normal output of the R-S flip-flop is ____. a. Reset to 0 b. Set to 1 c. Held at 0 (in hold mode) d. Held at 1 (in hold mode)____ 70.

During time period t2, the normal Q output of the R-S flip-flop is ____. a. Reset to 0 b. Set to 1 c. Held at 0 (in hold mode) d. Held at 1 (in hold mode)____ 71.

During time period t3, the normal Q output of the R-S flip-flop is ____. a. Reset to 0 b. Set to 1 c. Held at 0 (in hold mode) d. Held at 1 (in hold mode)____ 72.

The clocked R-S flip-flop has active ____ data inputs (R and S inputs). a. HIGH b. LOW____ 73.

During time period t4, the clocked R-S flip-flop is in the ____mode of operation. a. Hold b. Reset c. Set

____ 74.

During time period t2, the clocked R-S flip-flop is in the ___mode of operation. a. Hold b. Reset c. Set____ 75.

During time period t3, the clocked R-S flip-flop is in the ____ mode of operation. a. Hold b. Reset c. Set____ 76.

After clock pulse t1, the normal Q output of the clocked R-S flip-flop is _____. a. Reset to 0 b. Set to 1 c. Held at 0 (in hold mode) d. Held at 1 (in hold mode)____ 77.

After clock pulse t2, the normal Q output of the clocked R-S flip-flop is _____. a. Reset to 0 b. Set to 1 c. Held at 0 (in hold mode) d. Held at 1 (in hold mode)____ 78.

After clock pulse t3, the normal Q output of the clocked R-S flip-flop is _____. a. Reset to 0 b. Set to 1 c. Held at 0 (in hold mode) d. Held at 1 (in hold mode)____ 79.

The asynchronous inputs to this D flip-flop are the_____ inputs. a. CLK and PS b. CLR and PS c. D and CLK____ 80.

The normal output (Q) of the D flip-flop will be _____ after pulse t1.a. HIGH b. LOW ____ 81.

The normal output (Q) of the D flip-flop will be ___ after pulse t2.a. HIGH b. LOW ____ 82.

The normal output (Q) of the D flip-flop will be ___ after pulse t3. a. HIGH b. LOW____ 83.

The normal output (Q) of the D flip-flop will be ___ after pulse t4. a. HIGH b. LOW____ 84.

The J-K flip-flop is in the_____ mode of operation during pulse t1. a. Asynchronous clear b. Asynchronous preset c. Hold d. Set____ 85.

The J-K flip-flop is in the_____ mode of operation during pulse t2. a. Reset b. Asynchronous preset c. Hold d. Set____ 86.

The J-K flip-flop is in the_____ mode of operation during pulse t3. a. Reset b. Asynchronous preset c. Hold

d. Set ____ 87.

The J-K flip-flop is in the_____ mode of operation during pulse t4. a. Reset b. Toggle c. Hold d. Set____ 88.

The J-K flip-flop is in the_____ mode of operation during pulse t5. a. Toggle b. Asynchronous clear c. Hold d. Set____ 89.

The normal output (Q) of the J-K flip-flop will be ____ after pulse t1. a. HIGH

b. LOW ____ 90.

The normal output (Q) of the J-K flip-flop will be ____ after pulse t2. a. HIGH b. LOW____ 91.

The normal output (Q) of the J-K flip-flop will be ____ after pulse t3. a. HIGH b. LOW____ 92.

The normal output (Q) of the J-K flip-flop will be ____ after pulse t4. a. HIGH b. LOW____ 93.

The normal output (Q) of the J-K flip-flop will be ____ after pulse t5. a. HIGH b. LOW____ 94.

The J-K flip-flop is in the ____ mode of operation during pulse t1. a. Toggle b. Asynchronous preset c. Hold d. Set____ 95.

The J-K flip-flop is in the ____ mode of operation during pulse t2. a. Toggle b. Asynchronous preset c. Hold d. Set____ 96.

The J-K flip-flop is in the ____ mode of operation during pulse t3. a. Toggle b. Asynchronous preset c. Hold d. Set____ 97.

The J-K flip-flop is in the ____ mode of operation during pulse t4. a. Toggle b. Asynchronous preset c. Hold d. Set____ 98.

The normal output (Q) of the J-K flip-flop will be _____ after pulse t1. a. HIGH b. LOW____ 99.

The normal output (Q) of the J-K flip-flop will be _____ after pulse t2. a. HIGH b. LOW____ 100.

The normal output (Q) of the J-K flip-flop will be _____ after pulse t3. a. HIGH b. LOW____ 101.

The normal output (Q) of the J-K flip-flop will be _____ after pulse t4. a. HIGH b. LOW ____ 102. The normal output (Q) of a flip-flop is forced to a logical ____ when the unit is reset.a. 0 b. 1 ____ 103. The normal output (Q) of a flip-flop is forced to a logical _____ when the unit is reset. a. 0 b. 1 ____ 104.

The 7475 latch is in what mode of operation during time period t1? a. Data enabled b. Data latched____ 105.

The 7475 latch is in what mode of operation during time period t2? a. Data enabled b. Data latched____ 106.

The 7475 latch is in what mode of operation during time period t3? a. Data enabled b. Data latched____ 107.

The 7475 latch is in what mode of operation during time period t4?

a. Data enabled b. Data latched ____ 108. A Schmitt trigger device is commonly used for ____. a. Counting b. Multiplexing c. Storing data d. Wave shaping ____ 109. Schmitt trigger devices are said to have _____ because their switching thresholds are different for

positive-going and negative-going inputs. a. Bandwidth b. Convergence c. Hysteresis d. Wobbulation____ 110.

This is the IEEE logic symbol for the _____ IC. a. 7476 hex Schmitt trigger inverter b. 7476 D flip-flop c. 7476 hex latch d. 7476 J-K flip-flop____ 111.

The small triangles at the S and R leads on the left side of the IEEE logic symbol mean these are _____. a. Active-LOW inputs b. Active-HIGH inputs c. Active-HIGH outputs

Logic Circuits I Study Guide for Ch 6-7 Answer Section

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42.

T F F T T F F F T T T F F T T F T F F T T F F T T F T F T B A A D C D A D A D D A C

43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88.

B D D C E C B B B A B E A E C C C B D D C B B C A B B D A A C A B B D A B B A B A B A C B B

89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111.

A B B A B B C A A A A B A A B A A B A D C D A