Linking Mixed-Signal Design and Test · (TTM) for mixed-signal IC’s. The various aspects of the mixed-signal test problem are discussed in chap-ter 2 of this thesis. A general discussion

Linking Mixed-Signal Design and Test

Generation and Evaluation of

Specification-Based Tests

Nur Engin

Samenstelling promotiecommissie:

Voorzitter: Prof.dr. W.E. van der Linden, Universiteit TwenteSecretaris: Prof.dr. W.E. van der Linden, Universiteit TwentePromotor: Prof.dr. H. Wallinga, Universiteit TwenteAss. Promotor: Dr.ir. H.G. Kerkhoff, Universiteit TwenteReferent: Dr.-Ing. M.J. Ohletz, Alcatel MicroelectronicsLeden: Prof.dr.ir. B. Nauta, Universiteit Twente

Prof.dr.ir. T. Krol, Universiteit TwenteProf.dr.ir. W.M.G. van Bokhoven, TU EindhovenProf.dr.ir. J.L. Huertas Diaz, University of Sevilla

Title: Linking Mixed-Signal Design and TestGeneration and Evaluation of Specification-Based Tests

Author: Nur EnginISBN: 90-3651494-0

Printed by Febodruk B.V., Enschedec©N. Engin 2000

LINKING MIXED-SIGNAL DESIGN AND TEST

GENERATION AND EVALUATION OF SPECIFICATION-BASED TESTS

PROEFSCHRIFT

ter verkrijging vande graad van doctor aan de Universiteit Twente,

op gezag van de rector magnificus,prof. dr. F.A. van Vught,

volgens besluit van het College van Promotiesin het openbaar te verdedigen

op vrijdag 29 september 2000 te 16.45 uur.

door

Nur Engingeboren op 16 september 1970

te Ankara (Turkije)

Dit proefschrift is goedgekeurd door

de promotor, Prof. dr. H. Wallinga,

en de assistent promotor, Dr. ir. H.G. Kerkhoff.

Was man nicht versteht, besitzt man nicht.

GOETHE

Contents

Summary vii

Acknowledgments ix

Symbols xi

Abbreviations xiii

1 Introduction 11.1 Testing: The Hidden Challenge . . . . . . . . . . . . . . . . 21.2 Analog and Mixed-Signal Testing . . . . . . . . . . . . . . . 3

1.2.1 Analog vs Digital Testing . . . . . . . . . . . . . . . 31.2.2 Analog/Mixed-Signal Challenges . . . . . . . . . . . 5

1.3 Motivation and Problem Definition . . . . . . . . . . . . . . 91.4 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.5 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 The Mixed-Signal Test Problem 152.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.2 Mixed-Signal IC Architectures . . . . . . . . . . . . . . . . 162.3 Current Design and Test Practice . . . . . . . . . . . . . . . 18

2.3.1 Prototype Test . . . . . . . . . . . . . . . . . . . . . 182.3.2 Production Test . . . . . . . . . . . . . . . . . . . . 20

2.4 Market Requirements . . . . . . . . . . . . . . . . . . . . . 242.4.1 Quality . . . . . . . . . . . . . . . . . . . . . . . . . 24

i

2.4.2 Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.4.3 Time-to-Market . . . . . . . . . . . . . . . . . . . . . 30

2.5 Mixed-Signal Test: Current Issues and Challenges . . . . . 312.5.1 Test and Measurement Environments . . . . . . . . 312.5.2 Design for Testability (DfT) . . . . . . . . . . . . . . 322.5.3 Built-in Self-Test (BIST) . . . . . . . . . . . . . . . 332.5.4 Automatic Test Program Generation (ATPG) . . . . 352.5.5 Test Program Evaluation . . . . . . . . . . . . . . . 37

2.6 Trends in Mixed-Signal IC Design . . . . . . . . . . . . . . 382.7 Trends in IC Technology . . . . . . . . . . . . . . . . . . . . 402.8 Design-Test Link . . . . . . . . . . . . . . . . . . . . . . . . 402.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 422.10 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3 A General Framework for Mixed-Signal Test Generationand Testing 493.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 493.2 Design and Test Flow: The Current Status . . . . . . . . . 503.3 High-Level Considerations . . . . . . . . . . . . . . . . . . . 513.4 Macro-Level Considerations . . . . . . . . . . . . . . . . . . 563.5 Simulation Support for Test . . . . . . . . . . . . . . . . . . 58

3.5.1 Simulation-Based Test Generation . . . . . . . . . . 583.5.2 Virtual Testing . . . . . . . . . . . . . . . . . . . . . 60

3.6 Reuse Issues in Design and Test . . . . . . . . . . . . . . . . 633.7 State of the Art in Design-Test Link . . . . . . . . . . . . . 63

3.7.1 Virtual Test Software . . . . . . . . . . . . . . . . . 643.7.2 Test Plan Generation Tools . . . . . . . . . . . . . . 653.7.3 Test Program Evaluation Tools . . . . . . . . . . . . 66

3.8 A General Framework for Design-Test Link . . . . . . . . . 663.8.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . 683.8.2 Design and Test Methodology . . . . . . . . . . . . . 69

3.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 713.10 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . 71

ii

4 MISMATCH: A Framework for Design-Test Link 754.1 System Overview . . . . . . . . . . . . . . . . . . . . . . . . 754.2 Integrated Design and Test Flow . . . . . . . . . . . . . . . 774.3 Test Database . . . . . . . . . . . . . . . . . . . . . . . . . . 774.4 Design for Testability . . . . . . . . . . . . . . . . . . . . . 804.5 Design Database . . . . . . . . . . . . . . . . . . . . . . . . 814.6 MISMATCH CAD Data Flow . . . . . . . . . . . . . . . . . 82

4.6.1 Usage of Simulation Results . . . . . . . . . . . . . . 834.6.2 Test Set Selection . . . . . . . . . . . . . . . . . . . 86

4.7 MISMATCH CAT Data Flow . . . . . . . . . . . . . . . . . 884.7.1 Test Control Signal Generation . . . . . . . . . . . . 904.7.2 Automatic Routing for the Test Set . . . . . . . . . 904.7.3 Test Generation for Mixed-Signal Macros . . . . . . 924.7.4 Test Generation for Digital Macros . . . . . . . . . . 93

4.8 An Example: Design and Test of a Compass Watch . . . . . 944.8.1 IC Overview . . . . . . . . . . . . . . . . . . . . . . 944.8.2 Analog Functionality and the Test Library . . . . . 96

4.9 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054.9.1 Digital Parts . . . . . . . . . . . . . . . . . . . . . . 1054.9.2 Analog Parts . . . . . . . . . . . . . . . . . . . . . . 107

4.10 Discussion of Experiences . . . . . . . . . . . . . . . . . . . 1084.11 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104.12 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5 Defect-Oriented Test Evaluation for Analog Blocks 1155.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155.2 General Test Selection Criteria . . . . . . . . . . . . . . . . 1165.3 Specification Coverage vs. Fault Coverage . . . . . . . . . . 1165.4 Manufacturing Defects and IC Faults . . . . . . . . . . . . . 1185.5 Layout Based Fault List Extraction . . . . . . . . . . . . . . 121

5.5.1 Critical Area . . . . . . . . . . . . . . . . . . . . . . 1215.5.2 Fault Probability Calculations . . . . . . . . . . . . 122

5.6 Analog Fault Simulation as a Test Evaluation Method . . . 1245.7 Problem Definition . . . . . . . . . . . . . . . . . . . . . . . 125

iii

5.8 Standard Methods in Circuit Simulation . . . . . . . . . . . 1275.9 Simulation Complexity . . . . . . . . . . . . . . . . . . . . . 132

5.9.1 Evaluation of Device Models . . . . . . . . . . . . . 1345.9.2 Solution of Linear Equations . . . . . . . . . . . . . 1355.9.3 Number of NR Iterations . . . . . . . . . . . . . . . 135

5.10 Fault Simulation: Overview of Existing Methods . . . . . . 1375.10.1 Methods for Linear Circuits . . . . . . . . . . . . . . 1395.10.2 Methods for Solving Sets of Linear Equations... . . . 1395.10.3 Other Methods . . . . . . . . . . . . . . . . . . . . . 148

5.11 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495.12 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . 151

6 A New Approach Towards Analog Fault Simulation 1556.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1556.2 Simulator Requirements . . . . . . . . . . . . . . . . . . . . 1566.3 DC-Bias Grouping . . . . . . . . . . . . . . . . . . . . . . . 1576.4 One-Step Relaxation Method . . . . . . . . . . . . . . . . . 1636.5 Grouping Methods . . . . . . . . . . . . . . . . . . . . . . . 1656.6 Partial LU Update . . . . . . . . . . . . . . . . . . . . . . . 1666.7 Parallel Simulation . . . . . . . . . . . . . . . . . . . . . . . 1706.8 Implementation and Results . . . . . . . . . . . . . . . . . . 1706.9 Conclusions and Future Research . . . . . . . . . . . . . . . 1786.10 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . 180

7 Conclusions and Recommendations 1857.1 Summary of Results . . . . . . . . . . . . . . . . . . . . . . 1857.2 Original Contributions of This Thesis . . . . . . . . . . . . 1877.3 Recommendations . . . . . . . . . . . . . . . . . . . . . . . 187

Appendices 189

A Example of a Virtual Instrument 191A.1 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . 191A.2 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

iv

B Mixed-Signal Test System: An Overview 195B.1 Digital Tester Part . . . . . . . . . . . . . . . . . . . . . . . 195B.2 Analogue Tester Part . . . . . . . . . . . . . . . . . . . . . . 196B.3 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . 197

C Verification Test Results for the Compass Watch BufferMacro 199

Samenvatting 201

About the Author 203

v

Summary

The work described in this thesis is aimed at the exploration of new methodsfor the integration of design and test development procedures for mixed-signal integrated circuits (IC’s). Mixed-signal IC’s are currently found inmany electronic systems, including telecommunications, audio and videoinstruments, automotive parts, etc. The testing of these IC’s presentsproblems due to the complex nature of analog functionality and the non-automated analog design process. Automatic generation of test programsfor analog parts is a problem which is not yet fully solved. Once a test isgenerated, formal methods to ensure the quality of developed tests do notexist or have a large overhead. Systematic links between design and testdevelopment processes of analog and mixed-signal circuits are required toimprove these points and to ensure high quality and low time-to-market(TTM) for mixed-signal IC’s.

The various aspects of the mixed-signal test problem are discussed in chap-ter 2 of this thesis. A general discussion of the present mixed-signaldesign and test practice, the implications of market requirements on thetest methodology, and the future challenges for mixed-signal testing is pre-sented. It has been concluded that long test development and debuggingtime and lack of methods for realistic test evaluation are the main chal-lenges in mixed-signal testing at present.

The discussions in chapter 3 are aimed at defining a general frameworkfor the integration of mixed-signal design and test activities along the ICdevelopment traject. For this, the test considerations at various levels ofabstraction are given, and the present state of the art and possibilities invirtual testing and design-test link tools are presented. At the end of thischapter, a general framework for linking mixed-signal design and test ispresented.

In chapter 4, an environment for the integration of design and test flowsfor the prototype test of mixed-signal IC’s is introduced and implemented.The described environment (MISMATCH) is based on the sharing of de-sign data with the test environment for generation of specification-based

vii

prototype tests during the design steps. The functionality consists of theselection of test methods from a test library, usage of macro specificationsto select test functions, generation of control signals for access to the testedparts and addition of information for automatic routing to required testermodules. MISMATCH has been implemented using existing design and testframeworks and the resulting system has been used for the design and testtraject of a mixed-signal IC. The corresponding test results are presented.

In chapter 5, an important aspect of the generated tests, the test effec-tiveness, is discussed. The manner in which tests have been generated inthe MISMATCH framework as described in chapter 4 guarantees only thatcertain parameters are measured, and not that the process-related failurepossibilities are covered. In order to be able to have high IC quality figures,tests have to address the cause and not only the consequence of defects.For this reason, the link between the IC manufacturing process and testquality is investigated in this chapter. The chapter concludes that decreas-ing the fault simulation time is one of the biggest challenges in evaluatingthe quality of mixed-signal tests. A discussion of the existing methods fordecreasing the fault simulation time is presented.

The aim of decreasing the fault simulation time is pursued in chapter 6,where a new method for the efficient fault simulation of mixed-signal cir-cuits is presented. This method is based on decreasing the complexity offault simulations by using parallel simulation techniques. A prototype faultsimulator is implemented for checking the speedup of the new method. Thisimplementation uses resistive bridges as fault model, although the methodis also applicable to other fault models. The experiments made using theprototype simulator are presented in the chapter. The results show that animprovement of 30% is possible compared to the conventional simulationmethods.

viii

Acknowledgments

The efforts of a number of people have been vital for the existence andquality of this thesis. I owe gratitude to all colleagues and friends whohave a part in making the last four and half years a nice time, and whohave encouraged me to keep the good spirit even in the ‘less nice’ times.Specifically, I would like to thank:

• Han Speek, for his indispensable help for the implementation andimprovement of the fault simulation software, and for his constant(moral and technical) support and constructive criticism during thewriting of this thesis,

• Ronald Tangelder, for being a resourceful and enjoyable discussionpartner (be it about IC testing, European history or the touristicspots in Germany!), and for his detailed and valuable feedback onthe earlier versions of this thesis,

• My supervisor Hans Kerkhoff, for introducing me to mixed-signaltesting and for laying the conceptual foundations of the MISMATCHframework,

• My promotor Hans Wallinga, for his support especially during thelast year and the writing of this thesis,

• Commission member Michael Ohletz, for his detailed remarks on theearlier version of this thesis which have contributed a great deal tothe quality of the final version,

• Nico Csizmadia, Taco Zwemstra, Yizi Xing and Harry Bremer ofPhilips Semiconductors, discussions with whom have helped me tosee ‘the practical face of mixed-signal testing’, and Nico Csizmadiaalso special thanks for the nice and useful time during my practicaltraining in Nijmegen,

• Students Johan Wesselink and Ercan Yılmaz for implementing theconversion functions for the MISMATCH framework, and Kitty vanNee and Pieter Jan Bouma for making parts of the test library, andMetin Tümkaya for his efforts towards implementing MISMATCH,

ix

• Cor Bakker for his high quality maintenance of the PC network andfast and friendly support with all PC problems,

• Marcel Weusthof and Henk de Vries for their technical support duringthe test experiments,

• Egbert Holl, for the maintenance of the HP-network,• The administrative staff of the department ICE and later the teaching

chair SC, the secretaries Margie Rhemrev, Marie-Christine Prédéryand Mariska Buurman, and the financial administrators Sophie Kreulenand Joke Vollenbroek: thanks for keeping things organized and thework atmosphere enjoyable,

• My office mates Victor Kaal, Jan Harm Nieland, Milan Stancic andLiquan Fang, for the nice and interesting discussions (in a wide spec-trum including goats, computers, photography, movies, food, politics,and common words in Serbian and Turkish): the good mood in theoffice was sometimes crucial in ‘keeping me going’ !

• Gidi Kroon, for sharing all kind of good and bad events of the lastyears, and for suggesting improvements on some parts of this thesis,

• Gidi Kroon and Milan Stancic, for accepting to be my ‘paranimfen’.

Last but not the least, I would like to thank family members who havemeant so much for me with their encouragement and support: My parentsand Elif: thanks for the ‘eat-a-lot-laugh-a-lot’ weeks in Turkey which mademe go back to work in good mood, my mother, thanks for emailing me everyday and worrying so much about me that nothing is left for me to worryabout myself. Canım anneciğim, babacığım ve Elif: teşekkürler! Ans, Jaapand Raph, thanks for your unconditional support and friendship, and Jaapfor calling me kızım! And Marc, thanks for going through this adventurewith me, putting up with me at those times when I was not exactly gezellig,for feeding me and cheering me up, for keeping me up to date with thenews about Turkey, for making me understand the ‘Dutch way’ and feel athome, for believing in me at all times and under all circumstances, and ...for translating the summary into Dutch!

Nur EnginEindhoven,September 2000

x

Symbols

x scalarx vectorX matrixx(k) kth iteration of xx∗ exact solution of xx̃ estimated solution of xẋ time derivative of x|x| absolute value of the scalar x|x| Euclidean norm of the vector xx ∈ S x is element of set S|S| cardinality of set S< set of real numbers

Abbreviations

ADC Analog to Digital ConverterATE Automatic Test EquipmentATPG Automatic Test Pattern GenerationAWG Arbitrary Waveform GeneratorBIST Built-In Self-TestCAD Computer-Aided DesignCAT Computer-Aided TestCUT Circuit Under TestDAC Digital to Analog ConverterDfM Design for ManufacturabilityDfT Design for TestabilityDIB Device Interface BoardDOT Defect Oriented TestingDSP Digital Signal ProcessingDUT Device Under TestEDA Electronic Design AutomationIC Intergrated CircuitIP Intellectual PropertyGPIB General-Purpose Interface BusMISMATCH MIxed-Signal MAnipulation Tool for CHipsMNA Modified Nodal AnalysisMUT Macro Under TestNR Newton-Raphson (iterations)PLL Phase-Locked LoopPPM Parts Per MillionPWL Piecewise LinearSNR Signal-to-Noise Ratio

xiii

STIL Standard Test Interface LanguageTHD Total Harmonic DistortionTTM Time-To-MarketVI Virtual InstrumentVHDL VHSIC Hardware Description LanguageVHSIC Very High-Speed Integrated CircuitVME Virtual Machine environmentVXI VMEbus eXtensions for Instrumentation

xiv

Chapter 1

Introduction

When the historians of the future will have to name our time, they surelywill have a large number of names to choose from: internet age, connec-tivity age, ubiquitous communication age ... Whatever their choice will be,there is no doubt that the revolution in communications is one of the mostrepresentative characteristics of the last two decades. With the number ofinternet connections doubling every year [Esta99], the internet has becomefar more commonly used than could be expected 10 years ago. We haveseen a similar speed in the acceptance of mobile telephony by large masses,following the decrease in the price for buying and using cellular phones.

The place and importance of electronic appliances in our daily lives is get-ting larger at a fast pace. Looking ahead, it is possible to anticipate someof the technological leaps to come in the near future. A series of newapplications is already beginning to bring together the internet, mobilecommunications and consumer electronics platforms. Power managementapplications will have to improve to keep the mobile applications withinthese platforms usable. These developments will result in many changesin the way people live, work and communicate. The human-computer in-terface will become more natural by developments in speech recognitiontechniques. Improvements in the quality of automotive electronics, homeentertainment systems and office peripherals will certainly continue. Asa result, many aspects of human life, some of them ‘safety-critical’, arecontrolled by electronic systems.

Considering that most of the data processing that occurs in communica-

1

2 CHAPTER 1. INTRODUCTION

tions and computers is digital, it seems as if analog design in integratedcircuits (IC’s) becomes less common. However, one of the few commonpoints among the diverse application domains mentioned above is thatthey require mixed-signal IC’s for their key functionality. Systems for mo-bile telephones and wireless networks require transmitters, receivers andpower management circuitry. Multimedia applications require conversioninto analog forms at the back end, speech recognition has to acquire speechas an analog signal, and internet connections via digital subscriber line(DSL) IC’s acquire and transmit data via an analog front end (AFE). Itis possible to increase the number of examples. The fact is that we livein an analog world, and the more electronics becomes a part of our dailylives, the more common mixed-signal IC’s will become. A recent marketanalysis shows that in the near future the main driving force behind thesemiconductor industry will not be the computer industry any more, butcommunications [McCl00]. Communications is an area which is based onRF and mixed-signal electronics, and this fact sets a good background tocontemplate on challenges in producing high-quality, low-cost mixed-signalIC’s.

1.1 Testing: The Hidden Challenge

Whether a given functionality can be designed and produced into an ICbrings almost always design and manufacturing challenges into mind. Athird group of challenges is almost always overlooked and heavily underes-timated. This group consists of the challenges related to testing the IC inorder to guarantee its quality.

When the IC market is considered, the customers are the system developers.For the developed IC to function correctly on a system board, importanttechnical features have to be verified before it is shipped to the customercompany. In the examples given in the previous section, many importanttechnical features such as speed (e.g. networking applications) and outputsignal distortion level (e.g. audio applications) are key to the performanceof the IC’s and so the verification of these features are always required bythe sale contract.

In general, testing challenges can be classified as test software-, test hardware-and access-related challenges. Test software includes test generation, which

1.2. ANALOG AND MIXED-SIGNAL TESTING 3

is the combination of procedures/algorithms for finding good test signals,i.e. signals by applying which we can almost surely know whether the ICwill function correctly. Test hardware is the hardware framework that isresponsible for applying test signals and measuring the IC response to thesesignals. The performance features of the test hardware such as speed, noisefigures, signal sourcing and measurement ranges, etc. have to fit the speci-fications of the tested IC, or, the device under test (DUT). And finally, thedesign should be adapted so that the IC nodes that have to be measuredfor testing are accessible.

1.2 Analog and Mixed-Signal Testing

Historically, digital and analog testing have developed at very differentpaces, causing analog test methodology to be in a far earlier stage todaythan its digital counterpart. CAD tools for automatic test generation andtest circuitry insertion are available already since two decades for digital cir-cuits. The main reason for this is the ease of formulating the test generationas a mathematical problem due to the discrete signal and time values. Thedistinction between what does and what does not work is crisp and clearfor digital circuitry. For analog, on the other hand, the question can betterbe stated as ‘how good’ the circuitry works. Does an analog-to-digital con-verter (ADC) work correctly when it delivers a signal-to-noise ratio (SNR)of 69.99dB, when the specified minimum performance figure is 70dB? Doesthe system board application suffer from this underperformance? For ana-log designs, the definition of fault-free and faulty circuits is much morea matter of specification thresholds and sensitivity of application than asharp distinction as in the case of digital circuits.

1.2.1 Analog vs Digital Testing

For analog circuitry, the generation of optimal test signals based on designtopology is still not fully automated. As opposed to the digital approachbased on the gate-level netlist, analog testing still relies mainly on a black-box approach, where the specifications of the circuitry are verified withoutpaying attention to the structure or circuit layout. Another lagging issue isthe usage of standard design methods to make the circuitry easily or better


testable (Design for Testability, DfT). Scan chains are used in synchronousdigital circuitry for this purpose. A comparable analog approach still doesnot exist. Similarly, the modeling of process defects and the usage of thesemodels for developing and improving test signals is already standard prac-tice for digital circuits for more than two decades whereas similar methodsfor analog circuitry are just beginning to be applied by some manufacturers.For some of these issues, alternative approaches are still in research phase.For some others, there are technically feasible alternatives but the exist-ing production infrastructure and cost of changing present test methods isslowing down the acceptance of these methods. In table 1.1, a summary offundamental differences between digital and analog testing is presented1.In table 1.2, the present situation in digital and analog testing is compared.

Digital Design and Testing Analog Design and Testing

Discrete signal values Continuum of signal values

Discrete time instants1 Continuous time

No coupling between building blocks Coupling between building blockscan be significant

Systematic design with synthe-sis based on hardware descriptionlanguages1

Less systematic design, automaticsynthesis at research phase

High structural complexity, largenumber of elements

Lower structural complexity, highfunctional complexity, small numberof elements

Absolute distinction of fault-free/faulty circuit

Distinction of fault-free/faulty cir-cuit depends on tolerance valueschosen

Low sensitivity to crosstalk andnoise

Very high sensitivity to crosstalkand noise

Low sensitivity to process parametervariations

Higher sensitivity to process param-eter variations

Table 1.1: Fundamental differences between digital and analog design andtesting

1The indicated points apply only to synchronous digital circuits


Digital Testing Analog Testing

Automatic test generation based oncircuit netlist

No automatic test generation basedon circuit netlist

Standard DfT inserted automati-cally and used extensively

No standard DfT, ad hoc access cir-cuitry

Testing donimantly structural Testing dominantly functional

Standard fault models used No standard fault models used

DfT does not commonly affect theperformance

DfT often affects the performance

Table 1.2: Current state in digital and analog testing

1.2.2 Analog/Mixed-Signal Challenges

1.2.2.1 Test Software-Related

The IC manufacturing process is neither deterministic nor fully controllable.Microscopic particles present in the manufacturing environment, slight vari-ations in the parameters of manufacturing steps and human errors can alllead to the geometrical and electrical properties of an IC to deviate fromthose generated at the end of the design process. Tests applied to an IChave to be able to discriminate between fault-free and faulty IC’s in a rea-sonable amount of time. If the test is not sufficiently effective, this cancause faulty IC’s to be delivered or fault-free IC’s not to be delivered. De-livering a faulty IC will result in decrease in the quality and reliability of thefinal product. Not delivering a fault-free IC, on the other hand, costs theIC manufacturer - and eventually the consumer - extra money. Conversely,if a test perfectly discriminates between faulty and fault-free devices butrequires a long time for measurements and computation, then this alsomakes the IC more expensive since test time has a significant share in theoverall IC costs. To summarize, the generation and evaluation of effectivetests is a very important issue in the production of an IC that has directconsequences in the price and quality of the final product.


For digital circuits, algorithms for the generation of test patterns basedon gate-level netlist exist since as early as 1960’s [Roth66],[Goel81]. With-out the so-called ATPG (Automatic Test Pattern Generation) methods, itwould certainly be impossible to produce the large digital IC’s of the lasttwenty years at reasonable costs and quality. A similar test generation so-lution for analog testing became necessary with the increasing integrationof analog and digital functionality on one chip. The analog test communityhas also been aiming at a solution comparable to that in digital, but theanalog version of the problem is not solvable by similar analytical tech-niques. In the case of digital, the discreteness in time and signal values,the well-defined fault propagation paths and topological boundaries of faultinfluence have simplified the problem to some extent with respect to theanalog case. As a result, algorithms have been developed based on calcu-lating the signal changes introduced by faults and logic rules to find inputcombinations to create changes between fault-free and faulty behavior (pathsensitization) and propagate these changes to the primary outputs. A sim-ilar approach can not be applied to analog circuits. The main reasons forthis are:

• There are not only two choices of signal values to choose from, but inprinciple an infinite number of signal values are possible. The choicebetween two specific signal values can cause better or less good resultsrelated to observing the fault at the outputs.

• The time variation properties of analog signals bring an extra dimen-sion to the problem, since applying an AC, DC or transient test canbe more or less efficient depending on the circuit and the targetedfault.

• It is not possible to make a one-to-one link between the functionand structure of analog circuitry such as in digital circuits. Given aparticular topology, there is no general way of determining which partof the functionality is of interest and what the related performancelimits are.

• The propagation of fault effects to the output is not possible in thedigital sense, because of two reasons. First, the effect of a fault cannot be modeled to propagate in one direction as is the case in digi-tal. The fault effect propagates in all directions and the calculation


of this propagation pattern becomes therefore much more complexthan in the digital case. Secondly, in analog circuits, the informationthat a fault is present at a certain node does not readily comprisethe signal value information for that node, making time consumingcalculations of signal values necessary. Nonlinearity, loading betweencircuit blocks, presence of energy-storing components and parasiticsfurther complicate these calculations.

The obstacles presented above have kept analog netlist-based (i.e. struc-tural) test generation from being applied in practice. Research is still donein this area, and the application of netlist-based test generation in prac-tice requires a breakthrough in terms of the computational costs and gen-eral applicability. Today, specification-based testing (checking whether thespecifications are met) and functional testing (checking the functioning ofthe circuit with a standard input) are the dominating methods in analogtesting.

One point of view can be that, since the circuit specifications are the man-ner which fit more into the way of thinking about analog designs, it isnecessary to formulate and think about the analog test generation problemin a completely different manner. A way of doing that would be linking itwith analog synthesis techniques. Analog synthesis problem can be definedas ‘generating an analog netlist from a given function description’ (whichactually happens routinely in the case of digital, by means of hardwaredescription languages such as VHDL and digital synthesis tools). If thisproblem is solved, then this will open a possibility for solving the analogtest generation problem in a similar way, since for this test signals need tobe generated based on the netlist, which can be seen more or less as thereverse problem.

Unfortunately, a satisfying solution to the analog synthesis problem has notbeen found to this day. The research on this subject [Kras99], [Deby98],[Leen91] has been going on for two decades already, and the results are stillnot so far that any analog block design can be made from a description[Ohr99]. So the alternative of solving the analog test generation problembased on these methods remains unfeasible for the time being.


1.2.2.2 Test-Hardware Related

The most significant developments in mixed-signal testing in the last twodecades have been in mixed-signal test hardware. Despite this, the evo-lution in design, technology and integration levels has been so fast that anumber of important problems for future products are expected to arisebecause of the insufficient accuracy in signal sourcing and measurementequipment. It is predicted in the 1999 edition of the International Tech-nology Roadmap for Semiconductors that tester parameters such as noisefloor, clock speed and clock jitter will have to continue to be improved, al-though the existing techniques will fail to support this rate of improvementstarting from as early as 2001 [SIA 99].

1.2.2.3 Access-Related

Until today, the semiconductor industry has been keeping up with the pre-diction made by Gordon Moore in 1965, that the functionality per chipwill double every 1.5 to 2 years. This growth of the IC integration levelis predicted to continue in the coming years, under the pressure of thesemiconductor market to conserve the increasing functionality/price andperformance/price ratios.

The consequence of increasing integration is that less functionality is di-rectly accessible from the IC pins. The expected growth of transistors perIC pin in the coming years is shown in figure 1.1 [Zori99]. The result ofthis growth is that with every product generation there are more internalcomponents and blocks which have to be tested by indirect access or bymeans of adding circuitry to maintain the possibility of access. Techniquesof modifying the design to ensure testability for digital parts are fully auto-mated and standard for synchronous circuits at the moment, but the sameis not true for analog. Most of the techniques categorized as BIST (Built-in Self-Test) and DfT (Design for Testability) are in the research phase foranalog designs. It is possible to use ad hoc methods to make a numberof internal lines accessible from the primary input and outputs of the IC,although doing this without decreasing the performance can be difficult foranalog circuits [Nagi99].

1.3. MOTIVATION AND PROBLEM DEFINITION 9

100

200

300

400

500

600

700

800

00.25 0.18 0.13 0.1 0.07 0.05 0.035Feature size, mµ1997 ‘99 2000 ‘05 ‘08 ‘11 ‘14

Testing

com

ple

xity

index

inth

ousands

oftr

ansis

tors

per

pin

Figure 1.1: Increase in test complexity for digital circuits due to integrationas predicted by the International Technology Roadmap in 1998 [Zori99]

1.3 Motivation and Problem Definition

During the begin years of the IC industry, when the level of integrationdid not exceed tens of transistors or a few gates, the design and testingactivities were all done by people understanding the manufacturing mech-anisms as well as circuit theory [Maly98]. Today, this is not true any more.The enormous diversity of product types, manufacturing techniques andthe complexity of designs force engineers to specialize, making abstractionsand focusing on one level of the design and production procedure. Test en-gineers, however, do not have this luxury. The definition of an efficient test


procedure for an IC requires a good understanding of the IC functionality,the manufacturing process and the test equipment. This being a difficulttask, the tools available for making links between these platforms are stillnot completely mature and standardized.

As explained in the previous section, testing of mixed-signal IC’s presentsproblems for all of test software, test hardware and access domains. Thequality and price of mixed-signal IC’s are being heavily affected by testproblems in each domain. Having stated that the test solutions are morestandardized for digital circuits, the mixed-signal test community will haveto come up with solutions that are compatible with existing digital methods.

There is a general tendency in the EDA (Electronic Design Automation)industry to regard the design-test link as a set of tools which enable thesimulation of generated tests. In the last decade, a number of EDA compa-nies have released tools that give this possibility [Bate92], [Analog]. Otherresearchers have developed software that is aimed at the automatic man-agement of hardware test resources [Mieg98]. An issue that has not beenaddressed in the mixed-signal design-test link methodology is a test gener-ation method that takes the design as starting point and makes it easier forthe designer to drive the test generation process based on his design infor-mation. Another important issue is, once the test signals and measurementsrequired are known, to check whether these are sufficiently effective withrespect to the IC design and the manufacturing process. These two issuesare the motivations of the research described in this thesis.

In figure 1.2, an analysis of the fundamental problems in testing as depictedby Maly [Maly97] is shown. In this diagram, the two fundamental problemsare identified as test bandwidth and test quality and specific challenges arepointed out for solving these problems. For mixed-signal testing specifically,other test hardware-related challenges such as noise floor and accuracy oftiming measurements will have to be added to this picture. The objectiveof this thesis can be described as solving a part of the problem under thecategory ‘incomplete test set’.

To summarize, the problem treated in this thesis can be defined as devel-oping the concept of a framework linking mixed-signal IC design and testenvironments. This framework must enable an IC development team to

. develop test programs in shorter time,

1.4. OUTLINE 11

FUNDAMENTAL TEST PROBLEMS

INSUFFICIENT TESTING BANDWIDTH INADEQUATE TEST QUALITY

INSUFFICIENT SPEEDOF TESTING

DECREASING CIRCUITOBSERVABILITY

INCOMPLETE TESTSET

SIMPLISTIC FAULTMODELS

Tester PinElectronics

TesterArchitecture

GrowingDie Size

Too CostlyDfT

Immature TestGeneration

Methodologies

Too HighComplexity of

Fault Simulation

Lack ofUnderstanding ofFault Mechanism

Figure 1.2: The fundamental test problems and their causes [Maly98]

. debug test programs in shorter time,

. automatically generate test programs that will guarantee high IC quality.The potential obstacles and opportunities for the development of a design-test framework satisfying the above conditions will be pointed out, and so-lutions to some key problems will be suggested in this thesis.

1.4 Outline

This thesis is organized as follows:

Chapter 2 covers the description of the mixed-signal test problem, withdiscussions of present and future challenges. The chapter begins with adescription of mixed-signal IC architectures. The existing industrial testmethods, various steps of testing and the main criteria for each step arethen subsequently discussed. After this, present IC market requirementsand their implications for mixed-signal testing are analyzed. Following this,the research areas and state of the art in mixed-signal testing research areexplained. This overview of the existing situation is followed by an overviewof future expectations in mixed-signal IC design and IC technology, from atesting point of view. Finally, the potential of a design-test link for being asolution to some of the discussed mixed-signal test challenges is discussed.

Chapter 3 focuses on the design-test link. The conditions for linking designand test are discussed for the various levels of design. The usage of sim-ulation to support the design-test link, the possibilities and challenges are


pointed out. The state of the art in the various domains of the design-testlink, such as virtual test, test plan generation and test program evaluationare summarized. Based on these discussions, a general framework for adesign-test link is defined. A systematic data flow between design and testenvironments is described.

Chapter 4 presents the implementation of a design and test frameworkbased on the concepts defined in chapter 3. The framework is meant for thedesign and design evaluation of mixed-signal circuits. The implementationincluding the design and test databases, and the software tool developed fortest plan generation are described in detail. The description of the designand test of an example IC is also included in this chapter. The generatedtest plan, test results and discussion of experiences are presented.

In chapter 5 another part of the design-test link is discussed: the evalua-tion of the generated test plan. In this chapter, arguments are given fora defect-based test evaluation and the challenges in performing this taskwith analog simulation methods are explored. The existing methods formaking fault simulations computationally less complex and more feasiblefor practical applications are described. The advantages and disadvantagesof each method are pointed out, and a complexity analysis is presented foran existing method.

Chapter 6 presents a new fault simulation methodology based on DC-biasgrouping of nonlinear circuits. The simulation method is meant for tran-sient simulation of nonlinear circuits, but some of the concepts describedcan also be applied to DC and small-signal AC simulation of these cir-cuits. First, the methods DC-bias grouping, one-step relaxation and linearequation update are described. The implementation of these methods ina prototype simulator is explained in detail. Two example analog circuitsare simulated with the prototype simulator, and their results are comparedwith simulations using the same simulator core in a standard simulationconfiguration. The results show that a CPU time reduction of about 30%is possible by using the described method.

The main conclusions drawn from the work described in the previous chap-ters are presented in chapter 7, and recommendations for future researchare made.

1.5. BIBLIOGRAPHY 13

1.5 Bibliography

[Analog] Saber-IC Pro website, http://www.analogy.com/Test/Apptech/sabericpro.htm.

[Bate92] S. Bateman and W. Kao, “Simulation of an Integrated Designand Test Environment for Mixed-Signal Circuits,” in Proc. Inter-national Test Conference, 1992, pp. 405-411.

[Deby98] G. Debyser and G. Gielen, “Efficient analog circuit synthesiswith simultaneous yield and robustness optimization,” in Proc.IEEE/ACM International Conference on Computer-Aided De-sign, 1998, pp. 308-311.

[Esta99] “United Nations Survey Projects Number of Net Users ,” in eMar-keter, URL:http://www.estats.com/estats/041999 un.html.

[Goel81] P. Goel, “An Implicit Enumeration Algorithm to Generate Testsfor Combinational Circuits,” in IEEE Transactions on Comput-ers, Vol. C-30, March 1981, pp. 215-222.

[Kras99] M. Krasnick, R. Phelps, R.A. Rutenbar and L.R. Carley, “MAEL-STROM: efficient simulation-based synthesis for custom analogcells,” in Proc. Design Automation Conference, 1999, pp. 945-950.

[Leen91] D.M.W. Leenaerts, “TOPICS: A new Hierarchical Design ToolUsing an Expert System and Interval Analysis,” in Proc. Seven-teenth European Solid State Circuits Conference, 1991, pp. 37-40.

[Maly97] W. Maly, “SIA Road Map and Design & Test,” Oral presentationat UC Berkeley, April 1997.

[Maly98] W. Maly, H.T. Heineken, J. Khare and P.K. Nag, “Design-Manufacturing Interface: Part I - Vision,” in Proc. DATE Con-ference, 1998, pp. 550-556.

[McCl00] B. McClean, “Communications Applications to Drive Future ICMarket,” in EETimes.com, URL: http://www.eetimes.com, May2000.

http://www.analogy.com/Test/Apptech/sabericpro.htmhttp://www.analogy.com/Test/Apptech/sabericpro.htmhttp://www.estats.com/estats/041999% protect global let unhbox voidb@x kern .06emvbox {hrule width.3em}un.htmlhttp://www.eetimes.com

[Mieg98] M. Miegler, O. Kraus, H. Tauber, G. Krampl, S. Sattler andE. Sax, “Tester Independent Program Generation Using GenericTemplates,” in Proc. International Mixed-signal Test Workshop,1998, pp. 260-263.

[Nagi99] N. Nagi, “System-on-a-Chip Mixed-Signal Test: Issues, CurrentIndustry Practices and Future Trends,” in Proc. InternationalMixed-Signal Test Workshop, 1999, pp. 201-211.

[Ohr99] S. Ohr, “Synthesis Proves to be Holly Grail for Analog EDA,” inEETimes.com, URL: http://www.eetimes.com, June 1999.

[Roth66] J.P. Roth, “Diagnosis of Automata Failures: A Calculus and aMethod,” in IBM Journal of Research and Development, Vol. 10,July 1966, pp. 278-291.

[SIA99] International Technology Roadmap for Semiconductors, 1999 Edi-tion.

[Zori99] Y. Zorian, “Testing the Monster Chip,” in IEEE Spectrum, July1999, pp. 54-60.

14

http://www.eetimes.com

Chapter 2

The Mixed-Signal TestProblem: State of the Artand Boundary Conditions

2.1 Introduction

New developments in the IC industry often result in new challenges beingintroduced in the testing area. Technical changes in the way of designingor manufacturing IC’s usually have their impact on IC test. Advancedhigh-speed IC’s require even faster testers as well as new test methods todetect speed-related failures. IC’s with a higher level of integration requirenew DfT (Design for Testability) methods to access all embedded blocks.High-performance audio and video IC’s require more accurate measure-ment methods to be able to test their tight specifications. Besides theseand other technical developments, the ever-increasing market demands onthe IC production such as higher quality, lower costs, shorter developmentand production time have also drastic consequences on how IC’s should betested.

In this chapter, a general introduction will be presented on the currentstate of the art and future challenges for the testing of mixed-signal IC’s.In this context, a link will be made to the IC design and manufacturingtrends and the emerging test problems.

15

16 CHAPTER 2. THE MIXED-SIGNAL TEST PROBLEM

2.2 Mixed-Signal IC Architectures

The architecture of a mixed-signal IC can be defined as the top-level orga-nization of analog and digital sub circuits. The sub circuits making up theIC architecture will be called analog/digital blocks. In test terminology, alsothe terms macros and cores are used to identify blocks. The mixed-signalIC architectures can be divided into two general categories[Aren97]:

• Register-controlled analog IC’s, which consist for the most part ofanalog blocks (see figure 2.1(a)). The signal path is to a large extentanalog, i.e. the processing of the input data is performed mostly bymeans of analog circuitry. The digital blocks usually make up partsor whole of the control circuitry. Typical examples are one-chip-TVIC’s, amplifiers for audio applications, etc. [Zwem98].

• Digitized analog IC’s, having digital blocks in the signal path (seefigure 2.1(b)) and analog and mixed-signal circuitry in peripheralblocks (analog-to-digital converter, ADC and digital-to-analog con-verter, DAC) and phase locked loop (PLL).

The architecture of a mixed-signal IC has direct implications on how andat what cost the IC can be made testable. The testable design and testingof register-controlled analog IC’s often creates access problems. InsertingDfT for each block to be tested can override the area and performancelimitations. Multiplexers are often used to make analog blocks accessiblefor testing, although too many multiplexers along the signal path of a highperformance IC, e.g. an audio application requiring high signal-to-noiseratio (SNR) can degrade the performance. In this kind of IC’s, a trade-offhas to be found between testability and the other limitations.

The second category of IC’s are less complicated to test, owing to thefact that the analog blocks are peripheral. The ADC and DAC blocksare made fully accessible by means of scan blocks at one side and primaryinputs/outputs at the other. A PLL block, similarly, can be accessed bymaking only the output observable since it is connected to a primary inputwhere the locking frequency is applied. By using these access blocks, theanalog/mixed-signal circuitry can be accessed and tested individually. Thereader is referred to [Nagi99] for an up-to-date review of the industrialtesting of these standard blocks.

2.2. MIXED-SIGNAL IC ARCHITECTURES 17

Figure 2.1: Mixed-signal IC architectures: (a) register-controlled analogIC’s, and (b) digitized analog IC’s [Aren97]

Apart from the favorable accessibility of the analog blocks, the digitizedanalog IC’s also have the useful property that they have only a few typesof standard blocks (e.g. ADC,DAC, PLL). These blocks can be generalizedin terms of functionality so that general test methods per block can bedeveloped and reused with a different configuration as often as an IC ofsimilar architecture has to be tested. The blocks having a well-definedfunctionality so that they can be modeled fully for testing purposes will becalled macros. Mixed-signal testing methods based on dividing the IC intomacros make up the macro-based testing approach. The industrial testing ofdigitized analog IC’s consists almost always of macro-based testing [Flah93],


[Agra98], [Nagi99], [Engi99a]. This is less true for the register-controlledanalog IC’s since the underlying blocks have diverse functionality, therebymaking the definition of macros difficult [Aren97], [Zwem98].

Because of the highly variable nature of blocks and the possibility of hav-ing blocks with non-standard functions, the application of systematic testtechniques to register-controlled circuits is very difficult. The methods de-scribed in this thesis are in general applicable to digitized analog IC’s. Ex-tension to register-controlled blocks can be possible for production groupswhere the reuse of analog macros from a library (with small modifications)is common. The issues of design and test reuse will be discussed in moredetail in chapters 3 and 4.

2.3 Current Design and Test Practice

The description of the IC design and test procedures requires a certaingeneralization. In fact, the procedures in each development and productionline depends on the type of product, test facilities at hand and the customerrequirements for the particular product. It is, however, possible to draw ageneral line which summarizes the common patterns of mixed-signal testingin industry. This will be explained and illustrated in this section. A generaloverview of the design and test flow for mixed-signal IC’s is given in figure2.2. The test steps involved are the prototype and production testing steps.

2.3.1 Prototype Test

The prototype test consists of two testing steps, design debug and designevaluation (see figure 2.3). Design debug is the first and most informal testthat an IC undergoes. The designer uses dedicated measurement instru-ments to see whether the crucial functions of the IC are working correctly.At the design evaluation step, the main aim is to apply a full functionaltest and to measure the specified parameters.

During the prototype test, the primary aim is IC characterization. Insteadof a pass/fail decision, the outcome of the prototype test is a set of perfor-mance figures for the prototype IC. Decision on the required modifications ismade by the designer based on these figures. Because the prototype testing

2.3. CURRENT DESIGN AND TEST PRACTICE 19

IC Specifications

IC Design and

Validation

Product Manufacturing

Shipping

Prototype Manufactureand

Testing

Production Test

T E

S T

D

E V

E L

O P

M E

N T

Figure 2.2: Overview of design and test flow

is performed on only a small number of IC’s, the test time is not a primarylimitation. However, test choice and measurement accuracy is importantsince a full evaluation is required and undetected design flaws can causedelays in the whole product development process. The hardware used indesign evaluation is often VXI/GPIB based computer-controlled measure-ment systems. These systems are not optimized for speed or reliability butcan make high accuracy measurements. Apart from the measurements de-scribed above, evaluation test also includes batch measurements made onthe production test facility on a larger number of IC’s, in order to obtainthe statistical distributions of measured parameters. If some of the distri-butions obtained are not within the desired limits, then either a redesignis required or precautions are taken in the IC processing steps to ensure abetter distribution.


Prototype Manufacturing

Design Debug

OK? Design ModificationsNO

Design Evaluation

OK?NO

YES

YES

To IC manufacture

IC Design

Figure 2.3: Prototype test flow

2.3.2 Production Test

Production test is the common name for the test steps applied to each ICat the mass production stage. These steps are applied before and afterthe IC is packaged and are called wafer test and final test, respectively(see figure 2.4). The wafer test usually consists of applying and measuringDC and low-frequency AC signals. These are mostly general functionaland parametric tests, or tests in which e.g. the connections of power linesare checked. It is often not possible to apply high frequency tests or testswhich require very accurate timing measurements because of the insufficientcontact characteristics of the wafer probe pins. These kind of tests areapplied at the final test stage once the IC is packaged.

During the wafer test, the dies which are defective are marked. The diesthat pass the wafer test are then packaged and the final test is applied. Atfinal test, the bonding connections are checked, the digital test patterns arerun, and key analog specifications are measured. In some cases, the teststhat have already been performed during wafer test can be skipped in thefinal test in order to decrease the test time.


Final Test

Wafer Test

Packaging

OK?

OK?

NO

YES

NO

YES

Shipping

Figure 2.4: Production test flow

There are differences in the requirements and aims for prototype test andproduction test. First of all, prototype test is focused primarily on designweaknesses rather than on manufacturing defects, while the main aim ofproduction testing is to detect the defects resulting from the imperfectionsof the manufacturing process. Secondly, the test time is an important is-sue in production test since it contributes to the costs of each IC. Anotherdifference is the characterization approach in prototype testing in contrastto the pass/fail decisions in production testing. And lastly, there is a largedifference between the equipment and software used for prototype test andproduction test (except for the batch measurements during design evalua-tion). In high-volume testing expensive industrial testers are used which areoften faster and considered to be more reliable than the VXI-based modularmeasurement systems. Tester reliability is more important in productiontesting since a possible breakdown will bring the production line to a stopwhich is highly undesirable. These testers can perform measurements atspeeds required in mass-production testing, nowadays also equipped withDSP and test debugging software. The test software delivered with in-dustrial testers contains standard DSP functions such as FFT. The main


Feature Prototype Test Production TestFocus on Design correctness Manufacturing defectsTest time Not important ImportantTest approach Characterization Pass/failEquipment VXI/GPIB based Industrial ATE

Table 2.1: Differences between prototype and production tests

differences between prototype and production testing are summarized intable 2.1.

Besides the tester, another piece of hardware that also plays an importantrole in the testing of an IC is the Device Interface Board (DIB) (also calledthe loadboard). This is the board that forms the interface between thetester and the IC being tested. The DIB consists of extra circuitry such asdecoupling and load elements which are required to maintain the correctinteraction of tester channel with the IC under test.

To have an idea about the efficiency of the mixed-signal IC design andtest flow, it is necessary to look at the sequence and interrelations of theinvolved tasks in terms of the time they take. Before doing this, the test-related tasks and concepts will be defined here.

Definition 2.1 The description of the stimuli and measurements for a spe-cific test method for one macro, written in a test description language thatcan drive the test equipment directly is called a test function.

Definition 2.2 The complete sequence of test functions for an IC, writtenin a test description language that can drive the test equipment directly iscalled a test program.

A test program is complete in the sense that it is directly executable on thetest equipment without other additions. Thus, except for test functions,also commands for the configuration of the tester, inputs for the test controlblocks of the IC, and other steps necessary for a complete automatic ICtesting process are also included in the test program.


Definition 2.3 The high level description of the test program is called atest plan.

The terms test function, test program and test plan correspond to levels ofabstraction for the representation of tests. These representations can existfor prototype testing as well as production testing. For analog and mixed-signal blocks, the test plan is either a document describing test parameterssuch as test signals, time length, measurement type etc. or another higherlevel representation of the test program. An example of a test plan forprototype testing will be given in Chapter 4.

The term test development (see figure 2.2) will be used throughout thisthesis to correspond to the total test preparation process starting from thebasic specifications and structure of the IC, and ending in a test program.

In figure 2.5 the timing of test development activities with respect to theIC development milestones is given. The design activities are not explicitlypresented, only the milestones reached are given in order to sketch the timerelation between IC design and test. The milestones are based on a generaltop-down design approach. The interdependencies of the tasks can be seenin the figure. The digital test patterns are generated when the gate leveldesign is complete. The test generation for analog macros begins afteror shortly before the analog macros are completely ready. Test programpreparation corresponds to the making of a complete test program fromthe generated test signals and vectors. The design of interface circuitry isalso part of the test program preparation process. When the prototype isready, the test program and the DIB are debugged using the prototype.

The prototype test preparation and prototype testing proceeds in parallelwith the production test activities. The generation of the prototype test hasto be completed before the prototype is ready, although this is not alwaysthe case in practice. Design debug and evaluation is done (partially) inparallel to the debugging of production tests.

The additional time costs due to testing steps is shown with black arrows infigure 2.5, denoted as ‘IC TTM bottleneck’. TTM is the acronym for time-to-market, and is a parameter for the speed at which the product is broughtto market, and is defined as the time between specification of a new productand the time it is brought to market. TTM is a very important factor interms of industrial competition. The TTM contribution of testing tasks


Production testplanning Digital test

generation

Analog test generation Testprogram

preparation

Test programdebugging Testing

Prototype testplanning

Prototype testpreparation

Debuggingevaluation

TIME

IC specs Behavior-level

design

Gate-leveldigitaldesign

Analogcell

layout

Placementand Routing

Pre-production Mass production

Fully automated process

Partially automated process

Non-automated process

IC development milestone

IC TTM bottleneck

Analogcell

design

Figure 2.5: Timing of test activities with respect to IC development

will be discussed in more detail in section 2.4.3. It suffices to say at thispoint that especially the debugging of prototype/production test programsoften makes up a bottleneck for the speed at which mass production canbegin.

2.4 Market Requirements

2.4.1 Quality

IC quality is defined as the number of shipped products that do not satisfythe specifications divided by the total number of shipped products [Aren97].The yield of the manufacturing process, the effectiveness of the tests usedand the accuracy and reliability of the testing equipment are the factors thatinfluence quality. In the IC industry, quality is measured in PPM (partsper million), i.e., the number of IC’s that fail to satisfy the specifications

2.4. MARKET REQUIREMENTS 25

per million shipped IC’s. Another term in production that is related toquality is the defect level (also measured in PPM).

Definition 2.4 Defect level is defined as the ratio of the number of shippedIC’s that do not function as specified to the total number of shipped IC’s.

Throughout this thesis, defect level will be used to denote the quality of anIC. The aim of this section is to present the relation between the IC qualityand the effectiveness of the corresponding test program. First some basicdefinitions related to IC manufacturing will be presented.

Definition 2.5 The number of fault-free dies produced divided by the totalnumber of dies is called the process yield.

Y = Number of fault-free dies / Total number of manufactured dies

Definition 2.6 For a given production test step, the number of IC’s thatpass the test divided by the number of IC’s that have been tested is calledthe test yield of that test step.

Ytest = Number of IC’s that passed the test / Total number of IC’s thathave been tested

Definition 2.7 Any deviation in the electrical or geometrical propertiesof the manufactured IC from the values given by the IC layout beyond theexpected process variation is called a defect.

Definition 2.8 The effect of a defect on the electrical characteristics ofthe IC deviating from the specified behavior is called a fault.

In other words, a fault is the consequence of a defect, but it is also possiblethat a circuit with a defect has electrically no fault at all.


Definition 2.9 Let F ={f1, f2, ..., fn} be the set of all n faults which areconsidered for an integrated circuit C. Let T be a test program for C, whichis able to detect a set of faults Fd, where Fd ⊂ F and | Fd |= m. The ratiomn expressed as a percentage is called the fault coverage of T for C basedon the fault set F .

The main aim of IC testing is to keep the defect level as low as possible.In the case of an ideal test, all possible defects are detected and the defectlevel becomes 0. A real test can deviate from this ideal case in two ways:either by failing fault-free IC’s (type 1 testing error), or by passing faultyIC’s (type 2 testing error) [Will90]. Having a large number of type 1 errorscauses the IC costs to increase because of throwing away fault-free products.Having a large number of type 2 errors, on the other hand, causes defectiveIC’s to be delivered, i.e. the defect level becomes high.

Given an IC and the test program written for this IC, the probability ofgetting type 1 and type 2 errors depend on separate factors. Type 1 errorprobability is a function of tester quality [Will90] and test limits but notof the test method used, so this error type will not be discussed here anyfurther. The probability of type 2 errors, on the other hand, depends on thefault coverage of the applied test program and the process yield. In otherwords, the main aim of writing an effective test program is minimizing theprobability of type 2 errors.

Assuming that there are no type 1 errors, and that all testing is doneat one step, the probability of type 2 errors is equal to the defect level;since they both correspond to the probability of a defective IC passing thetest. Although these assumptions do not hold in reality, the relationshipbetween defect level, fault coverage and testing errors is still a strong one.This relation has been investigated by several researchers [Will81], [Will90].The simplest and most popular model of this relation has been presentedby Brown and Williams [Will81]. This model gives the relation betweendefect level, process yield and fault coverage as

DL = 1− Y (1−T ) (2.1)

where DL is the defect level, Y is the process yield and T is the faultcoverage. This model is based on the assumptions that

• the set of all possible faults is finite and known beforehand,


• all faults are equally probable and independent,

• the probability of type 1 errors is zero.

Although the above assumptions are not realistic for an accurate estimationof the defect level, the relation presented in equation 2.1 gives a rough ideaabout the nature of the relation between product quality, process yield andthe fault coverage of the test program. In figure 2.6, this relation is shownfor a range of yield values. It can be seen in this figure that for a givenprocess yield, a high fault coverage is required for a low defect level.

95 95.5 96 96.5 97 97.5 98 98.5 99 99.5 1000

200

400

600

800

1000

1200

Fault coverage, %

Def

ect L

evel

, PP

M

Yield = 98%

Yield = 98.5%

Yield = 99%

Yield = 99.5%

Yield = 100%

Figure 2.6: The relation between process yield, defect level and fault cov-erage

The described relationship between process yield and fault coverage hasnot yet become a standard basis for the testing of analog and mixed-signalblocks. The methods that make the link between manufacturing process


defects and testing are called ‘defect-oriented testing’ (DOT) methods. Thework related to DOT methods for analog blocks has so far been limitedto academic institutions, and only recently a few examples of industrialexperiments have been published [Xing98], [Beur99]. It remains, however,a fact that a realistically obtained fault coverage figure is the only accurateway of optimizing the test effectiveness and, in many cases, decreasing thetest time by preventing overtesting. With the increasing market pressurefor lower defect levels and lower IC costs, it is expected that the usage ofanalog tests with high fault coverage will have to increase in future.

2.4.2 Cost

IC costs can be divided into the development and production costs of theIC. Test development costs are included in the IC development costs, andcost of testing an IC constitute a part of the production costs. In gen-eral, test development costs depend on the time spent on test generation,prototype testing and production test debugging. These issues are also re-lated to TTM, which is even more important than cost at the developmentphase. The cost of production testing an IC has, on the other hand, directimplications on the IC costs because the production test is applied to eachIC. Therefore, these costs will be discussed in this section. The costs ofproduction testing depend on the following factors [Engi99a]:

• the tester used,

• test yield (see definition 2.6),

• test time of a fault-free die,

• average test time of a faulty die,

• additional loading/handling times.

In general, for a fault-free die, the IC test cost is given by the costs ofrunning the tester per unit time multiplied by the total test time per IC.However, for a given industrial test facility, consisting of ATE and proberor handler, and a given test yield, the manipulatable test cost parametersare the test time of a fault-free product and the average test time of a faultyproduct. For the average cost of testing a die, the parameters test yield and


average test time of a faulty die must also be taken into account. The testtime of a fault-free die is the total time the complete test program takes tomeasure and process measurement data. The fact that the test time of afaulty die plays also a role implies that the tests should be ordered accordingto their success in detecting defects. It has been suggested [Milo94] to usethe fault coverage for making an optimal ordering of the tests to decreasethis test time. In general, a large amount of the test time of a mixed-signalIC is dominated by the tests for the analog parts. IC’s where analog blocksmaking up 10% of the IC circuitry account for 60% or more of the test timeare not uncommon [Nagi99],[Engi99a]. For this reason, the compaction ofanalog tests is an important issue in mixed-signal IC testing. However, itshould also be noted that wafer loading or package handling times are alsoimportant parameters for test time. In the situations where the handlingtimes are comparable with the test time, decreasing the test length willobviously not be sufficient. In these cases alternative solutions such asmultisite testing [Evan99] have to be applied, in order to make use of (apart of) the handling time to test another IC.

The remaining factor, the test yield, depends on the process yield and thepresence of test and measurement errors. Improving the process yield is be-yond the scope of this thesis; however, design for manufacturability (DfM)techniques can be used with the results of fault extraction to decrease theprobability of some faults. The probability of test errors can be decreasedby acquiring a good fault list for the IC and assessing fault coverage figuresfor the tests as explained in the previous section.

It becomes clear from the discussion of cost and quality issues of an ICthat having tests with high fault coverage can improve both the quality andthe cost figures. On the other hand, the accuracy of the estimated faultcoverage highly depends on how realistic the fault set at hand is. At presentthe fault models [Soma96a] for analog parts are not satisfactory for basingPPM estimates on, and extensive research is needed in this area in orderto make use of fault-based techniques in quality and cost improvement.

Another test-related factor that contributes indirectly to the cost of anIC is the area contribution of the built-in self-test (BIST) and design fortestability (DfT) circuitry. In semiconductor industry, the opinions aredivided on this subject. In fact, adding BIST and DfT in an efficientway can help decrease the test development and debugging costs, thereby


compensating for at least a part of the additional area cost. Studies ofcosts of these methods have been made, although these estimation methodstake digital IC’s into account such as in [Chen99]. For mixed-signal IC’s ageneralized framework for estimating this kind of costs does not yet exist,except for the ‘home-grown’ IC cost models of individual manufacturers[Engi99a].

Finally, on-line debugging of tests has also often been pointed out as acost factor [Bate92], because of the high costs of operating the expensiveATE. For this reason, research into ‘first-time-right’ tests and test simula-tion software employing tester models has gained momentum. Some ATEmanufacturers supply debugging software for off-line debugging, but thedebugging of the device under test (DUT) with the DIB is still performedfor a large part on-line. Standardization in terms of tester and interfaceboard models have not been achieved yet for mixed-signal circuits.

2.4.3 Time-to-Market

Experience shows that roughly one third of the total manpower in thedesign and test trajectory is spent on test development, programming anddebugging [Brem98]. The effect of test activities on TTM is actually moreimportant than given by this figure, because most of this time is spent atthe end of the design cycle, when relatively little time is spent on designand evaluation activities, and test debugging dominates.

As far as the mixed-signal blocks are concerned, the test issues that aremost related to TTM are the development and debugging of test programs.The general tendency for mixed-signal parts is to start test developmentonce the design and sometimes even the prototype is ready [Kao 92]. Alarge part of the debugging is done normally on the tester using the ICprototype [Engi99a]. Test programs with less complexity and methods thatgenerate first-time-right test programs can help to a degree to decrease thecontribution of test debugging to TTM. However, this is a very complicatedproblem for mixed-signal circuitry, since analog effects from the interfacecircuitry such as noise and loading, grounding problems and similar effectsare very difficult to represent with a generalized model. Simple programbugs or errors related to the configuration of the ATE can, however, beprevented by (semi-)automating the test development process.

2.5. MIXED-SIGNAL TEST: CURRENT ISSUES AND CHALLENGES 31

2.5 Mixed-Signal Test: Current Issues and Chal-lenges

The pace of change in the field of analog testing has not been comparable toits digital counterpart. The main development until now has been namelyin the area of test hardware and DSP methods, while work done in subjectslike test generation, fault modeling and diagnosis has failed to converge tostandard applications. Here, the state of the art in the main mixed-signaltest issues will be summarized briefly.

2.5.1 Test and Measurement Environments

The most important developments in the testing of mixed-signal IC’s hasbeen the developments in the ATE hardware and software. The accuracy,noise figures and speed of ATE has developed very fast in the last decades,but these issues are expected to remain challenges for ATE designers in thefuture [SIA 99], [Groc97].

The usage of DSP-based analysis methods and coherent testing in mixed-signal ATE has been an important turning point for mixed-signal testing.Coherent testing relies on the full synchronization of analog and digitalparts in the test equipment and is the basis of dynamical measurements inmodern ATE. Roughly stated, the coherency principle is based on choosingthe number of samples of the measured periodic signal N , with respect tothe number of periods measured M , such that M and N are two relativelyprime integers [Maho87]. Coherent testing has many advantages. For onething, the test speed can be governed by M rather than by the speed ofthe device under test (DUT). Also, the accuracy of dynamic measurements,which are very important for the testing of mixed-signal blocks, increases[Groc97].

In general, the DSP methods offer a level of flexibility and repeatabilitywhich would be impossible with conventional analog measurements. Theanalysis of captured data in the digital domain has also changed the mea-surement equipment capabilities substantially by making e.g. the conceptof ‘virtual instruments’ possible. Virtual instruments are measurement op-tions in the form of software-emulated instruments.


As to ATE software, the major advances of the recent years is the introduc-tion of the ‘virtual test’ concept. Virtual testing is the off-line verificationand partial debugging of test programs in a simulation environment. Suchan environment consists of tester models, a circuit simulator and possiblydebugging functions in order to verify the working of the developed testprogram before the prototype is produced. The aim is to make test debug-ging faster and optimistic results are reported in terms of TTM reduction[Einw98]. At present, most industrial ATE is delivered with some virtualtest and debugging capability.

2.5.2 Design for Testability (DfT)

The work done on mixed-signal DfT methods during the last decade hasfocused on

• developing a mixed-signal extension to the IEEE boundary scan stan-dard (IEEE 1149.1) to enable access to inputs and outputs of analogblocks [Park93], [Sunt95], [Whet96],

• evaluations on the performance of the mixed-signal test bus [Lofs96],

• other DfT structures for enabling testing of analog blocks.

The mixed-signal extended version of the IEEE 1149.1 standard is calledIEEE 1149.4 Mixed-Signal Test Bus and is recently approved as an officialIEEE standard. The mixed-signal test bus IEEE 1149.4 is slowly startingto be used by the semiconductor industry. A reason for this limited useis that the standard is actually meant for board level test, so it is notsuitable for most IC-level tests. Most of the crucial tests for analog andmixed-signal modules are dynamic and high speed, which fall outside theapplication domain of IEEE 1149.4. The standard will require a few yearsbefore the industry is fully aware of its possibilities for board level test,and IC level usage for static tests may follow once IEEE 1149.4 becomes acommon DfT method for mixed-signal IC’s.

The rest of mixed-signal DfT research focuses on developing configurableanalog blocks (mostly operational amplifiers [Brat95], [Soma90], [Reno98])for making access to embedded circuitry possible. Current-based testing


has shown to have a high fault coverage for the testing of ADC’s , andanother method has also been described [Lamm98] for testing a completeanalog part of an IC by monitoring the proportions of various source lines.DfT structures for high-frequency circuits is also becoming a focus point.Recently, a DfT structure employing undersampling has been suggested andmeasurements at frequencies such as 1.1 GHz have been reported [Maso99].

The acceptance and application of the research results on mixed-signal DfTis very careful and slow in the IC industry. In most of the mixed-signalIC’s with a digitized analog architecture, the analog blocks are peripheraland access problems are solved to a great extent by using scan cells atthe border of digital circuitry as done in [Flah93]. For register-controlledanalog architectures, access remains a problem, since the IC developers areoften not very willing to insert DfT structures inside their analog circuitrybecause of the risk of degrading the performance, especially for high fre-quency and high performance circuitry. At present, the industrial practicefor mixed-signal DfT is still to use analog switches/multiplexers and digitalscan cells to reach analog/mixed-signal blocks.

2.5.3 Built-in Self-Test (BIST)

Built-in self-test is the common name for self-test circuitry on the IC. Thegreatest motivation behind analog and mixed-signal BIST is attaining thespeed and quality which is not possible or very expensive to get by usingexternal ATE. In general, the usage of BIST structures for analog on-chiptest is aimed at improving the test costs and quality by [Sunt97]:

• Decreasing the test time/costs,

• Making it possible to test a mixed-signal IC on digital ATE

• Making more accurate and at-speed measurements possible withoutsuffering from the ATE limitations and available ATE for differenttest phases (chip, board, system, etc.).

As for test development and debugging time: test development time istypically included in the design time of BIST. The reuse of configurableBIST specialized on one type of analog macro makes it possible to minimize


design time for BIST. Test debugging is in this case not necessary, assumingthat the BIST covers all the test requirements for the block.

The research in mixed-signal BIST has a long history. There have been alarge number of BIST designs developed for generating standard test stim-uli on-chip, for carrying out standard tests for often-used blocks such asADC and DAC, and test output processing techniques such as signatureanalysis. Among the existing mixed-signal BIST methods, important ex-amples are HBIST [Ohle91], MADBIST [Tone96], HABIST [Fris97] andOBIST [Arab97]. HBIST is a global BIST scheme for the whole IC, andincludes both self-test modes both for digital and analog blocks and also amode for on-board interconnect testing. HABIST, OBIST and MADBISTconsist of methods for testing analog blocks alone. HABIST uses histogrammethods to produce a signature of the activity at the selected nodes of thetested block. OBIST is based on a scheme which makes all analog blocksact like oscillators in the test mode, check the oscillation frequency anddecide on whether the blocks are faulty. MADBIST is a specification-basedon-chip testing scheme, including on-chip test stimulus generation and mea-surement circuitry for measuring typical specifications of standard analogblocks (i.e. harmonic distortion of an ADC).

In the recent years, commercially available mixed-signal BIST has appearedon the market. The mixed-signal BIST solutions from LogicVision [EET 97]consist of BIST designs specializing in two of the most frequently testedanalog macros, the PLL [pllBIS] and the ADC [adcBIS]. Using these testmodules, it is possible to run a number of standard functional pass-fail tests[EET 97], where the operation limits are either hard coded in the BISTcircuitry or entered by the user. Another option is the BISTMaxx suitefrom Fluence [BISTMa], which is based on a set of tools including OBISTand HABIST described in the previous paragraph. BISTMaxx includeshardware structures to be used on-chip and software tools to enable BISTconfiguration and the generation of supporting test algorithms.


2.5.4 Automatic Test Program Generation (ATPG)

Automatic generation of test programs for analog and mixed-signal circuitsis traditionally macro-based and functional. Testing in this sense corre-sponds to the measurement of a set of specifications and usage of predeter-mined specification tolerance boxes for making the pass/fail decision. Thisapproach is called functional ATPG [Soma96b]. In recent years, however,the large scale of integration and the high demand for quality has beenforcing another direction in analog test: generating and evaluating testsbased on the circuit structure (read: netlist) and the set of potential faults,thus creating the structural ATPG approach.

While functional test development methods are practical for developingtests for design evaluation, it is difficult to tell whether they are actuallyefficient. This is because no well-defined correlation exists between speci-fications and process defects, and thus it is not possible to tell that a testthat checks the specification also checks a large amount of possible defectsthat can occur in the production. This is a disadvantage when test timeis valuable and one wants to use it as efficiently as possible in order todecrease the defect level. These arguments make structural test generationattractive especially for production testing. However, analog structuralATPG is still in a very primitive phase. It is practically impossible to de-velop a method that can generate tests based on any netlist. The reasonsfor this have been discussed in section 1.2.2.1. Because of this difficulty,most of the structural methods constrain themselves to (combinations of)few types of inputs (mostly sine, ramp, step, etc.) and standard AC or DCmeasurements [BenH96], and use various methods and criteria to select aneffective set of these inputs. With respect to the selection method used,structural ATPG methods can be categorized as:

• Sensitivity analysis based methods: Sensitivity analysis makes use ofa sensitivity matrix, which consists of elements each of which relatesthe derivative of an output with respect to a circuit parameter, i.e.,

S =∂v∂p

(2.2)

where S is the sensitivity matrix, ∂p is the vector of perturbationsin the parameter values pi, and ∂v is the vector of corresponding


changes in the output voltage values. The sensitivity matrix canbe used as an accurate relation between the circuit operation andthe parameter values, however, for large circuits can lead to largesimulation times. The sensitivity matrix approach has been used inmany works, a good example is [BenH96], where sensitivity analysishas been used to select test stimuli values for a predefined set ofinput types (voltage level for DC, frequency for AC, etc.). This worktakes the advantage of sensitivity analysis to generate tests also forparametric faults by calculating minimum and maximum values forelement deviations. The test generation is done by taking each faultin the fault dictionary into account and calculating the best AC andDC test inputs for detecting the fault.

• Linearity based methods: These methods are based on the linear sys-tem theory and are applicable to systems which operate in their linearregions in both fault-free and faulty state. In [Bali95] and [Pan 97]examples of such ATPG methods are given. The main disadvantageis that it can not be assumed in general that the faulty circuit willstill be operating in its linear region. It can not even be assumed thatthe number of states will remain the same for the faulty circuit. Theonly application area of these methods is possibly detecting the softfaults in linear circuits.

• Fault simulation based methods: These methods rely on fault simu-lations in order to choose and configure test stimuli out of a numberof predefined signals. In [Kaal96] an example of such an ATPG toolis given. The main disadvantage of this type of tools is the largesimulation time needed to simulate each fault. Development of fasterfault simulation methods (see chapter

Documents

Linking Mixed-Signal Design and Test · (TTM) for mixed-signal IC’s. The various aspects of the mixed-signal test problem are discussed in chap-ter 2 of this thesis. A general discussion