8/12/2019 Lesson Plan LPV

1/2

Class No. TitlePercentageof portions

covered1. Introduction:

1101 - 06

1. Need for low power VLSI chips Digital Integrated circuits

2. Sources of power dissipation on3. Emerging Low power approaches

4. Emerging Low power approaches.

5. Introduction to Verilog

. !h"sics of power dissipation in #$%S de&ices.

2. Device & Technology Impact on Low Power:

2307 - 12

1. D"namic dissipation in #$%S

2. 'ransistor si(ing ) gate o*ide thic+ness

3. 'ransistor si(ing ) gate o*ide thic+ness

4. impact of technolog" Scaling

,. impact of technolog" Scaling

. 'echnolog" ) De&ice inno&ation

3. Power estimation, Simulation Power analysis

3613 - 1

1. S!I#E circuit simulators-2. gate le&el logic simulation

3. capaciti&e power estimation

4. static state power

,. gate le&el capacitance estimation

. architecture le&el anal"sis

. architecture le&el anal"sis- data correlation anal"sis in DS!

s"stems $onte #arlo simulation

!. Probabilistic power analysis/

"0

20 - 26

1. 0andom logic signals

2. 2. proailit" ) freuenc"

3. proailistic power anal"sis techniues

4. proailistic power anal"sis techniues,. signal entrop".

. signal entrop".

. signal entrop"

". Low Power Design Circuit level/

6327 - 33

1. !ower consumption in circuits

2. .lip lops) Latches design

3. high capacitance nodes

4. low power digital cells lirar"

,. Logic level: ate reorgani(ation-

. state machineencoding- pre5computation logic

. state machineencoding- pre5computation logic

6. state machineencoding- pre5computation logic

6. Low power Architecture & Systems

7"3! - 3

1. !ower ) performance management

2. !ower ) performance management

3. switching acti&it" reduction

4. parallel architecture with &oltage reduction

,. flow graph transformation

. low power arithmetic components- low power memor"

design.

7.Low power Cloc Distribution: ##

8/12/2019 Lesson Plan LPV

2/2

!0 - !6

1. !ower dissipation in cloc+ distriution

2. !ower dissipation in cloc+ distriution

3. single dri&er Vs distriuted uffers

4. single dri&er Vs distriuted uffers

,. 7ero s+ew Vs tolerale s+ew-

. chip )pac+age co design of cloc+ networ+

. chip )pac+age co design of cloc+ networ+

#. Algorithm & Architectural Level !etho"ologies

100!7 - "2

1. Introduction2. designflow

3. 8lgorithmic le&el anal"sis ) optimi(ation-

4. 8lgorithmic le&el anal"sis ) optimi(ation-

,. 8rchitectural le&elestimation ) s"nthesis

. 8rchitectural le&elestimation ) s"nthesis

. 8rchitectural le&elestimation ) s"nthesis

'e*t 9oo+s/

#$:aushi+ 0o"- Sharat !rasad- ;Low%Power C!S 'LSI Circuit Design< =ile"- 2>>>

2.ar" :. ?eap- ;Practical Low Power Digital 'LSI Design>23.0aae"- !edram- ;Low Power Design !etho"ologies< :luwer 8cademic- 1@@