Lect2 up270 (100328)

Lecture 270 – High Speed Op Amps (3/28/10) Page 270-1

CMOS Analog Circuit Design © P.E. Allen - 2010

LECTURE 270 – HIGH SPEED OP AMPSLECTURE ORGANIZATION

Outline• Extending the GB of conventional op amps• Cascade Amplifiers

- Voltage amplifiers- Voltage amplifiers using current feedback

• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 368-384



INCREASING THE GB OF OP AMPSWhat is the Influence of GB on the Frequency Response?The unity-gainbandwidth represents a limit in the trade-off between closed loop voltagegain and the closed-loop -3dB frequency.Example of a gain of -10 voltage amplifier:

0dB

20dB

|Avd(0)| dB

Magnitude

log10(ω)GBωA ω-3dB

Op amp frequency response

Amplifier with a gain of -10

Fig. 7.2-1

What defines the GB?We know that

GB = gmC

where gm is the transconductance that converts the input voltage to current and C is thecapacitor that causes the dominant pole.This relationship assumes that all higher-order poles are greater than GB.



What is the Limit of GB?The following illustrates whathappens when the next higher pole isnot greater than GB:

For a two-stage op amp, the polesand zeros are:

1.) Dominant pole p1 = -gm1

Av(0)Cc

2.) Output pole p2 = -gm6

CL

3.) Mirror pole p3 = -gm3

Cgs3+Cgs4 and z3 = 2p3

4.) Nulling pole p4 = -1

RzCI

5.) Nulling zero z1 = -1

RzCc-(Cc/gm6)

0dB

20dB

|Avd(0)| dB

Magnitude

log10(ω)GBωA ω-3dB

Op amp frequency response

Amplifier with a gain of -10

Fig. 7.2-2

Next higher pole-40dB/dec



Higher-Order PolesFor reasonable phase margin, the smallest higher-order pole should be 2-3 times largerthan GB if all other higher-order poles are larger than 10GB.

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-GB-10GB

Dominantpole

Smallest non-dominant pole

Larger non-dominant poles

GB

10GB0dB

Av(0) dB

GBAv(0)

log10ω

If the higher-order poles are not greater than 10GB, then the distance from GB to thesmallest non-dominant pole should be increased for reasonable phase margin.



Increasing the GB of a Two-Stage Op Amp1.) Use the nulling zero to cancel the closest pole beyond the dominant pole.2.) The maximum GB would be equal to the magnitude of the second closest pole beyond

the dominant pole.3.) Adjust the dominant pole so that 2.2GB (second closest pole beyond the dominant

pole)Illustration which assumes that p2 is the next closest pole beyond the dominant pole:

0dB

|Avd(0)| dB

Magnitude

log10(ω)

Fig. 7.2-3

-40dB/dec

-p1-p2 = z1-p4-p3

|p1| |p2|

|p4||p3|

-60dB/dec-80dB/dec

Before cancellingp2 by z1 and increasing p1

jωσ

|p1|

GB

-p1New Old

GBIncrease

OldGBNew

Old New



Example 270-1 - Increasing the GB of the Op Amp Designed in Ex. 230-1Use the two-stage op amp designed

in Example 230-1 and apply the aboveapproach to increase the gainbandwidthas much as possible. Use the capacitorvalues in the table shown along with Cox= 6fF/μm2.Solution1.) First find the values of p2, p3, and p4.

a.) From Ex. 230-2, we see thatp2 = -95x106 rads/sec.

b.) p3 was found in Ex. 6.3-1 asp3 = -1.25x109 rads/sec. (alsothere is a zero at -2.5x109

rads/sec.)

-

+vin

M1 M2

M3 M4

M5

M6

M7

vout

VDD = 2.5V

VSS = -2.5V

Cc = 3pF

CL =10pF

3μm1μm

3μm1μm

15μm1μm

15μm1μm

M84.5μm1μm

30μA

4.5μm1μm

14μm1μm

94μm1μm

30μA

95μA

Fig. 7.2-3A

Rz

Type P-Channel N-Channel UnitsCGSO 220 10-12 220 10-12 F/mCGDO 220 10-12 220 10-12 F/mCGBO 700 10-12 700 10-12 F/mCJ 560 10-6 770 10-6 F/m2CJSW 350 10-12 380 10-12 F/mMJ 0.5 0.5MJSW 0.35 0.38



Example 270-1 - Continued(c.) To find p4, we must find CI which is the output capacitance of the first stage of theop amp. CI consists of the following capacitors,

CI = Cbd2 + Cbd4 + Cgs6 + Cgd2 + Cgd4

For Cbd2 the width is 1.5μm L1+L2+L3=3μm AS/AD=4.5μm2 and PS/PD=9μm.For Cbd4 the width is 15μm L1+L2+L3=3μm AS/AD=45μm2 and PS/PD=36μm.From Table 3.2-1:

Cbd2 = (4.5μm2)(770x10-6F/m2) + (9μm)(380x10-12F/m) = 3.47fF+3.42fF 6.89fF

Cbd4 = (45μm2)(560x10-6F/m2) + (36μm)(350x10-12F/m) = 25.2fF+12.6F 37.8fF

Cgs6 in saturation is,

Cgs6=CGDO·W6+0.67(CoxW 6L6)=(220x10-12)(85x10-6)+(0.67)(6x10-15)(42.5) = 18.7fF + 255fF = 273.7fF

Cgd2 = 220x10-12x1.5μm = 0.33fF and Cgd4 = 220x10-12x15μm = 3.3fF

Therefore, CI = 6.9fF + 37.8fF + 273.7fF + 0.33fF + 3.3fF = 322fF. Although Cbd2 andCbd4 will be reduced with a reverse bias, let us use these values to provide a margin.Thus let CI be 322fF.

In Ex. 230-2, Rz was 4.564k which gives p4 = - 0.680x109 rads/sec.



Example 270-1 - ContinuedTherefore, the roots are:

jω

σ x 109

-1-2-3

z3 = -2.5G p3 = -1.25G p4 = -0.68G

p2 = -0.095G New GB

070503-01

When p2 is cancelled, the next smaller pole is p4 which will define the new GB. 2.)Using the nulling zero, z1, to cancel p2, gives p4 as the next smallest pole.For 60° phase margin GB = |p4|/2.2 if the next smallest pole is more than 10GB.

GB = 0.680x109/2.2 = 0.309x109 rads/sec. or 49.2MHz.This value of GB is designed from the relationship that GB = gm1/Cc. Assuming gm1 is

constant, then Cc = gm1/GB = (94.25x10-6)/(0.309x109) = 307fF. It might be useful toincrease gm1 in order to keep Cc above the surrounding parasitic capacitors (Cgd6 =18.7fF). The success of this method assumes that there are no other roots with amagnitude smaller than 10GB.

The result of this example is to increase the GB from 5MHz to 49MHz.



Example 270-2 - Increasing the GB of the Folded Cascode Op Amp of Ex. 240-4Use the folded-cascode op amp designed in

Example 240-4 and apply the above approach toincrease the gainbandwidth as much as possible.Assume that the drain/source areas are equal to2μm times the width of the transistor and that allvoltage dependent capacitors are at zero voltage.Solution

The poles of the folded cascode op amp are:

pA -1

RACA (the pole at the source of M6 )

pB -1

RBCB (the pole at the source of M7)

p6 -gm10

C6 (the pole at the drain of M6)

p8 -gm8rds8gm10

C8 (the pole at the source of M8)

p9 -gm9C9 (the pole at the source of M9)

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VPB1

M4 M5

RAI6

VPB2 RB

I4 I5

VDD

I7M6 M7

VNB2

M8 M9

M10 M11

+−

vIN

vOU

VNB1

I1 I2

M1 M2

M3I3

CL



Example 270-2 - ContinuedLet us evaluate each of these poles.1.) For pA, the resistance RA is approximately equal to gm6 and CA is given as

CA = Cgs6 + Cbd1 + Cgd1 + Cbd4 + Cbs6 + Cgd4From Ex. 240-4, gm6 = 774.6μS and capacitors giving CA are found as,

Cgs6 = (220x10-12·80x10-6) + (0.67)(80μm·0.5μm·6fF/μm2) = 177.6fF

Cbd1 = (770x10-6)(16.5x10-6·2x10-6) + (380x10-12)(37x10-6) = 39.5fF

Cgd1 = (220x10-12·16.5x10-6) = 3.6fF

Cbd4 = Cbs6 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fFand

Cgd4 = (220x10-12)(80x10-6) = 17.6fFTherefore,

CA = 177.6fF + 39.5fF + 3.6fF + 147fF + 17.6fF + 147fF = 0.532pFThus,

pA = -774.6x10-6

0.532x10-12 = -1.456x109 rads/sec.

2.) For the pole, pB, the capacitance connected to this node isCB = Cgd2 + Cbd2 + Cgs7 + Cgd5 + Cbd5 + Cbs7



Example 270-2 - ContinuedThe various capacitors above are found as

Cgd2 = (220x10-12·16.5x10-6) = 3.6fFCbd2 = (770x10-6)(16.5x10-6·2x10-6) + (380x10-12)(37x10-6) = 39.5fF

Cgs7 = (220x10-12·80x10-6) + (0.67)(80μm·0.5μm·6fF/μm2) = 177.6fFCgd5 = (220x10-12)(80x10-6) = 17.6fF

andCbd5 = Cbs7 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fF

The value of CB is the same as CA and gm6 is assumed to be the same as gm7 giving pB =pA = -1.456x109 rads/sec.3.) For the pole, p6, the capacitance connected to this node is

C6= Cbd6 + Cgd6 + Cgs10 + Cgs11+ Cbd8 + Cgd8

The various capacitors above are found asCbd6 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fFCgs10 = Cgs11 = (220x10-12·10x10-6) + (0.67)(10μm·0.5μm·6fF/μm2) = 22.2fFCbd8 = (770x10-6)(10x10-6·2x10-6) + (380x10-12)(2·12x10-6) = 24.5fFCgd8 = (220x10-12)(10x10-6) = 2.2fF and Cgd6 = Cgd5 =17.6fF

Therefore,C6 = 147fF + 17.6fF + 22.2fF + 22.2fF + 2.2fF + 17.6fF = 0.229pF



Example 270-2 - ContinuedFrom Ex. 240-4, gm6 = 774.6x10-6. Therefore, p6, can be expressed as

-p6 = 774.6x10-6

0.229x10-12 = 3.38x109 rads/sec.

4.) Next, we consider the pole, p8. The capacitance connected to this node isC8= Cbd10 + Cgd10 + Cgs8 + Cbs8

These capacitors are given as,Cbs8 = Cbd10 = (770x10-6)(10x10-6·2x10-6) + (380x10-12)(2·12x10-6) = 24.5fF

Cgs8 = (220x10-12·10x10-6) + (0.67)(10μm·0.5μm·6fF//μm2) = 22.2fFand

Cgd10 = (220x10-12)(10x10-6) = 2.2fFThe capacitance C8 is equal to

C8 = 24.5fF + 2.2fF + 22.2fF + 24.5fF = 73.4FFUsing the values of Ex. 240-4 of 600μS, the pole p8 is found as,

-p8 = gm8rds8 gm10/C8 = -600μS·600μS·/4.5μS·73.4fF = -1090x109 rads/sec.

5.) The capacitance for the pole at p9 is identical with C8. Therefore, since gm9 is600μS, the pole p9 is -p9 = 8.17x109 rads/sec.



Example 270-2 - ContinuedThe poles are summarized below:

pA = -1.456x109 rads/sec pB = -1.456x109 rads/sec p6 = -3.38x109 rads/sec

p8 = -1090x109 rads/sec p9 = -8.17x109 rads/secjω

σ x 109-1 -2 -3

p9 = -8.17G p6 = -3.38GpA = pB

= -1.456G New GB = 0.2x109

070503-02 -4 -5 -6 -7 -8

p8 = -1090G

The smallest of these poles is pA or pB. Since p6 is not much larger than pA or pB, wewill find the new GB by dividing pA or pB by 4 (which is guess rather than 2.2) to get364x106 rads/sec. Thus the new GB will be 364/2 or 58MHz.Checking our guess gives a phase margin of,

PM = 90° - 2tan-1(0.364/1.456) - tan-1(0.364/3.38) = 56° which is okayThe magnitude of the dominant pole is given as

pdominant = GB/Avd(0) = 364x106/3,678 = 99,000 rads/sec.

The value of load capacitor that will give this pole isCL = (pdominant·Rout)-1 = (99x103·7.44M )-1 = 1.36pF

Therefore, the new GB = 58MHz compared with the old GB = 10MHz.



Elimination of Higher-Order PolesThe minimum circuitry for a cascode op amp is shown below:

060710-01

vin + VNB1

vin + VPB1

VNB2

VPB2

VDD

M1

M2

M3

M4

vout

CL

Dominant Pole

Non-dominant

Pole

Non-dominant

Pole

If the source-drain area between M1 and M2 and M3 and M4 can be minimized, the non-dominant poles will be quite large.



Dynamically Biased, Push-Pull, Cascode Op Amp

M1

M2

M3

M4

M6

M7

vout

VDD

VSS

C1

M5

M8

C2

vin+IB

φ1

φ1

φ1 φ2

φ2

φ2

vin-

+-VB2

+-VB1

Fig.7.2-5

Push-pull, cascode amplifier: M1-M2 and M3-M4Bias circuitry: M5-M6-C2 and M7-M8-C1



Dynamically Biased, Push-Pull, Cascode Op Amp - ContinuedOperation:

M6

M7

VDD

VSS

C1

M5

M8

C2

vin+IB

+-VB2

+-VB1

+

-VDD-VB2-vin+

+

-vin+-VSS-VB1

M1

M2

M3

M4

vout

VDD

VSS

C1

C2

vin-

+

-VDD-VB2-vin+

+

-vin+-VSS-VB1

VDD-VB2-(vin+-vin-)

VSS+VB1-(vin+-vin-)

Equivalent circuit during the φ1 clock period Equivalent circuit during the φ2 clock period.Fig. 7.2-6



Dynamically Biased, Push-Pull, Cascode Op Amp - ContinuedThis circuit will operate on both clock phases† .

† S. Masuda, et. al., “CMOS Sampled Differential Push-Pull Cascode Op Amp,” Proc. of 1984 International Symposium on Circuits and Systems,

Montreal, Canada, May 1984, pp. 1211-12-14.

M1

M2

M3

M4

M6

M7

vout

VDD

VSS

C1

M5

M8

C2

vin+IB φ2

φ1

φ1

φ1vin-

+

-VB2

+

-VB1

Fig. 7.2-7

C4

C3

φ2

φ2

φ2 φ1

φ1 φ2

φ2 φ1

Performance (1.5μm CMOS):• 1.6mW dissipation• GB 130MHz (CL=2.2pF)• Settling time of 10ns (CL=10pF)

This amplifier was used with a28.6MHz clock to realize a 5th-orderswitched capacitor filter having acutoff frequency of 3.5MHz.



CASCADED AMPLIFIERS USING VOLTAGE AMPLIFIERSBandwidth of Cascaded AmplifiersCascading of low-gain, wide-bandwidth amplifiers:

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Ao s/ω1+1

Vin Vout

Ao s/ω1+1

Ao s/ω1+1

A1 A2 An

Ao s/ω1+1

n

Overall gain is Aon

-3dB frequency is,

-3dB = 1 21/n-1

If Ao = 10, 1 = 300 x106 rads/sec. and n = 3, then

Overall gain is 60dB and -3dB = 0.51 1 = 480x106 rads/sec. 76.5 MHz



Voltage Amplifier Suitable for Cascading

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VDD

Vout +−

Vin+

−

Μ1 Μ2Μ3 Μ4Μ5

VNB1

VPB1 VPB1

Μ6

Μ7

I7

I3 I4I5 I6

I1 I2

Voltage Gain:

VoutVin

= gm1gm3 =

Kn'(W1/L1)(I3+I5)Kp' (W3/L3)I3

-3dB gm3Cgs1



Ex. 270-3 - Design of a Voltage Amplifier for CascadingDesign the previous voltage amplifier for a gain of Ao = 10 and a power dissipation of nomore than 1mW. The design should permit Ao to be well defined. What is the -3dB forthis amplifier and what would be the -3dB for a cascade of three identical amplifiers?

SolutionTo enhance the accuracy of the gain, we replace M3and M4 with NMOS transistors to avoid thevariation of the transconductance parameter. Thisassumes a p-well technology to avoid bulk effects.The gain of 10 requires,

W1L1 (I3+I5) = 100

W3L3 I3

If VDD = 2.5V, then 2(I3+I5)·2.5V = 1000μW.

Therefore, I3+I5 = 200μA. Let I3 = 20μA and W1/L1 = 10W3/L3.

Choose W1/L1 = 5μm/0.5μm which gives W3/L3 = 0.5μm/0.5μm. M5 and M6 aredesigned to give I5 = 180μA and M7 is designed to give I7 = 400μA.

The dominant pole is gm3/Cout.

060711-01

VDD

Vout +−

Vin+

−

Μ1 Μ2Μ3 Μ4Μ5

VNB1

VPB1 VPB1

Μ6

Μ7

I7

I3 I4I5 I6

I1 I2



Ex. 270-3 – ContinuedCout = Cgs3+Cbs3+Cbd1+Cbd5+Cgd1+Cgd5+Cgs1(next stage) Cgs3 + Cgs1

Using Cox = 60.6x10-4 F/m2, we get,

Cout (2.5+0.25)x10-12 m2x 60.6x10-4 F/m2 = 16.7fF Cout 20fF

gm3 = 2·120·1·20 μS = 69.3μS

Dominant pole 69.3μS/20fF = 34.65x108 rads/sec. f-3dB = 551MHz

The bandwidth of three identical cascaded amplifiers giving a low-frequency gain of60dB would have a f-3dB of

f-3dB(Overall) = f-3dB 21/3-1 = 551MHz (0.5098) = 281MHz.

Pdiss = 3mW

060711-02

log10(f)

dB

60

40

20

0

-60dB/dec.

-40dB/dec.

-20dB/dec.

551MHz

281MHz

3 cascaded stages

2 cascaded stages

Single stage



A 71 MHz CMOS Programmable Gain Amplifier†

Uses 3 ac-coupled stages.First stage (0-20dB, common gate for impedance matching and NF):

vout

VDD

vout

CMFB

VBP

VBN

0dB2dB

VB1

vin

VB1

vin

0dB 2dB

M2dB M0dB M2dBM0dB

M2 M2

M3

Fig. 7.2-137A

Rin = 330 to match source driving requirement

All current sinks are identical for the differential switches.Dominant pole at 150MHz.

† P. Orsatti, F. Piazza, and Q. Huang, “A 71 MHz CMOS IF-Basdband Strip for GSM, IEEE JSSC, vol. 35, No. 1, Jan. 2000, pp. 104-108.



A 71 MHz PGA – ContinuedSecond stage (-10dB to 20dB):

M2 M2

M3

M2 M2

M3

CMFB

-10dB

-10dB

vout vout

VBP

VBN

vin vin

Fig. 7.2-137A

M5

M4

M6

M2dB M0dB

0dBLoad -10dB

Load

M5

M4

M6

M2dBM0dB

0dB 2dB0dB2dB

VDD

Dominant pole is also at 150MHzFor VDD = 2.5V, at 60dB gain, the total current is 2.6mA

IIP3 +1dBm



CASCADED AMPLIFIERS USING CURRENT FEEDBACK AMPLIFIERSAdvantages of Using Current FeedbackWhy current feedback?• Higher GB• Less voltage swing more dynamic rangeWhat is a current amplifier?

Requirements:io = Ai(i1-i2)

Ri1 = Ri2 = 0

Ro =

Ideal source and load requirements:Rsource =

RLoad = 0

Ri2

i1

i2io

+

-

CurrentAmplifier

Ri1

Ro

Fig. 7.2-8A



Bandwidth Advantage of a Current Feedback AmplifierConsider the inverting voltage amplifiershown using a current amplifier withnegative current feedback:

The output current, io, of the currentamplifier can be written as

io = Ai(s)(i1-i2) = -Ai(s)(iin + io)The closed-loop current gain, io/iin, can befound as

ioiin =

-Ai(s)1+Ai(s)

However, vout = ioR2 and vin = iinR1. Solving for the voltage gain, vout/vin gives

voutvin =

ioR2iinR1 =

-R2R1

Ai(s)1+Ai(s)

If Ai(s) = Ao

(s/ A) + 1 , then

vinvout

+- +

-i1

i2 io

io

vout

CurrentAmplifier

R1R2iin

VoltageBufferFig. 7.2-9

voutvin =

-R2R1

Ao1+Ao

A(1+Ao)s + A(1+Ao) Av(0) =

-R2AoR1(1+Ao) and -3dB = A(1+Ao)



Bandwidth Advantage of a Current Feedback Amplifier - ContinuedThe unity-gainbandwidth is,

GB = |Av(0)| -3dB = R2Ao

R1(1+Ao) · A(1+Ao) = R2

R1 Ao· A =

R2

R1 GBi

where GBi is the unity-gainbandwidth of the current amplifier.

Note that if GBi is constant, then increasing R2/R1 (the voltage gain) increases GB.

Illustration:

Ao dB

ωA

R2R1

>1

R2R1

GB1 GB2

Current Amplifier

0dB

Voltage Amplifier,

log10(ω)

Magnitude dB

Fig. 7.2-10

(1+Ao)ωA

GBi

= K

R1Voltage Amplifier, > KR2

1+AoAo dB

1+AoAo dBK

Note that GB2 > GB1 > GBi

The above illustration assumes that the GB of the voltage amplifier realizing the voltagebuffer is greater than the GB achieved from the above method.



Current Feedback AmplifierIn a current mirror implementation of the current amplifier, it is difficult to make the inputresistance sufficiently small compared to R1.

This problem can be solved using a transconductance input stage shown in the followingblock diagram:

060711-04

GMAi

RF

VinVout

+

−

VoutVin =

-GMRFAi1 +Ai



Differential Implementation of the Current Feedback AmplifierVDD

060712-01

Rin

RF RF+ −Vout

VPB1

VPB2

VNB2

M1 M2

1:n 1:n

Vin+ Vin

-

Iin = gm1

1+ 0.5gm1Rin

Vin+- Vin

-

2 and Vout = n (2RF)

1+n Iin

VoutVin

2nRFRin



A 20dB Voltage Amplifier using a Current AmplifierThe following circuit is a programmable voltage amplifier with up to 20dB gain:

M1

VDD

VSS

R1

+1 +1

VBias

+ -vout

vin+ vin-

M2

x2= 1/4

x4=1/8

x2= 1/4

x4=1/8

x1=1/2

x1=1/2

R2 R2

Fig. 7.2-135A

R1 and the current mirrors are used for gain variation while R2 is fixed.



Programmability of the Previous StageInput OTA:

Changes GM in 6dB steps.



Programmability of the Voltage Stage – Cont’dCurrent Amplifier:

Changes RF in 2dB steps

(RF20dB = 2.1k , RF18dB = 1.6k , RF16dB = 1.3k , and RF14dB = 5k .)

RFTotal = 10k .



Frequency Response of the Current Feedback PGA Stage0.5pF load:



Frequency Response of the Entire 60dB PGAIncludes output buffer:



SUMMARY• Increasing the GB of an op amp requires that the magnitude of all non-dominant poles

are much greater than GB from the origin of the complex frequency plane• The practical limit of GB for an op amp is approximately 5-10 times less than the

magnitude of the smallest non-dominant pole ( 100MHz)• To achieve high values of GB it is necessary to eliminate the non-dominant poles

(which come from parasitics) or increase the magnitude of the non-dominant poles• The best way to achieve high-bandwidth amplifiers is to cascade high-bandwidth

voltage amplifiers• If the gain of the high-bandwidth voltage amplifiers is well defined, then it is not

necessary to use negative feedback around the amplifier• Amplifiers with well defined gains are obtainable with a -3dB bandwidth of 100MHz

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Lect2 up270 (100328)