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Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 040 - ULTRA-DEEP SUBMICRON AND BiCMOSTECHNOLOGIES
LECTURE ORGANIZATIONOutline• Ultra-deep submicron CMOS technology
- Features- Advantages- Problems
• BiCMOS technology process flow- CMOS is typical submicron (0.5 μm)
• SummaryCMOS Analog Circuit Design, 2nd Edition ReferenceNew material
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-2
CMOS Analog Circuit Design © P.E. Allen - 2010
ULTRA-DEEP SUBMICRON (UDSM) CMOS TECHNOLOGYUSDM Technology• Lmin 0.1 microns
• Minimum feature size less than 100 nanometers• Today’s state of the art:
- 65 nm drawn length- 15 nm lateral diffusion (35 nm gate length)- 1.2 nm transistor gate oxide- 8 layers of copper interconnect
• Specialized processing is used to increase drive capability and maintain low offcurrents
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-3
CMOS Analog Circuit Design © P.E. Allen - 2010
65 Nanometer CMOS TechnologyTEM cross-section of a 35 nm NMOS and PMOS transistors.†
NMOS: PMOS:
These transistors utilize enhanced channel strains to increase drive capability and toreduce off currents.
† P. Bai, et. Al., “A 65nm Lobic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57
μm2 SRAM Cell, IEEE Inter. Electron Device Meeting, Dec. 12-15, 2005.
NMOS
220 nm pitch
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-4
CMOS Analog Circuit Design © P.E. Allen - 2010
UDSM Metal and InterconnectsPhysical aspects:
Layer Pitch(nm)
Thickness(nm)
AspectRatio
Isolation 220 230 -Polysilicon 220 90 -Contacted Gate Pitch 220 - -Metal 1 210 170 1.6Metal 2 210 190 1.8Metal 3 220 200 1.8Metal 4 280 250 1.8Metal 5 330 300 1.8Metal 6 480 430 1.8Metal 7 720 650 1.8Metal 8 1080 975 1.8
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-5
CMOS Analog Circuit Design © P.E. Allen - 2010
What are the Advantages of UDSM CMOS Technology?Digital Viewpoint:• Improved Ion/Ioff 70 Mbit SRAM chip:
• Reduced gate capacitance• Higher drive current capability• Reduced interconnect density• Reduction of active powerAnalog Viewpoint:• More levels of metal• Higher fT• Higher capacitance density• Reduced junction capacitance per gm
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-6
CMOS Analog Circuit Design © P.E. Allen - 2010
What are the Disadvantages of UDSM CMOS Technology (for Analog)?• Reduction in power supply resulting in reduced headroom• Gate leakage currents• Reduced small-signal intrinsic gains• Increased nonlinearity (IIP3)• Noise and matching??Intrinsic gain and IP3 as a function of the gate overdrive for decreasing VDS:†
† Anne-Johan Annema, et. Al., “Analog Circuits in Ultra-Deep-Submicron CMOS,” IEEE J. of Solid-State Circuits, Vol. 40, No. 1, Jan. 2005, pp. 132-
143.
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-7
CMOS Analog Circuit Design © P.E. Allen - 2010
What is the Gate Leakage Problem?Gate current occurs in thin oxide devices due to direct tunneling through the thin oxide.Gate current depends on:1.) The gate-source voltage (and the drain-gate voltage)
iGS = K1vGS exp(K2vGS) and iGD = K3vGD exp(K4vGD)
2.) Gate area – NMOS leakage 6nA/μm2 and PMOS leakage 3nA/μm2
Unfortunately, the gate leakage current is nonlinear with respect to the gate-source andgate-drain voltages. A possible model is:
051205-03
f(vGS)
f(vGD)+
−vGD
+
−vGS f(vDG)
f(vSG)+
−vSG
+
−vDG
NMOS PMOS
Large Signal Models
ggd
ggs
NMOS
gsg
gdg
PMOS
Small Signal Models
Base current cancellation schemes used for BJTs are difficult to apply to the MOSFET.
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Gate Leakage and fgateThe gate leakage can be represented by a conductance, ggate, in parallel with the
gate capacitance, Cgate. Since these two elements have identical area dependence, theyresult in a frequency, fgate, that is fairly independent of the drain-source voltage, vds.
fgate = ggate
2 Cgate
1.5·1016 vGS2etox(vGS-13.6) (NMOS)
0.5·1016 vGS2etox(vGS-13.6) (PMOS)
where tox is in nm and vGS is in V.
For frequencies above fgate theMOSFET looks capacitive and belowfgate, the MOSFET looks resistive (gateleakage).
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-9
CMOS Analog Circuit Design © P.E. Allen - 2010
UDSM CMOS Technology Summary• Increased transconductance and frequency capability• Low power supply voltages• Reduced parasitics• Gate leakage causes challenges for analog applications of UDSM technology
- Can no longer use the MOSFET for capacitance- Conflict between matching and gate leakage
• Other issues- Noise- Zero temperature coefficient behavior- Etc.
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-10
CMOS Analog Circuit Design © P.E. Allen - 2010
BiCMOS TECHNOLOGYTypical 0.5μm BiCMOS TechnologyMasking Sequence: 1. Buried n+ layer 9. Base oxide/implant 17. Contacts
2. Buried p+ layer 10. Emitter implant 18. Metal 1 3. Collector tub 11. Poly 1 19. Via 1 4. Active area 12. NMOS lightly doped drain 20. Metal 2 5. Collector sinker 13. PMOS lightly doped drain 21. Via 2 6. n-well 14. n+ source/drain 22. Metal 3 7. p-well 15. p+ source/drain 23. Nitride passivation 8. Emitter window 16. Silicide protectionNotation used in the following slides:
BSPG = Boron and Phosphorus doped Silicate Glass (oxide)Kooi Nitride = A thin layer of silicon nitride on the silicon surface as a result of thereaction of silicon with the HN3 generated, during the field oxidation.TEOS = Tetro-Ethyl-Ortho-Silicate. A chemical compound used to deposit conformaloxide films.
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-11
CMOS Analog Circuit Design © P.E. Allen - 2010
n+ and p+ Buried Layers
Starting Substrate:
p-substrate 1μm
5μmBiCMOS-01
n+ and p+ Buried Layers:
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-02
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Epitaxial Growth
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layerp+ buried layer
p-typeEpitaxialSilicon
p-well n-well p-well
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
n-well
BiCMOS-03
Comment:• As the epi layer grows vertically, it assumes the doping level of the substrate beneathit.• In addition, the high temperature of the epitaxial process causes the buried layers to
diffuse upward and downward.
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Collector Tub
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-welln-well
p-well
1μm
5μm
Collector Tub
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-04
Original Area of CollectorTub Implant
Comment:• The collector area is developed by an initial implant followed by a drive-in diffusion to
form the collector tub.
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Active Area Definition
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-welln-well
p-well
1μm
5μm
Collector Tub
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-05
Nitrideα-Silicon
Comment:• The silicon nitride is use to impede the growth of the thick oxide which allows contact
to the substrate• -silicon is used for stress relief and to minimize the bird’s beak encroachment
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Field Oxide
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
FOX
p-welln-well
p-well
1μm
5μm
Collector Tub
Field Oxide Field Oxide
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-06
FOX Field Oxide
Comments:• The field oxide is used to isolate surface structures (i.e. metal) from the substrate
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Collector Sink and n-Well and p-Well Definitions
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
Collector Tub
Field Oxide
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-07
FOX
Field Oxide
Collector Sink Anti-Punch ThroughThreshold Adjust
Anti-Punch ThroughThreshold Adjust
n-well
FOX Field Oxide
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Base Definition
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
FOX
p-well p-well
1μm
5μm
Collector Tub
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-08
Field Oxide Field Oxide
n-well
FOX Field Oxide
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Definition of the Emitter Window and Sub-Collector Implant
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-09
Field Oxide
n-well
Sub-Collector
FOX
Field Oxide
Sacrifical Oxide
FOX Field Oxide
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Emitter Implant
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
Collector Tub
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-10
Field Oxide
n-well
Sub-CollectorFO
X
Field Oxide
Emitter Implant
FOX Field Oxide
Comments:• The polysilicon above the base is implanted with n-type carriers
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Emitter Diffusion
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-11
Field Oxide
n-well
FOX
Field Oxide
Emitter
FOX Field Oxide
Comments:• The polysilicon not over the emitter window is removed and the n-type carriers diffuse
toward the base forming the emitter
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Formation of the MOS Gates and LD Drains/Sources
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-12
Field Oxide
n-well
FOX
Field OxideFOX Field Oxide
Comments:• The surface of the region where the MOSFETs are to be built is cleared and a thin gate
oxide is deposited with a polysilicon layer on top of the thin oxide• The polysilicon is removed over the source and drain areas• A light source/drain diffusion is done for the NMOS and PMOS (separately)
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Heavily Doped Source/Drain
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-13
Field Oxide
n-well
FOX
Field OxideFOX Field Oxide
Comments:• The sidewall spacers prevent the heavy source/drain doping from being near the
channel of the MOSFET
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Siliciding
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-14
Field Oxide
n-wellFO
X
Field Oxide
Silicide TiSi2 Silicide TiSi2 Silicide TiSi2
FOX Field Oxide
Comments:• Siliciding is used to reduce the resistance of the polysilicon and to provide ohmic
contacts to the base, emitter, collector, sources and drains
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Contacts
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μmBiCMOS-15
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
Tungsten Plugs Tungsten PlugsTungsten PlugsTEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
FOX
Comments:• A dielectric is deposited over the entire wafer• One of the purposes of the dielectric is to smooth out the surface• Tungsten plugs are used to make electrical contact between the transistors and metal1
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal1
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μmBiCMOS-16
Field Oxide Field Oxide
n-wellFO
X
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
Metal1 Metal1Metal1
FOX
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal1-Metal2 Vias
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μmBiCMOS-17
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
Tungsten Plugs Oxide/SOG/Oxide
FOX
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal2
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μmBiCMOS-18
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
Metal 2
FOX
Oxide/SOG/Oxide
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal2-Metal3 Vias
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μmBiCMOS-19
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
FOX
TEOS/BPSG/SOG
Oxide/SOG/Oxide
Comments:• The metal2-metal3 vias will be filled with metal3 as opposed to tungsten plugs
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Completed Wafer
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1μm
5μmBiCMOS-20
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
Nitride (Hermetically seals the wafer)
FOX
TEOS/BPSG/SOG
Metal3
Oxide/SOG/Oxide
Oxide/SOG/Oxide
Metal3Vias
Lecture 040 – UDSM and BiCMOS Technologies (3/24/10) Page 040-30
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• UDSM technology typically has a minimum channel length less than 0.1μm• UDSM transistors utilize enhanced channel strains to increase drive capability and
reduce off currents• Advantages of UDSM technology include:
- Smaller devices- Higher speeds and transconductances- Improved Ion/Ioff
• Disadvantages of UDSM technology include:- Gate leakage currents- Reduced small signal gains- Increased nonlinearity
• BiCMOS technology- Offers both CMOS transistors and a high performance vertical BJT- CMOS is typically a generation behind- Silicon germanium can be used to enhance the BJT performance