Last Copy to Print

8/13/2019 Last Copy to Print

1/82

1

SERIES AND SHUNT FEEDBACK AMPLIFIERS

(i) VOLTAGE SHUNT FEEDBACK AMPLIFIER

PIN CONFIGURATION: SYMBOL:

(i) CIRCUIT DIAGRAM OF VOLTAGE SHUNT FEEDBACK AMPLIFIER:


2/82

2

EX.NO: SERIES AND SHUNT FEEDBACK AMPLIFIERS

DATE:

AIM:

(i)To design and construct a Voltage Shunt feedback amplifier and to obtain its frequencyresponse curve with and without feedback.

(ii)To design and construct a Current Series feedback amplifier and to obtain its frequencyresponse curve with and without feedback.

(i) VOLTAGE SHUNT FEEDBACK AMPLIFIERAPPARATUS REQUIRED:

S.No Components Range Quantity

1. Transistor BC107 1

2. Resistor 600,4K,4.7K,10K 1

3. Function Generator - 1

4. Cathode Ray Oscilloscope - 1

5. DC regulated power supply (0-30)V 16. Probe - 2

7. Connecting wires - -

8. Bread Board - 1

DESIGN:

Given

oCL

o

LCoC

ffC

fCL

f

iCL

i

B

E

eefeie

BEfeieiC

EL

EECE

CCBBEEBCCCE

CC

EE

E

E

ECBEf

CLSfeLCCC

XfC

RRX

RXXf

CXf

C

RRR

I

mVrrhh

RRhhX

RfCRX

RR

RVVVVVVV

V

VI

V

R

IIVVKRKR

KRKRRhHzfmAIVV

2

1

10

//

10/,2

1,

2

1//

26,*

//1

2

10,10/

.,,2/

10,

,7.0,10,68

4,7.4,600,200,50,1,10

21

21

2

2


3/82

3

(ii) CURRENT SERIES FEEDBACK AMPLIFIERPIN CONFIGURATION: SYMBOL:

(ii) CIRCUIT DIAGRAM OF CURRENT SERIES FEEDBACK AMPLIFIER


4/82

4

(ii) CURRENT SERIES FEEDBACK AMPLIFIERAPPARATUS REQUIRED:



2. Resistor 600,4.7K,10K 1

3. Function Generator - 14. Cathode Ray Oscilloscope - 1

5. DC regulated power supply (0-30)V 1

6. Probe - 2


8. Bread Board - 1

DESIGN:

Given

iCL

iB

BEfeieiC

oCL

oLC

oC

CEL

EECE

CCB

BEEBEECCCECC

E

EEefeie

CCE

E

e

CCCE

ECBE

LSfeLCCC

XfCRRR

RRhhX

XfC

RRX

XfCRX

RR

RVV

VVVRIRIVV

I

VRrhh

VV

I

mVr

VVIIVVKR

KRRhHzfmAIVV

2

1,//

//1

2

1,

10

//

2

1,10/

.

,

,*

10,

26

2/,7.0,10

7.4,600,290,50,1,10

21

21

1

1


5/82

5

MODEL GRAPH:


6/82

6

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. Apply 10V dc supply to the collector and base of transistors.3. Set the Input voltage using Function generator and vary the frequency in desired

range.4. For each frequency note down the corresponding Output voltage values.5. Repeat the same procedure for with feedback amplifier circuit.

6. Graphs are plotted as gain versus frequency for the tabulated readings.


7/82

7

TABULATION:

(i) VOLTAGE SHUNT FEEDBACK AMPLIFIERVi = Volts

S.No.

With Feedback Without Feedback

Frequency

(Hz)

OutputVoltage

(Volts)

Gain =20log(Vo/Vi)(dB)

Frequency

(Hz)

OutputVoltage

(Volts)

Gain =20log(Vo/Vi)(dB)


8/82

8


9/82

9

(ii) CURRENT SERIES FEEDBACK AMPLIFIER

Vi = Volts

S.No.

With Feedback Without Feedback

Frequency

(Hz)

Output

Voltage

(Volts)

Gain =

20log(Vo/Vi)(dB) Frequency

(Hz)

Output

Voltage

(Volts)

Gain =

20log(Vo/Vi)(dB)


10/82

10

RESULT:

Thus voltage shunt and current series feedback amplifiers were designed and

constructed . Also their frequency response curves with and without feedback were obtained.

Bandwidth of voltage shunt feedback amplifier:

Without feedback:

With feedback :

Bandwidth of current series feedback amplifier:

Without feedback:

With feedback :

Preparation 25

Performance

& Result25

Total 50

Faculty signature


11/82

11

RC PHASE SHIFT AND WIEN BRIDGE OSCILLATORS

(i) RC PHASE SHIFT OSCILLATORPIN CONFIGURATION: SYMBOL:

CIRCUIT DIAGRAM OF RC PHASE SHIFT OSCILLATOR:


12/82

12

Ex. No: RC PHASE SHIFT AND WIEN BRIDGE OSCILLATORS

DATE:

AIM:

(i)To design and construct an RC phase shift oscillator circuit to generate a sine waveform.

(ii) To design and construct a Wien bridge oscillator circuit to generate a sine waveform.

(i) RC PHASE SHIFT OSCILLATORAPPARATUS REQUIRED:



2. Resistor 10K 3

3. Capacitor 10F47F

21



6. Probe - 2


8. Bread Board - 1

DESIGN:

)(462

1

10,

10

%10

2/

,

4,2,10,100,12

212

RRRCf

I

RIVVR

RI

VR

I

VR

I

VR

VofV

VVV

VV

IIII

I

KHzfmAIKRVVGiven

C

o

C

EECECCC

B

CC

B

B

E

EE

CCE

BEEB

CCCE

CBEC

B

oCCC


13/82

13

(ii) WIEN BRIDGE OSCILLATORCIRCUIT DIAGRAM OF WIEN BRIDGE OSCILLATOR:

MODEL GRAPH FOR RC PHASE SHIFT AND WIEN BRIDGE OSCILLATORS:


14/82

14

(ii) WIEN BRIDGE OSCILLATOR

APPARATUS REQUIRED:



2. Resistor 2.2K,47K,300K4.6K,41K,100K

1

2

3. Capacitor 1nF,10F

23



6. Probe - 2


8. Bread Board - 1

DESIGN:

RCfCCCRRRLet

nFCKHzf

2

1,,

1,15

2121

PROCEDURE:1. Connections are given as per the circuit diagram.

2. Switch on the dc power supply and apply 12V as bias voltage.

3. Sine wave output is obtained and the readings are tabulated.4. Graph is plotted by taking time period along X-axis and voltage along Y-axis.


15/82

15

TABULATION:

S.No Type Amplitude(Volts) Time period(ms)

Frequency f = 1/T (Hz)

TheoriticalValue

PracticalValue

1.RC phase shiftoscillator

2.Wien bridge

oscillator


16/82

16

RESULT:

Thus the RC Phase shift and Wein bridge oscillators were

designed and constructed . Also their output waveforms were plotted.

Frequency of Oscillation of RC Phase shift oscillator:

Theoritical Value :

Practical Value :

Bandwidth of Oscillation of Wein bridgeoscillator:

Theoritical Value :Practical Value :

\Preparation 25

Performance

& Result25

Total 50

Faculty signature


17/82

17

HARTLEY AND COLPITTS OSCILLATORS

(i) HARTLEY OSCILLATORPIN CONFIGURATION: SYMBOL:

CIRCUIT DIAGRAM OF HARTLEY OSCILLATOR:


18/82

18

Ex. No: HARTLEY AND COLPITTS OSCILLATORS

DATE:

AIM:

(i)To design and construct a Hartley oscillator circuit to generate a sine waveform.(ii) To design and construct a Colpitts oscillator circuit to generate a sine waveform.

(i) HARTLEY OSCILLATORAPPARATUS REQUIRED:



2. Resistor 390,270K 1

3. Capacitor 1nF,0.02F,0.1F,47F 1

4. Radio Frequency Choke 30mH 1



7. Probe - 2

8. Connecting wires - -9. Bread Board - 1

PROCEDURE:1. Connections are given as per the circuit diagram.2. Switch on the dc power supply and apply 10V as bias voltage.3. Sine wave output is obtained and the readings are tabulated.4. Graph is plotted by taking time period along X-axis and voltage along Y-axis.

DESIGN:

LCf 2

1

?2/

02.0

30

21

LLL

FC

KHzf

21 LLL


19/82

19

(ii) COLPITTS OSCILLATORPIN CONFIGURATION: SYMBOL:

CIRCUIT DIAGRAM OF COLPITTS OSCILLATOR:

MODEL GRAPH FOR HARTLEY AND COLPITTS OSCILLATORS:


20/82

20

(iii) COLPITTS OSCILLATORAPPARATUS REQUIRED:



2. Resistor 2.2K,100K47K

1

2

3. Capacitor 0.02F, 0.1F,0.2F,10F

12



6. Probe - 2


8. Bread Board - 1

DESIGN:

?,2

1

10,02.0,2.0

21

21

21

LCLC

CCf

KHzfFCFGivenC

r

r


21/82

21

TABULATION:

S.No Type Amplitude(Volts) Time period(ms)

Frequency f = 1/T (Hz)

Theoritical

Value

Practical

Value

1. Hartley Oscillator

2. Colpitts Oscillator


22/82

22

PROCEDURE:


2. Switch on the dc power supply and apply 12V as bias voltage.3. Sine wave output is obtained and the readings are tabulated.

4. Graph is plotted by taking time period along X-axis and voltage along Y-axis.

\

RESULT:

Thus the Hartley and Colpitts oscillators were designed and constructed . Also

their output waveforms were plotted.

Frequency of Oscillation of Hartley oscillator:

Theoritical Value :

Practical Value :

Bandwidth of Oscillation of Colpitts oscillator:

Theoritical Value :

Practical Value :

Preparation 25

Performance& Result

25

Total 50

Faculty signature


23/82

23

TUNED CLASS C AMPLIFIER


CIRCUIT DIAGRAM:

MODEL GRAPH:


24/82

24

EX.NO: TUNED CLASS C AMPLIFIER

DATE:

AIM:

To design and construct a tuned Class C amplifier circuit and to obtain its frequency

response.

APPARATUS REQUIRED:

S.No Components Range Quantity1. Transistor BC107 1

2. Capacitor 1nF,0.1F

220F

1

2




6. Probe - 2


8. Bread Board - 1

DESIGN:

Given

?,1

2

1

,

9,10

%10

,

2

7.0,1.0,220,80,100,10,1

1

1

2

2

21

LnFLetC

LCf

I

VVR

I

VR

IIII

IVR

VVV

VofV

IIII

I

VV

VVFCFCCKHzfVVmAI

r

BCCB

BB

E

EE

EBEB

CCE

CBE

C

B

CC

CE

BEoeirCCC


25/82

25

TABULATION:

Vi = Volts

S.No Frequency(Hz) Output Voltage(Volts) Gain = 20log(Vo/Vi) (dB)


26/82

26

PROCEDURE:

1. Connections are given as per the circuit diagram.2. Apply 10V dc supply to the collector and base of transistors.

3. Set the Input voltage using Function generator and vary the frequency in desired

range.4. For each frequency note down the corresponding Output voltage values.

5. Graphs are plotted as gain versus frequency for the tabulated readings.

RESULT:

Thus the tuned class C amplifier was designed and its frequency response was

obtained.

Bandwidth of tuned amplifier :

Resonant Frequency of tuned amplifier :

Preparation 25

Performance

& Result25

Total 50

Faculty signature


27/82

27

INTEGRATOR, DIFFERENTIATOR, CLIPPERS ANDCLAMPERS

(i) INTEGRATOR & DIFFERENTIATORPIN CONFIGURATION: SYMBOL:

CIRCUIT DIAGRAM OF INTEGRATOR AND DIFFERENTIATOR:


28/82

28

EX.NO: INTEGRATOR, DIFFERENTIATOR, CLIPPERS ANDDATE: CLAMPERS

AIM:(i) To design and construct differentiator and integrator circuits and to obtain their output

waveforms.

(ii) To construct biased positive and negative clipper circuits and to obtain their outputwaveforms.

(iii) To construct and test the clamper circuit.

(i) INTEGRATOR & DIFFERENTIATORAPPARATUS REQUIRED:


1. Capacitor 0.1F 1

2. Diode 1N4007 1


4. Cathode Ray Oscilloscope - 15. DC regulated power supply

6. Probe - 2


8. Bread Board - 1

DESIGN:

Given

FCLet

RCTKHzf

1.0

,,1


29/82

29

MODEL GRAPH:

INTEGRATOR

DIFFERENTIATOR


30/82

30

PROCEDURE:

1.Connections are given as per the circuit diagram.

2.Set the Input signal with the help of function generator.

3.Output is taken from CRO.4.Readings are noted and tabulated.

5.Graph is drawn for timeperiod versus amplitude.


31/82

31

(ii) CLIPPERCIRCUIT DIAGRAM OF CLIPPER::

MODEL GRAPH FOR CLIPPER:


32/82

32

(ii) CLIPPERAPPARATUS REQUIRED:


1. Diode 1N4007 1

2. Resistor 2.5K 1



6. Probe - 2


8. Bread Board - 1

PROCEDURE:


2.Set the Inputp signal with the help of function generator.

3.Output is taken from CRO.

4.Readings are noted and tabulated.5.Graph is drawn for timeperiod versus amplitude.


33/82

33

(iii) CLAMPERCIRCUIT DIAGRAM OF CLAMPER:

MODEL GRAPH FOR CLAMPER:

\


34/82

34

(iii) CLAMPERAPPARATUS REQUIRED:


1. Diode 1N4007 1

2. Resistor 10K 1

3. Capacitor 10F 14. Function Generator - 1



7. Probe - 2


Bread Board - 1

PROCEDURE:


2.Set the Input signal with the help of function generator.3.Output is taken from CRO.

4.Readings are noted and tabulated.

5.Graph is drawn for timeperiod versus amplitude.


35/82

35

TABULATION:

Amplitude(Volts)

Timeperiod(ms)

1.Differentiator

Without diode

With diode

2.Integrator

Without diode

With diode

3.Clipper

Positive Clipper

Negative Clipper

4.Clamper

Positive Clamper

Negative Clamper


36/82

36

RESULT:

Thus the following circuits were designed and constructed and their output

waveforms were also obtained.

i. Integrator and Differentiator

ii.Biased Positive and Negative Clipper circuits

iii. Clamper circuit

Preparation 25

Performance

& Result25

Total 50

Faculty signature


37/82

37

ASTABLE, MONOSTABLE AND BISTABLE MULTIVIBRATORS

(i) ASTABLE MULTIVIBRATOR


CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:


38/82

38

EX.NO: ASTABLE, MONOSTABLE AND BISTABLE MULTIVIBRATORS

DATE:

AIM:(i) To design and construct an astable multivibrator and to obtain its waveform.

(ii) To design and construct a monostable multivibrator with a pulse width of 0.1ms usingtransistor.

(iii) To design and construct a bistable multivibrator with a frequency of 2 KHz and to obtain

its performance curve.

(i) ASTABLE MULTIVIBRATORAPPARATUS REQUIRED:



2. Capacitor 1nF 2

3. Cathode Ray Oscilloscope - 14. DC regulated power supply (0-30)V 1

5. Probe - 2


7. Bread Board - 1

DESIGN:

Given

RCT

I

VR

CCCRRR

RRR

nFCKHzfmAIVV

C

CCC

CCC

CCC

38.1

1,3.1,5,10

21

21

21

PROCEDURE:


2. Apply 10V dc supply to the collector and base of transistors.3. Output is taken from collector and base of each transistor.

4. Readings are noted and tabulated.

5. Graph is drawn for timeperiod versus amplitude.


39/82

39

(ii) MONOSTABLE MULTIVIBRATOR



CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:


40/82

40

(ii) MONOSTABLE MULTIVIBRATOR

APPARATUS REQUIRED:


1. Transistor SL100 2

2. Diode 1N4007 1

3. Capacitor 1nF 1



7. Probe - 2


9. Bread Board - 1

DESIGN:

Given

?

1.0.69.0

?1

)/1(10/

?

.2/1

2

1,

1000

9

10

/)(,

/

/

2,2,2.1

100,7.0,3,3,2,12

2max

1

1

12

22

21

ma x

C

msasTTakeCRT

RnFCLet

fTTCR

C

CRWheref

fXC

RX

I

VVR

IVVVR

IVVVRh

II

IVVVR

IVR

RRRKHzfKHzfKR

hVVVVVVmAIVV

B

dd

dd

S

S

CC

C

i

CC

B

BEre

BreBECC

BBEreCCB

fe

C

B

CreCECCC

Eree

CCC

i

feBEreCECCC

PROCEDURE:


2. Apply 10V dc supply to the collector and base of transistors.3. Output is taken from collector and base of each transistor.

4. Readings are noted and tabulated.

5. Graph is drawn for timeperiod versus amplitude.


41/82

41

(iii) BISTABLE MULTIVIBRATOR


CIRCUIT DIAGRAM OF BISTABLE MULTIVIBRATOR:


42/82

42

iii) BISTABLE MULTIVIBRATOR

APPARATUS REQUIRED:


1. Transistor SL100 2

2. Diode 1N4007 3



6. Probe - 2


8. Bread Board - 1

DESIGN:

Given

?1

)2/(/1.

?//

2

1

9/

10/

/

/

2,3,180,2,12

max

21

max

2

1

ma x

d

d

BBEre

BBEreCC

CresatCECCC

C

ree

feCB

resatCEfeCCC

CMRLet

fffTLetTCR

CRRRWhereRC

f

IVVR

IVVVR

IVVVR

I

VR

hII

KHzfVVVhmAIVV

PROCEDURE:


2. Apply 12V dc supply to the collector and base of transistors.

3. Set the trigger I/P voltage using Function generator.

4. Output is taken from collector of each transistor.5. Readings are noted and tabulated.

6. Graph is drawn for time period versus amplitude.


43/82

43

ASTABLE MULTIVIBRATOR

MODEL GRAPH:

MONOSTABLE MULTIVIBRATOR

MODEL GRAPH:


44/82

44


45/82

45

BISTABLE MULTIVIBRATOR

MODEL GRAPH:

TABULATION:

Amplitude (Volts) Time period ( ms)

1.Astable

Multivibrator

Across C1

Across C2

Across B1

Across B2

2.MonostableMultivibrator

Trigger Input

Output

3.BistableMultivibrator

Trigger Input

Across C1

Across C2


46/82

46

RESULT:

Thus the following circuits were designed and constructed and their outputwaveforms were also obtained.

i. Astable multivibrator

ii.Monostable multivibrator

iii. Bistable multivibrator

Preparation 25

Performance& Result

25

Total 50

Faculty signature


47/82

47

SIMPLE SWEEP AND BOOTSTRAP SWEEP GENERATOR

SIMPLE SWEEP GENERATOR


CIRCUIT DIAGRAM OF SIMPLE SWEEP CIRCUIT:

OUTPUT OF SIMPLE SWEEP CIRCUIT:


48/82

48

Ex.No: SIMPLE SWEEP AND BOOTSTRAP SWEEP GENERATOR

DATE

AIM:-

To create a PSPICE model and to simulate a sweep circuit and bootstrap sweep generator

circuit

PROCEDURE:

1. Use PSPICE evaluation package and Vdc as input source.2. Select ProgramOrCAD 9.1Captureclick on filenewprojectclick to get

the component file.3. To draw the circuit we require transistors ( 2N2646 & BC107),Vdc , ground

terminals,resistors and external a.c input signal.

4. Select the parts one by one and place them in the work area.5. Arrange the parts and make connections using wire.6. The parts attributes are changed by giving double click on the labelthen enter the new

value.

7. Save the circuit as file.8. Click Pspice before which place the differential voltage marker at the o/p side and voltagemarker at the input side.

9. Click PspiceNew simulation profileopen analysissetup time domain analysischange Run to timegive O.K.

10.Open Pspicecreate Netlist to make sure that there are no wiring errors.11.If there is no error, then open Pspiceclick Runclick Plotadd plot to window

Cut and paste the waveforms.12.The same procedure is repeated for bootstrap sweep generator.


49/82

49

BOOTSTRAP SWEEP GENERATOR


CIRCUIT DIAGRAM OF BOOTSTRAP SWEEP GENERATOR:

OUTPUT OF BOOTSTRAP SWEEP GENERATOR:


50/82

50

RESULT:Thus the PSPICE model of sweep circuit and bootstrap sweep generator citcuits are

simulated.

Preparation 25

Performance

& Result25

Total 50

Faculty signature


51/82

51

SIMULATION OF DIFFERENTIAL AMPLIFIER

SYMBOL:

CIRCUIT DIAGRAM OF DIFFERENTIAL AMPLIFIER :


52/82

52

Ex.No: SIMULATION OF DIFFERENTIAL AMPLIFIER

DATE:

AIM:

To create a PSPICE model and to simulate a differential amplifier in both common and

differential modes.

SOFTWARE REQUIRED:OrCAD 9.1

DESIGN:Vcc=12v , IE=1mA , VEE= -12V

Assume Ad=150 , VBE= 0.7V

RE=[VEE -VBE)] / IE

re=26mV/IE

Ad=Rc/re; Rc=Adre


53/82

53

OUTPUT OF DIFFERENTIAL MODE:

OUTPUT OF COMMON MODE:


54/82

54

PROCEDURE:

1. Use PSPICE evaluation package and Vdc as input source.2. Select ProgramOrCAD 9.1Captureclick on filenewprojectclick to

get the component file.3. To draw the circuit we require transistors ( 2N2222),Vdc , ground terminals,resistors and

external a.c input signal.

4. Select the parts one by one and place them in the work area.5. Arrange the parts and make connections using wire.6. The parts attributes are changed by giving double click on the labelthen enter the

new value.

7. Save the circuit as file.8. Click Pspice before which place the differential voltage marker at the o/p side andvoltage marker at the input side.

9. Click PspiceNew simulation profileopen analysissetup time domain analysischange Run to timegive O.K.

10.Open Pspicecreate Netlist to make sure that there are no wiring errors.11.If there is no error, then open Pspiceclick Runclick Plotadd plot to windowCut and paste the waveforms.

12.The same procedure is repeated for differential mode of operation.

RESULT:Thus the PSPICE model of differential amplifier in both common and differential modes are

designed and simulated successfully.

Preparation 25

Performance

& Result25

Total 50

Faculty signature


55/82

55

SIMULATION OF BUTTERWORTH SECOND ORDER LOW PASS FILTER AND HIGH

PASS FILTER

SYMBOL: PIN DIAGRAM:

CIRCUIT DIAGRAM OF BUTTERWORTH SECOND ORDER LOW PASS FILTER:

CIRCUIT DIAGRAM OF BUTTERWORTH SECOND ORDER HIGH PASS FILTER:


56/82

56

EX.NO: SIMULATION OF BUTTERWORTH SECOND ORDER LOW

DATE: PASS FILTER AND HIGH PASS FILTER

AIM:

To create a PSPICE model and to simulate a second order Butterworth low pass and high

pass filter having upper cutoff frequency 1KHz and to determine its frequency response.

SOFTWARE REQUIRED:

OrCAD 9.1

DESIGN:

i

f

o

o

h

fh

R

RA

A

RCf

KRnforFCKHzf

1

3

2

1

86.5,2414.1,1.0,1


57/82

57

OUTPUT OF LOW PASS FILTER

OUTPUT OF HIGH PASS FILTER


58/82

58

PROCEDURE:

1. Use PSPICE evaluation package and Vdc as input source.2. Select ProgramOrCAD 9.1Captureclick to get the component file.3. To create the lowpass filter circuit we require Opamp(741),Vdc , ground

terminals,resistors,capacitors and external a.c input signal.4. Select the parts one by one and place them in the work area.5. Arrange the parts and make connections using wire.6. Save the circuit as file.7. Click Pspice before which place the voltage marker at the i/p and o/p sides.8. Click PspiceNew simulation profileopen analysissetup time domain analysis

change Run to timegive O.K.

9. Open Pspicecreate Netlist to make sure that there are no wiring errors.10.If there is no error, then open Pspiceclick Runclick Plotadd plot to window

Cut and paste the waveforms.

RESULT:

Thus the PSPICE model of a second order Butterworth low pass and high pass filter having

upper cutoff frequency 1KHz are designed ,simulated and its frequency response are showned

Preparation 25

Performance

& Result25

Total 50

Faculty signature


59/82

59

SIMULATIONS OF ASTABLE, MONOSTABLE AND BISTABLE

MULTIVIBRATORS

(1) ASTABLE MULTIVIBRATOR




60/82

60

EX.NO: SIMULATIONS OF ASTABLE, MONOSTABLE AND BISTABLE

DATE: MULTIVIBRATORS

AIM:

To create a PSPICE model and to simulate Astable, Monostable and Bistablemultivibrators.


PROCEDURE:

1. Use Pspice evaluation package and Vdc as input source.2. Select ProgramOrCAD 9.1Captureclick on filenewprojectclick to get

the component file.

3. To draw the circuit we require IC 555, Vdc,ground terminals, resistors, capacitors.4. Select the parts one by one and place them in the work area.5. Arrange the parts and make connections using wire.6. The parts attributes are changed by giving double click on the labelthen enter the new

value.7. Save the circuit as file.8. Click Pspice before which place the voltage marker at the input side and output side.9. Click PspiceNew simulation profileopen analysissetup time domain analysis


10.Open Pspicecreate Netlist to make sure that there are no wiring errors.11.If there is no error, then open Pspiceclick Runclick Plotadd plot to window

Cut and paste the waveforms.12.The same procedure is repeated for Monostable and Bistable multivibrator .


61/82

61

(2) MONOSTABLE MULTIVIBRATOR


(3) BISTABLE MULTIVIBRATORS

CIRCUIT DIAGRAM OF BISTABLE MULTIVIBRATOR


62/82

62


63/82

63

OUTPUTS OF ASTABLE MULTIVIBRATOR:

OUTPUT ACROSS C1 & C2:

OUTPUT ACROSS B1 & B2:


64/82

64


65/82

65

OUTPUT OF MONOSTABLE MULTIVIBRATOR:

OUTPUT OF BISTABLE MULTIVIBRATOR:


66/82

66

RESULT:

Thus the PSPICE model of Astable, Monostable and Bistable multivibrators were created and

simulated successfully.

Preparation 25

Performance& Result

25

Total 50

Faculty signature


67/82

67

SIMULATION OF CMOS INVERTER, NAND AND NOR GATES

(i) INVERTERCIRCUIT DIAGRAM OF CMOS INVERTER :

(ii) NAND

CIRCUIT DIAGRAM OF CMOS NAND GATE:


68/82

68

Ex.No: SIMULATION OF CMOS INVERTER, NAND AND NOR GATES

DATE:

AIM:

To create a PSPICE model and to simulate a CMOS inverter, NAND and NOR gates


PROCEDURE:

1. Use PSPICE evaluation package and Vdc as input source.2. Select ProgramOrCAD 9.1Captureclick to get the component file.3. To create CMOS inverter circuit we require NMOS, PMOS, Vdc,ground terminals andexternal a.c input signal.4. Select the parts one by one and place them in the work area.5. Arrange the parts and make connections using wire.6. Save the circuit as file.7. Click Pspice before which place the voltage marker at the i/p and o/p sides.8. Click PspiceNew simulation profileopen analysissetup time domain analysis

change Run to timegive O.K.9. Open Pspicecreate Netlist to make sure that there are no wiring errors.10.If there is no error, then open Pspiceclick Runclick Plotadd plot to window


11. The same procedure is repeated for simulation of CMOS NAND and NOR gates.


69/82

69

(iii) NOR

CIRCUIT DIAGRAM OF CMOS NOR GATE:

OUTPUT OF CMOS INVERTER


70/82

70


71/82

71

OUTPUT OF CMOS NAND

OUTPUT OF CMOS NOR


72/82

72

RESULT:

Thus the PSPICE model of CMOS inverter, NAND and NOR gates were created and

simulated successfully.

Preparation 25

Performance& Result

25

Total 50

Faculty signature


73/82

73

SIMULATION OF ANALOG MULTIPLIER

CIRCUIT DIAGRAM OF ANALOG MULTIPLIER:


74/82

74

Ex.No: SIMULATION OF ANALOG MULTIPLIER

DATE:

AIM:

To create a PSPICE model of analog multiplier and verify its output


PROCEDURE:

1. Use PSPICE evaluation package and Vdc as input source.2. Select ProgramOrCAD 9.1Captureclick to get the component file.3. Select the parts one by one and place them in the work area.4. Arrange the parts and make connections using wire.5. Save the circuit as file.6. Click Pspice before which place the voltage marker at the i/p and o/p sides.7. Click PspiceNew simulation profileopen analysissetup time domain analysis


8. Open Pspicecreate Netlist to make sure that there are no wiring errors.9. If there is no error, then open Pspiceclick Runclick Plotadd plot to window



75/82

75

OUTPUT OF ANALOG MULTIPLIER


76/82

76

RESULT:Thus the PSPICE model of analog multiplier circuit was created and simulated successfully.

Preparation 25

Performance

& Result25

Total 50

Faculty signature


77/82

77

SIMULATION OF D/A and A/D CONVERTERS (R-2R LADDER)

CIRCUIT DIAGRAM OF D/A and A/D CONVERTERS (R-2R LADDER):


78/82

78

Ex.No: SIMULATION OF D/A and A/D CONVERTERS (R-2R LADDER)

DATE:

AIM:

To create a PSPICE model of D/A and A/D Converters Using Successive approximation

method

SOFTWARE REQUIRED:

OrCAD 9.1

PROCEDURE:

1. Use PSPICE evaluation package and Vdc as input source.2. Select ProgramOrCAD 9.1Captureclick to get the component file.3. Select the parts one by one and place them in the work area.4. Arrange the parts and make connections using wire.5. Save the circuit as file.6. Click Pspice before which place the voltage marker at the i/p and o/p sides.7. Click PspiceNew simulation profileopen analysissetup time domain analysis


8. Open Pspicecreate Netlist to make sure that there are no wiring errors.9. If there is no error, then open Pspiceclick Runclick Plotadd plot to window



79/82

79

OUTPUT OF A/D CONVERTER


80/82

80

RESULT:

Thus the PSPICE model of D/A and A/D Converters Using R-2R ladder rmethod was createdand simulated successfully.

Preparation 25

Performance& Result

25

Total 50

Faculty signature


81/82

81

VIVA:1.State Barkhausen criterion.

2.What is the use of RFC?3.How do Hartley differ from Colpitts oscillator?

4.Give the frequency range of Hartley and Colpitts oscillator.

5.What is Class C operation?6.Define tank circuit.

7.Give some applications of tuned Class C amplifier.8.What is the difference b/w Class C and Class D operation?9. If the I/P to the differentiator is cosine wave what is the Output?

10. What do you mean by biased clipper?

11. What are the other names of clipper & clamper?12. If the I/P to the integrator is square wave what is the Output?

13. If the I/P to the integrator is step signal what is the Output?14.What is the difference b/w oscillator and multivibrator?

15. What do you mean by quasi stable state?16. What is the use of speed-up capacitor?

17. Give some applications of bistable multivibrator.

18.What is the difference b/w blocking oscillator and oscillator?19.Define CMRR.20.Give some applications of differential amplifier.

21.What are the ideal characteristics of differential amplifier.

22.Why do we call Wienbridge oscillator as lead-lag circuit oscillator?23.Why 3 RC networks in cascaded connection are in RC phase shift oscillator?

24.What are the advantages & disadvantages of RC phase shift oscillator?

25.What is Feedback?What are its types?26.Which type of Feedback is used in amplifiers?

27.Give any 4 merits of negative Feedback?

28.Define desensitivity.

29.What do you meant by Sampling and mixing in the context of Feedback amplifiers?30.What is the expansion of Pspice?

31.Differentiate active filter and passive filter.

32.Give the important features of IC 741.33.Define cut-off frequency and bandwidth.

34.What is the difference b/w oscillator and multivibrator?

35.Define pulse width.

36.What do you mean by quasi stable state?37. What is the use of speed-up capacitor?

38. Give some applications of bistable multivibrator.

39. Which type of feedback is used in multivibrators?

40. What is the difference b/w blocking oscillator and oscillator?41. Give some applications of astable multivibrator.

42. Give some triggering methods of monostable multivibrator.

43.If the Input to the differentiator is cosine wave what is the Output?44.What do you mean by biased clipper?

45.What are the other names of clipper & clamper.

46.If the Input to the integrator is square wave what is the Output?47. If the Input to the integrator is step signal what is the Output?


82/82

Documents

Last Copy to Print