Lab Manul of Vlsi

8/2/2019 Lab Manul of Vlsi

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CIT-CHANGA Electronics & Communication Department

PROGRAME 1

STATEMENT: To implement all logic gates using VHDL.

--To implement xnor gate

library ieee;entity xnor2 is port(a, b : in bit;

y : out bit);

end xnor2;

architecture rtl of xnor2 is

begin

y


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entity jnot is port (a, b : in bit;

y : out bit);

end jnot2;

architecture rtl of jnot2 isbeginy


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PROGRAME 2

STATEMENT: To implement all logic gates using eight select lines.

library ieee;

use ieee.std_logic_1164.all;

entity allgates is port(

a, b,clk: in std_logic;

sel: in std_logic_vector(2 downto 0);

y : out std_logic);end allgates;

architecture rtl of allgates isbegin

process(clk)begin

if rising_edge(clk) then

case sel iswhen "000" =>

y

y

y

yy

y

yy

null;

end case;

end if;end process;

end rtl;

VLSI TECHNOLOGY AND DESIGN


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PROGRAME 3

STATEMENT: To implement half adder using dataflow, behavior, and structural

Style of modeling using VHDL.

--half adder using dataflow style of modeling

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity had is

port(X,Y:in STD_LOGIC;S,C:out STD_LOGIC);end had;

architecture str of had is

beginS


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--half adder using structural style of modeling

--half adder using structural

library ieee;use ieee.std_logic_1164.all;

entity haddstr isport(a,b :in bit;sum,cary:out bit);

end haddstr;

architecture ha_structure of haddstr iscomponent xor_2

port(x,y:in bit; z:out bit);

end component;

component and_2

port(x1,y1:in bit; z1:out bit);end component;

beginp: xor_2 port map(a,b,sum);

q: and_2 port map(a,b,cary);

end ha_structure;

--now entity and architecture of xor gate.

entity xor_2 isport(x,y:in bit; z:out bit);

end xor_2;

architecture a of xor_2 is

begin

z


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PROGRAME 4

STATEMENT: To implement full adder using dataflow, structural and mixed style of

Modeling using VHDL.

--1 bit full adder using dataflow modeling

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity fda is

port(X,Y,Z:in STD_LOGIC;S,C:out STD_LOGIC);end fda;

architecture dataflow of fda isbegin

S


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p5:and_2 port map(a,cin,t3);p6:or_2 port map(t1,t2,v);

p7:or_2 port map(t3,v,cout);

end struct;

--entity and architecture of xor componententity xor_2 isport(x1,y1:in bit;z1:out bit);

end xor_2;

architecture dataflow of xor_2 isbegin

z1


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PROGRAME 5

STATEMENT: To implement 41 mux using VHDL.

library ieee;


entity mux1 is

port( d0,d1,d2,d3:in bit;s :in bit_vector(1 downto 0);

y:out bit);

end mux1;

architecture behave of mux1 isbegin

process(s)

begin

case s iswhen"00" => y y y y y


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PROGRAME 6

STATEMENT: To implement 81 mux using VHDL.

--one bit 8 to 1 mux with active low enable

library ieee;


entity mux8to1 is port (

i : in std_logic_vector(7 downto 0);

sel : in std_logic_vector(2 downto 0);

y : out std_logic;en : in bit);

end mux8to1;

architecture behavioral of mux8to1 isbegin

processbegin

if (en='1') then

case sel is

when "000" =>y

y

y

y y

y

y

y

y


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PROGRAME: 7

STATEMENT: To implement 3 to 8 decoder using VHDL.

--To implement 3 to 8 decoder.


entity decode is

port (Ain:in std_logic_vector(2 downto 0);

en: in std_logic;

Yout:out std_logic_vector(7 downto 0));

end decode;

architecture decode_arch of decode is

begin

process(Ain)begin

if en='0' then

Yout'0');

elsecase Ain is

when "000" => Yout Yout Yout Yout Yout Yout Yout YoutYout


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PROGRAME: 5

STATEMENT: To implement D,SR,JK and T flip flop using VHDL.

--implement D flip flop using VHDL.

library ieee;


entity dff isport (d,clk,clear,preset :in std_logic;

q, qbar :buffer std_logic);

end dff;

architecture behavioural of dff is

beginp:process (clear,preset,clk)

begin

if(clear = '1') thenq


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RS flip flop using VHDL.

--To implement RS flip flop


entity rsflf isport (r,s,clk,clear:in std_logic;

q,qbar:out std_logic);

end rsflf;

architecture behave of rsflf is

beginp:process(clear,clk)

variable qv:std_logic:='0';variable qbarv:std_logic:='1';

begin

if(clear='1') then

qv:='0';qbarv:='1';

VLSI TECHNOLOGY AND DESIGN


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elsif(rising_edge(clk))then

if(s='0' and r='0') then

qv:=qv;qbarv:=qbarv;

elsif(s='1' and r='0') thenqv:='1';qbarv:='0';

elsif(s='0' and r='1') then

qv:='0';

qbarv:='1';elsif(s='1' and r='1') then

qv:='W';

qbarv:='W';end if;

end if;

q


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q


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q


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PROGRAME: 12

STATEMENT: To implement 4 bit comparator using VHDL.

--To implement 4 bit comparator using VHDL.


entity compar is

port(

A:in std_logic_vector(3 downto 0);B:in std_logic_vector(3 downto 0);

equal:out bit;

Agrater:out bit;Aleser:out bit);

end compar;

architecture arch of compar is

begin

equal


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PROGRAME: 13

STATEMENT: To implement 4 bit shift register using VHDL.

--To implement 4 bit shift register using VHDL.

library ieee;


entity shift4 isport( input:in std_logic_vector(3 downto 0);

w,clk,shift_en:in std_logic;

clear,load,left_right:in std_logic;output:buffer std_logic_vector(3 downto 0));

end shift4;

architecture behave of shift4 is

begin

p:process(clear,load,clk)begin

if (clear='1') then

output


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PROGRAME: 14

STATEMENT: 8 bit up counter with count enable and asynchronous reset.


use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity counter8 is

port ( clk:in std_logic;

en:in std_logic;rst: in std_logic;

cout: out_std_logic_vector(7 downto 0));

end counter8;

architecture counter8_arch of counter8 is

signal count:std_logic_vector(7 downto0);begin

process(clk,en,count,rst)

beginif rst=1 then

count0);elsif clkevent and clk=1 then

if en=1 then

count


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PROGRAME: 15

STATEMENT: Sequence detector (Mealy Model)

library ieee;


entity seq_det is

port ( data_in: in std_logic;

clk:in std_logic;

reset: in std_logic;data_out:out std_logic);

end seq_det;

architecture seq_det_arch of seq_det is

type state_type is array (2 downto 0) of bit;constant A: state_type:=000;

constant B: state_type:=001;

constant C: state_type:=010;constant D: state_type:=011;

constant E: state_type:=100;

signal state: state_type;

begin

process(clk,reset)begin

if reset=1 then

state


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when C=> if data_in=1 thenstate


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PROGRAME: 16

STATEMENT: Sequence detector (Moore Model)

library ieee;


entity seq_det_moore is

port(

data_in: in std_logic;

clk: in std_logic;reset: in std_logic;

data_out: out std_logic;

);end seq_det_moore;

architecture seq_det_moore_arch of seq_det_moore is

type state_type is array (2 downto 0) of bit;

constant A:state_type:=000;

constant B:state_type:=001;

constant C:state_type:=010;

constant D:state_type:=011;

constant E: state_type:=100;signal state: state_type;

begin

process(clk,reset,data_in)begin

if reset=1 then

state


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data_out if data_in=1 then

state

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Lab Manul of Vlsi