EE 533Verilog Design

Siddharth BhargavSome of the slides borrowed from Pankaj Golani

Syntax of module definitions

module name (port1, port2, port3, port4, ...); // keywords are in italicsoutput port1;input port2, port3;inout port4;reg port1; // output ports are usually defined as registersreg variable1, variable2; // definitions of local variableswire variable3;initialstatements // any of the behavioral modeling statementsalwaysstatements // any of the behavioral modeling statementsassigncontinuous-assign-statements // required for netsmod1 mod1Instance (variable1, variable2, ...) // instantiating lowerlevelmodulesendmodule

Assignments – Continuous and Procedural

Continuous assignments• Models combinational logic• Assigns values to data-types net

module and(a, b, out);input a, b;output out;wire out;assign out = #1 a & b;endmodule

• Is evaluated as soon as one of the RHS operand changes and value is assigned to LHS

• Out is continuously driven

Procedural assignments• Models combinational and sequential

logic• Assigns values to data-types reg

module and(a, b, out);input a, b;output out;reg out;always @(a or b)beginOut <= #1 a&b;endendmodule

• Out will remain unchanged until the always block is executed again

Examples - Modeling and testbench

module nand2(in1, in2, Out); input in1, in2; output Out; reg Out; always @(in1 or in2) begin Out = ~(in1 & in2); end endmodule

module top;reg a, b; wire out;

nand2 i1(a,b, out);

initialbegin a = 0; b = 0; #5 a = 0; b = 1; #5endendmodule

Always/ initial

• Initial• Starts at time 0• Executes only once• Is typically used for initialization in behavioral code (e.g., testbenches)• Syntax

initialbegina = 1’b1;b = 1’b0;

end• Always

• Starts at time 0• Executes as an infinite loop similar to a infinite loop in C• Syntax

alwaysbegin#5 clock = ~clock;end

Always

When is an always block executed?• always

Starts at time 0• always @(a or b or c)

Whenever there is a change on a, b, or c• always @(posedge clk)

Whenever clk goes from low to high• always @(negedge bar)

Whenever bar goes from high to low

Blocking assignments

• Statements are executed in order.• Example

alwaysbeginX = 0; Y = #10 1; Z = #20 1;End

• X = 0 will happen at time t = 0• Y = 1 will happen at time t = 10• Z = 1 will happen at time t = 30

Non Blocking assignments

• Statements are executed without blocking execution of following statements.

• ExamplealwaysbeginX <= 0; Y <= #10 1; Z <= #20 1;End

• X = 0 will happen at time t = 0• Y = 1 will happen at time t = 10• Z = 1 will happen at time t = 20

NEVER MIX BLOCKING AND NON-BLOCKING !

begin/end and fork/join statements

• begin/end• Event happens in sequence• Example

Begin#10 a=1; At time = 10, a is set to 1#20 b=1; At time = 30, b is set to1End

• control passes out of the block after the last statement executes• fork/join

• Event happens in parallel• Example

fork#10 a=1; At time = 10, a is set to 1#20 b=1; At time = 20, b is set to1Join

• control passes out of the block after time 20

Examples of Combinational Circuits

• Include all input signals to sensitivity list (Example I).

• Avoid inferred latch in combinational circuits• Missing “else statement” (example II).• Missing “variable assignment” (example III).• Missing “conditions” (example III and IV).

Combinational Circuit Example I

• Include all input signals to sensitivity list.

// Poor coding for AND gate.always @(a) // missing “b” signalbegin if ((a == 1’b1) and (b == 1’b1))

// if “a” and “b” is 1 c = 1’b1; // set “c” to 1 else c = 1’b0; // o.w., set “c” to 0end

Combinational Circuit Example I• Recommended coding for AND gate.

always @(a or b) // include both “a” and “b”begin // in sensitivity list. if ((a == 1’b1) and (b == 1’b1)) // if “a” and “b” is 1 c = 1’b1; // set “c” to 1 else c = 1’b0; // otherwise, set “c” to 0end

Combinational Circuit Example II

• Poor coding style: missing “else statement”.

always @(a or b)begin if (a == 1’b1) q = b; // missing “else statement” infers latch. endend

Combinational Circuit Example II

• Recommended coding style.

always @(a or b)begin if (a == 1’b1) q = b; else // include “else statement” q = 1’b0;end

Combinational Circuit Example III

• Missing assignments and condition.always @(d)begin case (d) 2’b00: z = 1’b1; // missing “s” assignment 2’b01: z = 1’b0; // missing “s” assignment 2’b10: z = 1’b1; s = 1’b1; // missing condition “2’b11”. endcaseend

Sequential process assignment

• Use non-blocking assign. in always @(posedge clk) block// Poor coding stylealways @(posedge clk) b = a; // assignment of values depends on whichalways @(posedge clk) // always block scheduler chooses a = b; // first

// Recommended coding stylealways @(posedge clk) begin b <= a; // both signals are assigned at the clk edge a <= b;end

Sequential circuit with sync reset • Process with synchronous reset.

always @(posedge clk)begin if (rst == 1’b1) // synchronous when “rst” is 1 begin … // reset condition end else begin ... endend

Sequential circuit w/ async reset

• Process with asynchronous resetalways @(posedge clk or posedge rst)begin if (rst == 1’b1) // async. reset when “rst” is 1 begin … // reset condition end else begin … endend

Example of D-FF w/ asynch reset

module ASYNC_FF (d, clk, rst, q); input d; input clk; input rst; output q; req q;

always @posedge clk or negedge RST) if (!RST) // reset when “RST” is 0 q <= 0; // set “q” to 0 else // at the positive clk edge q <= d; // set “q” to input “d”

Enable pos edge flip-flop

module pos_ff(clk, in, en, out)input clk, en;input [7:0] in;output [7:0] out;reg [7:0] out;

always @(posedge clk) begin if (en == 1’b1) in = out;endendmodule

FSM Coding Styles

• Separate state memory (SM), next state logic (NSL), and output

function logic (OFL)

• State memory module

reg [1:0] STATE, NEXT_STATE;

always (posedge CLK or negedge RESET) if (!RESET) // asynchronous reset STATE <= IDLE; else // state assignment at clk edge STATE <= NEXT_STATE;

FSM with async reset

• Next state logic (NSL) module (combinational)

always (STATE or RW or INT_REQ or DMA_REQ) begin NEXT_STATE = STATE; // default assignment case (STATE) IDLE: if (INT_REQ) NEXT_STATE = INT_CYCLE; // next state assign. else if ... RW_CYCLE: ... endcaseend

FSM with async reset

• Output function logic (OFL) module (combinational)

always (STATE or RW or INT_REQ or DMA_REQ) beginmux_sels = ADD1MUL1; // default assignment

op_codes = OP1; case (STATE) IDLE: if (INT_REQ) mux_sels = ADD2MUL1; // assignment to mux selects

op_codes = OP1; else if ... RW_CYCLE: ... endcaseend

Memory Instantiation• Commonly , a two dimensional register array

is used for memory instantiation• Sometimes uses FPGA slices rather than in-

built modules.• More slices for book keeping.

• For EE533 , use IP core modules for memory.

Memory Instantiation .. Continued• There is no FOR loop in VERILOG to initialize or

load multiple data into memory.Recommended Coding style :

Always @(posedge clk)Begin If (reset) begin Counter <= 0;

….. end Else begin Counter <= Counter + 1

Case (counter)Memory [16] <=

32’bcafebeef;….

end case end…..end