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COE 203 Syllabus

Page 1 COE 203 Syllabus

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General:

Course Code: COE 203 Title: Digital Logic Laboratory Co-requisite(s): COE 202 (Digital Logic Design)

Catalog Description:

Review of Digital Logic Design: Design of Combinational Circuits, and Design of Sequential Circuits. Logic implementation using discrete logic components (TTL, CMOS), and programmable logic devices. Introduction to Field Programmable Logic Arrays (FPGAs). The basic design flow: design capture (schematic capture, HDL design entry, design verification and test, implementation (including some of its practical aspects), and debugging. Design of data path and control unit.

Grading Policy:

Lab Work 75% Reports 25%

Lab Work Grading Details (out of 100):

Integrating the design: 40 Timing Simulation: 20 Compiling, Bit-file Generation: 05 Verifying on the board: 10 Lab Report*: 25

* Students are recommended to refer to the writing skills improvement material (provided below as links) early in the semester so as to effectively implement suggested improvements in their reports.

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COE 203 Syllabus


Course Objectives:

After successfully completing the course, students will be able to:

1. Design combinational and sequential circuits using discrete components and FPGAs to meet certain specifications.

2. Design and conduct experiments related to digital systems and to analyze their outcomes.

Course Learning Outcomes and Indicators:

Course Learning Outcomes

Outcome Indicators and Details Assessment

Methods and Metrics

Min. Weight

O2. Ability to design and conduct experiments related to digital systems and to analyze their outcomes.

Design & conduct experiments on ripple carry adders, ALU, data & control unit, and learn how to implement on FPGAs.

Lab work 5%

O4. Ability to function as an effective team member

Working in a team to design a digital system and learn how to fast prototype using FPGAs.

Lab work & project

5%

O6. Ability to use design tools for Implementing digital circuits on FPGAs

Ability to use tools and discrete components, FPGAs, to model, simulate and implement digital circuits.

Lab work 5%

Weekly Breakdown of Lecture Course Material

Week Topics

1 Lab Introduction, bread boards, FPGA boards, policies, overview of experiments, reporting, team-work, attendance, grading, etc.

2

(Experiment 1) Introduction • Introduction to Boolean Logic and Gates • ICs and IC pins (Input, Output, I/O, Vcc/Vdd, Vss/GND • Truth tables of Inverter, AND, OR, XOR • Tools and equipment • BreadBoard and verification of Truth Table of above gates

Writing Skills Presentation to be delivered in the Lab. (Based on Instructor Discretion 1 presentation is to be selected out of 3 provided below as links)- Talk will last for roughly 30 minutes

COE 203 Syllabus


3

(Experiment 2) Prototyping of Logic Circuits using Discrete Components • Binary addition and Full adder Circuit Truth Table (Bread boarding) • Building 4-bit adders using 4 cascaded Full adders (Concept, no Bread

boarding) • ALU operation/capabilities • Verification of 4-bit adder operation using the ALU (Bread boarding) • 8-bit Full adder by cascading two ALUs

4

(Experiment 3) Introduction to FPGA • Introduction to FPGAs & Capabilities • Synthesis Flow in FPGAs and Demos for the tools to be used, e.g. schematic

capture &Simulation • Half adder experiment on FPGA board

5 No LAB PROBLEM SOLVING SESSION (Major 1 Week)

6

(Experiment 4) Creating and Using Symbols • Use FPGA tools to build:

a. Half-Adder b. Full adder using 2 HA’s + OR gate c. 4-bit Adder using 4 full adders

• Simulation should be performed and circuit downloaded and tested after developing each macro/symbol

7

(Experiment 5) Introduction to Sequential Circuits • Introduction to sequential circuit • Mod-16 counter • Use of push button for manual clock and bouncing problem. • Solution of bouncing problem. Introduction of debouncing Verilog

code/block • Introduction to LCD files. Use the LCD display to display counter contents (2

Digits)

8

(Experiment 6) Clock and Clock Frequency • Concept of clock and clock frequency • Counters as frequency dividers • Use Oscilloscopes to watch input frequency (on-board 50 MHz and the four

outputs of the counter) • Counter cascading to obtain larger counts • Choose a suitable (divide by x) counter to Generate a ≈ 1 Hz clock • Connect 3-LEDs to output of a 2x4 decoder whose input comes from a 2-bit

counter clocked by: a. The ≈0.75 Hz clock b. A ≈3 Hz clock c. A ≈20 Hz clock

COE 203 Syllabus


9

(Experiment 7) Building a Timer Circuit • Learn the difference between synchronous and asynchronous counters • Learn how to use count enable and carry-out signals • Build synch/asynch Modulo-10 counter • Build Modulo-6, Modulo-12 and Modulo-60 counter • Build 1Hz and 1 KHz pulse generator • Build hours, minutes, seconds timer • Use of LCD to display timer

10 No LAB PROBLEM SOLVING SESSION (Major 2 Week)

11

(Experiment 8) Reaction Timer Part 1 –Generating Random Delay • MSI parts: flip-flop, register, shift register, down counter • Use the datapath and control unit design method • Use frequency dividers to count time units • Generate random numbers using Linear Feedback Shift Register (LFSR)

12 (Experiment 9) Reaction Timer Part 2–Response Time • Saturating BCD counter • Comparing BCD numbers

13

(Experiment 10) Reaction Timer Part 3–The Control Unit and Integration • States and finite state machines (FSM) • Design a control unit as an FSM • Integrate the design to a full reaction timer

14 (Experiment 11) Reaction Timer Part 4–Challenging The Player • MSI parts: decoder, encoder and priority encoder • Extending the datapath without affecting the control unit • Managing different inputs and outputs

15 No LAB PROBLEM SOLVING SESSION (Final Week)

ABET Curricular Action to improve

the Writing

Skills

The Lab instructor is kindly requested to carry out the following actions: 1. Inform the students that their English Writing Skills will be given

10%

2. Request the students to follow the below attached template.

of overall Lab grades based on returned lab assignments and lab project reports.

1. Template for Lab assignments 2. Template for Project Report

3. Request the students follow the below listed writing skills guidelines:

COE 203 Syllabus


1. Writing Skills Presentation 1 2. Writing Skills Presentation 2 3. Writing Skills Presentation 3

4. Grade the students writing (lab assignments and Lab Project report) according to following guidelines: ABET Committee’s Writing Guide

Evidence of graded student writing skill report/assignment is to be kept with Lab instructors for use in future ABET visits.

Additional Material Posted for Students on the Web

Description Link

Lab Manual including syllabus

Available at WebCT in your COE 203 Sec. Files required for debouncing

Files required for using LCD display of FPGA Boards

Experiment 1: Let us get started

Page 1

Experiment 1

LLeett uuss ggeett ssttaarrtteedd Objectives

In this experiment, you will be introduced to:

Boolean Logic and Gates.

Learn logic gates basics (Signal voltages for 0 &1)

Logic operations: AND, OR, NAND, NOR and NOT and their truth tables.

Familiarize with IC’s (IC Pins: inputs, outputs, Vcc & GND, applying inputs and

monitoring outputs)

Verify basic gates operation

Using IC Tester and bread boards

Material Required

ICs – 7404, 7408, 7432, 7486

Wires

Wire Stripper

Prototyping board with power and ground connections

IC Tester

Boolean Logic

What is Boolean Logic?

It is the logic of “Binary” systems, i.e. 2-value systems, where only 2 values are

possible; either “True” or “False”.

Variables in Binary systems are “Binary Variables”, i.e., they can assume one of

only 2 possible values; either “True” or “False”.

In digital circuits, True is represented by a “High” voltage while False is represented

by a “Low” voltage.

Common alternative representation for these two values are “1” and “0”

(alternatively called “True” and “False” respectively).

This means that, in digital logic context, Truehigh1 while FalseLow0

Boolean logic requires its own special algebraic system “Boolean algebra”.

Compared to the normal algebraic operations, logic operations operate only on

“Binary Variables”.

Boolean algebra defines 3 basic Boolean operations; AND, OR and NOT.

In digital circuits, Boolean variables are represented by electronic signals. Boolean

operations on these variables are performed by electronic circuits referred to as

“Logic GATES”.

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Page 2

Experiment 1

AND Gate:

Given two statements (a and b) where each one of them can only be either TRUE or FALSE.

We can say that “statement a” AND “statement b” are TRUE only if “statement a” is true

and “statement b” is also True. Thus, AND-ing two True statements results in a True overall

statement.

In digital logic context, the output of an AND gate is True (High) only when ALL of its

inputs are individually True (High).

To describe the “AND” operation, we use a “Truth Table”. The Truth Table of a gate

specifies the output value of this gate for all possible input value combinations. For n

inputs, the number of possible input value combinations is 2n.

The truth table for the two-input “AND” gate is shown below.

NOT Gate:

Another important logic operation is the inverter or the complement; which is sometimes

called “NOT”. It is simply negating the logic making it “TRUE” if it was “False” and vice

versa. Now, try to write down the “NOT” truth table in the space below.

OR Gate:

OR gate output is always “HIGH” except when ALL the inputs are “LOW”.

Two inputs XOR gate output is same like two inputs “OR” excluding the case when both

inputs are high. Another way to describe the two inputs XOR gate is: its output is high if

the inputs are different while output is low if the inputs are the same.

Now, can you complete the following truth tables, one for OR and other for XOR?

In1 In2 Out

T T T

T F F

F T F

F F F

In1 In2 Out

1 1 1

1 0 0

0 1 0

0 0 0

In Out

T

In1 In2 Out

In1 In2 Out


Page 3

Experiment 1

Truth table verification using TTL ICs

Each IC in the 74 family has a number. The number, clearly, starts by 74, then followed by

few letters. These letters are related to some characteristics of the electronics inside. Some

examples of these letters are:

74L - Low power (compared to the original TTL logic family), very slow.

LS - Low Power Schottky (named after German physicist Walter H. Schottky)

AS - Advanced Schottky

ALS - Advanced Low Power Schottky

F - Fast (faster than normal Schottky, similar to AS)

Then the number is followed by 2 or three numbers. These numbers are the important part

that tells you what gates you can find inside the IC. For example:

74xx04 is NOT gate

74xx08 is AND gate

74xx32 is OR gate

74xx86 is XOR gate.

Using ICs with Bread Board

To be able to use an IC you need to refer to its data sheet. The pin layout is an essential

part of any data sheet.

Any IC has electronic circuits inside, so the first thing to connect to any IC is power. You

need an external power source (like a battery) to the IC power terminals (pins). These pins

are usually called Vcc (or Vdd) and Gnd (or Vss). Other than the power pins there are input

and output pins. See the last page of this experiment for gates pin layout examples.

Procedure

This experiment contains two parts:

In part 1, verify the truth tables of 2-input AND, NOR and XOR gates.

In part 2, build a 4-input AND gate using 2-input AND gates.

Part I – Verify the truth tables of 2-input AND, NOR and XOR gates.

Get the proper ICs (AND, OR, XOR, NOT) from the shelves.

Test the ICs on the IC tester.

Place the chips on the breadboard carefully.

Connect the Vcc pins of the chips to the +5V on the board.

Connect the GND pins of the chips to the GND on the board.

Use 2 switches for each of the 2 input AND, NOR and XOR gates and 3 LEDs for the

output of each gate.

Verify the truth tables of 2-input AND, NOR and XOR gates.


Page 4

Experiment 1

Part II –Build a 4-input AND gate using 2-input AND gates.

Using the AND gate chip (7408) make the 4-input AND gate circuit.

Connect 4 switches to the 4 inputs of the AND gate and an LED at the output of the

gate.

Verify the truth table of 4-input AND gate.

Lab Report

Submit the circuit of 4-input AND gate using 2-input AND gates and the truth table of 4-

input AND gate.

Figure 1.1: Internal Connections of Bread Board

Figure 1.2: Sample Circuit with Chips on Bread Board


Page 5

Experiment 1

By: Masud-ul-Hasan

Breadboard

By: Masud-ul-Hasan

Shape

By: Masud-ul-Hasan

Connections

By: Masud-ul-Hasan

Connections

Gap

By: Masud-ul-Hasan

Usage

Experiment 2: Prototyping of Logic Circuits using Discrete Components

Page 1

Experiment 2

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Objectives

In this experiment, you will learn:

Binary addition using Full adder

Building 4-bit adder

ALU (Arithmetic Logic Unit) operation/capabilities

Verification of 4-bit adder operation using ALU

Building 8-bit adder using 2 cascaded 4-bit adders (2 ALUs)

Material Required

ICs – 7408, 7432, 7486, 74181

Wires

Wire Stripper

Prototyping board with power and ground connections

IC Tester

Design Specifications

You will construct a full adder circuit. The full adder is a common circuit used in many

designs both small and large (including processors). The function of the full adder is quite

simple – add three, one-bit numbers. This may seem like a simple process, but the full

adder is designed to be cascaded to compute addition on (arbitrarily) larger numbers.

Your circuit must have three inputs, A, B, and Cin and two outputs, Sum and Cout. The

block diagram is shown in Figure 2.1 below:


Full

Adder

Sum

Cout

A

B

Cin

Figure 2.1: Block diagram of the Full adder circuit


Page 2 Experiment 2

Following is the truth table of Full adder circuit:

A B Cin Cout Sum

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Table 2.1: Truth Table of Full Adder

By simplifying the two outputs Sum and Cout using any minimization scheme (K-Maps, Boolean algebra, etc), you will get:

Sum= A ⊕ B ⊕ Cin

Cout = AB + ACin + BCin

Now implement the above two simplified Boolean equations on the breadboard using discrete components. The circuit diagram will be as follows:

Figure 2.2: Circuit diagram of the Full adder circuit


Page 3 Experiment 2

Procedure

This experiment will be developed in 2 main parts plus one bonus• In part 1, a 1-bit full adder circuit will be implemented.

part:

• In part 2, a 4-bit adder circuit will be built using an ALU. • In part 3 (bonus), an 8-bit adder circuit will be built by cascading two ALUs.

Part I – In this part, a 1-bit full adder circuit will be built. • Get the proper ICs (AND, OR, XOR) from the shelves. • Test the ICs on the IC tester. • Place the chips on the breadboard carefully. • Connect the Vcc pins of the chips to the +5V on the board. • Connect the GND pins of the chips to the GND on the board. • Build your logic diagram by making appropriate connections as shown in Figure 2.2 • Use 3 switches for the 3 inputs A, B, and Cin. • Connect the two outputs Sum and Cout to 2 LEDs. • Use the switches on the board to verify your circuit.

The circuit of a Full adder can be cascaded to build a 4-bit adder as shown (below) in Figure 2.3.

Part II– In this part, a 4-bit adder circuit will be built using an ALU. To avoid too many wiring, we will use the 4-bit adder as one of the available functions of ready made 4-bit ALU.

• Now use 74181 ALU on the breadboard. • Connect Vcc and Gnd of 74181 to +5V and GND of the board respectively. • Connect the four As (A3 A2 A1 A0) of 74181 to four switches. • Connect the four Bs (B3 B2 B1 B0) of 74181 to other four switches. • Connect M (mode) to the Gnd of the board. • Connect CR to the Vcc of the board. • Connect the four outputs F3 F2 F1 F0 of 74181 to the four LEDs. • Connect C (Carry out) to another LED. • Check the addition operation of 74181 ALU by making the select lines S3 S2 S1 S0

as 1 0 0 1 (fix these values by connecting S3 and S0 to +5V while S2 and S1 to GND)

• Change the values of the A and B switches and verify the result on the LEDs.

Figure 2.3: Block diagram of a 4-bit adder circuit.

C4 C3 C1 C2

Full Adder

Full Adder

Full Adder

Full Adder

A3 B3 A2 B2 A1 B1 A0 B0 C0

S0 S1 S2 S3


Page 4 Experiment 2

Part III (Bonus) – In this part, an 8-bit adder circuit will be built by cascading two ALUs.

• Extend your design to 8 bit adder circuit by cascading two 74181 chips and connecting the carry out (C) of the first to carry in (CR) of the second ALU. Join select lines and M of both chips together.

• Fix the select lines of both ALUs S3 S2 S1 S0 to 1 0 0 1 for addition function and M to Gnd of the board as in Part II.

• The first ALU will serve as lower nibble (half byte 4 3 2 1) and second ALU will serve as higher nibble (half byte 7 6 5 4).

• Due to limited number of switches, connect eight As (A7 A6 A5 A4 A3 A2 A1 A0) to eight switches.

• Connect eight Bs (B7 B6 B5 B4 B3 B2 B1 B0) to fix values (by connecting +5V and GND) like 00110011.

• Connect the eight outputs F7 F6 F5 F4 F3 F2 F1 F0 of 74181 to the eight LEDs. Leave the carry out (C) of second ALU unconnected as no LED will be left.

• Change the values of As switches and verify the result on the LEDs.

Table 2.2: Function Table of 4-bit ALU (74181)

Lab Report

Print the lab report format and write a complete lab report on this printed document about this experiment as mentioned in the document.


Page 5 Experiment 2

181 4-Bit ALU

Experiment 3: Introduction to FPGA

Page 1

Experiment 3

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Objectives

In this experiment, you will:

Get introduced to FPGA board

Get familiar with the ISE design suite and the ISim simulator

Learn how to make design entry and bind I/O board switches and LEDS

Design, simulate, and verify simple logic gates on board

Material Required

Spartan 3A board

ISE design suite software


In this experiment, you will be familiarized with the FPGA boards available in the lab. FPGA

stands for Field Programmable Gate Array, which is a programmable chip that allows you

to test and run, complicated logic designs.

The FPGA board used in this lab is the Xilinx Spartan3A board. The design process starts

with design preparation of the required logic circuit. Using ISE Design Suite, you will be

able to:

enter the design using schematic drawing

simulate the design to verify its functionality

download the configuration bits file of the verified design to the FPGA

verify the design on board

In this lab, you will make a design entry of a Half Adder. Then you will verify its functionality

using the behavioral simulator ISim. Finally, you will assign the I/O (Input/Output) of the

design to physical switches and LEDs of the board and program it.



Page 2

Experiment 3

Procedure

The procedure of this lab will be developed in 7 main parts;

1. In part 1, you will create and setup the project files and parameters in ISE design

suite software.

2. In part 2, you will enter the design using Schematic drawing.

3. In part 3, you will simulate the design and verify its functionality.

4. In part 4, you will connect the inputs and outputs of the circuit to input and output

pins in the FPGA board.

5. In part 5, you will generate the configuration bits file of the design.

6. In part 6, you will generate and analyze the post-place and route timing report.

7. In part 7, you will download the design configuration bits file to the FPGA board.

1. Create a New Project

The objective here is to setup the project files and parameters. A project in ISE is a

collection of all the files needed to create and download a design to the selected FPGA

device. The project will be adapted to use the FPGA available on our board. The project

allows us to draw a schematic as the main way of entering the design. Here are the steps

for creating a new project:

1. Launch Xilinix ISE design Suite software

2. Select File, New Project.

3. In the New Project Wizard dialog box, type the desired location in the Project

Location field, or browse to the directory under which you want to create your new

project directory using the browse button next to the Project Location field.

4. Enter “lab3” in the Project Name field. When you enter “lab3” in the Project Name

field, a lab3 subdirectory is automatically created in the directory path in the Project

Location field.

5. Use the pull-down arrow to select Schematic from the Top-Level Source Type field.

Click in the field to access the pull-down list.

6. Click Next.

7. In the New Project Wizard Device and Design Flow dialog box, use the pull-down

arrow to select the Value for each Property Name. Click in the field to access the pull-

down list. Make sure the values are as follows:

● Device Family: Spartan3A and 3AN

● Device: XC3S700A

● Package: fg484

● Speed Grade: -4

● Top-Level Module Type: Schematic

● Synthesis Tool: XST

● Simulator: ISim

● Preferred language: VHDL

8. When the table is complete, your project properties should look like Figure 1.


Page 3

Experiment 3

Figure 1: Project Properties

9. Click Next.

10. Click Finish to create the project. A summary of the project will be shown as in Figure 2.

A new project called lab3 is created and is shown on the left side panel under

implementation tab.

Figure 2: Summary of the Project

11. Right click on lab3 project and choose New Source. Select Schematic from the box on

the left and type in a file name for your project such as “halfadder”. Click Next. Click

Finish. A new Schematic file is created, click on symbol tab to show different symbols

and logic gates


Page 4

Experiment 3

2. Schematic Design Entry

The objective here is to enter the design using Schematic drawing. You will design a simple

half-adder using AND and XOR gates as follows,

1. Add a 2 input AND gate as follows,

● From the toolbar go to Add, click on Symbol. Or click the Add Symbol icon in the

vertical toolbar to the left of the workspace (Looks like a gate with a resistor below

it). Or simply click on symbols tab in the bottom of the design panel

● Select Logic from the list of Categories

● Select and2 from the list of Symbols

● Place one AND gate on the schematic. Click the left mouse button to place the gate

on the schematic where the cursor sits

● Press Esc to exit Add Symbol mode and restore your select tool

2. Add a 2 input XOR gate as follows,

● Select Logic from the list of Categories.

● Select xor2 from the list of Symbols.

● Place one XOR gate next to the AND gate on the schematic. Click the left mouse

button to place the gate on the schematic where the cursor sits.

● Press Esc to exit Add Symbol mode and restore your select tool

3. Adjust your view using the Zoom option (View, Zoom, In) and the scroll bars in the

schematic window

4. Add I/O Markers:

I/O markers are needed by the design tool to synthesize the design. They give a logical

connection for the synthesis tool to understand that the internal signal will be passed

outside either the chip or schematic. It is very important that the correct type of I/O

marker be used. Putting an input I/O marker on an output pin will cause an error.

Fortunately, ISE will automatically decide if the maker is input or output when it is

connected to the pin.

● Select Add, I/O Marker. Or click the Add I/O Marker icon from the vertical menu

bar

● Add input markers to the AND and XOR gates as follows,

○ Place the cursor, which now displays the input graphic, at the end of the input

wire

○ To rename the I/O Marker, double click on the I/O marker and chose Nets from

the left side. Type the name of the marker in the Value of the Name attribute. Or

Right Click and choose Rename port

○ Name the input markers of the AND gate A and B

○ The input graphic is added to the end of the wire, around the net name

● Wire the inputs of the AND gate to the inputs of the XOR gate

○ Select Add Wires from the vertical menu bar, and connect input I/O markers to

the XOR gate as shown in Figure 3


Page 5

Experiment 3

● Add an output marker to the output of the AND gate and another to the output of

the XOR gates

○ Select the Add an output marker radio button on the Options tab.

○ Place the cursor, which now displays the output graphic, at the end of

the output wire.

○ Name the output marker of the AND gate C and the output of the XOR

gate S

Figure 3

Your schematic is complete. Save the schematic diagram using File -> Save or press on the

Save icon on the toolbar.

3. Behavioral Simulation

The objective here is to simulate the design to verify its functionality. ISE provides an

integrated simulation flow with the ISim simulator that allows simulations to be run from

the Xilinx Project Navigator GUI. We introduce the concept of simulation and how to verify

the function of a circuit through behavioral simulation.

1. In the project navigator to the left, click on the Design tab, then click on your

schematic file. Change to the simulation mode by selecting the Simulation radio

button as shown in Figure 4.

Figure 4


Page 6

Experiment 3

2. Press on the + mark in front of ISim Simulator to expand the list. Right click on the

Simulate Behavioral Model and choose Process Properties to change simulation

attributes. Uncheck the mark in front of Run for Specified Time. This will not limit

the simulation for a specific run time. Press OK.

3. To run the simulation, double click on Simulate Behavioral Model, or right click

and press Run.

4. ISE will launch ISim in a separate window. If it didn’t, refer to the lab manual to

check the error logs and how to correct them. Note that the simulation will fail to

run if a current process of ISim is working, close any instance of ISim before running

any simulation.

5. ISim will launch automatically. The wave window displays the signals, buses and

their waveforms. Note that there are four signals shown; A, B, S, and C.

Figure 5

6. Right click on input A in the objects window, and choose Force clock. Add the

following values:

a) Leading Edge Value: 0

b) Trailing Edge Value: 1

c) Period: 1 us

7. Alternatively, you can write the following Tcl command in the console window:

a) isim force add A 0 -value 1 -time 500 ns -repeat 1 us

8. Similarly, right click on input B in the objects window and choose Force clock. Add

the following values:

9. Alternatively, you can write the Tcl command in the console window,

a) Leading Edge Value: 0


Page 7

Experiment 3

b) Trailing Edge Value: 1

c) Period: 0.5 us

10. Alternatively, you can write the Tcl command in the console window,

isim force add B 0 -value 1 -radix bin -time 250 ns -value 0 -radix bin -time 500 ns -

value 1 -time 750 ns -repeat 1us

11. Enter 1 us inside the simulation time toolbox in the toolbar, and then press Run for

the Time Specified in the Toolbar icon. Or type the following Tcl command in the

console window.

Run 1 us

12. The simulator will show the behavior of the gates according to the specified input

signals, press in Zoom to Full View in the toolbar to show the entire simulation

period.

13. The simulator will show the behavior of the gates according to the specified input

signals, press in Zoom to Full View in the toolbar to show the entire simulation

period. You can Zoom in and Zoom out using the icons in the toolbar. Your signals

should look like the following:

Figure 6

14. To restart the simulation, press on Restart icon on the toolbar. Note that restarting

the simulation will also remove the force clock values. You have to apply force clock

to the input signals before running the simulation again.

15. Verify that the circuit is working correctly by checking the time diagram (waveform)

as shown in Figure 6.

16. Close ISim and return to ISE.


Page 8

Experiment 3

4. Package Pins Assignment

The objective here is to connect the inputs of the circuit (A & B) to 2 of the input pins of

the FPGA chip which are connected to board switches. Likewise, we want to connect the

output of the circuit (S & C) to 2 of the output pins of FPGA chip which are connected to

board LEDs. This will allow us to manually test the circuit on the board. Switches and LEDs

on the FPGA board are connected as follows:

1. Choose input and output pins on your Digital Logic Board. See appendix A in the Lab

Guide for the pins diagram. Refer to Appendix B in the Lab Guide to find which pins of

the chip FPGA are connected to the board switches and LEDs. Pick two switches (inputs)

and two LEDs (outputs).

2. In the project navigator to the left, click on the Design tab. Then click on your schematic

file. Change to implementation mode by selecting the Implementation radio button

on top.

3. Click on I/O Pin Planning (Plan Ahead) – Post-Synthesis under User Constraints. This will

launch PlanAhead.

4. In PlanAhead, select the I/O Ports tab in the left panel, expand Scalar ports. You will find

a list of the I/Os of your schematic design, i.e., {A, B, S, and C}.

5. Decide the site number of the switch(es) and LED(s) for inputs and outputs on your

board (represented by a small code on the board). In this guide, we are using SW0,

SW1, LD0, and LD1 which have the sites v8, u10, r20, and t19, respectively.

6. Click on the I/O port, then click the column under Site on front of the I/O port and

choose the corresponding site from the drop down list. Do it for A, B, S, and C.

Figure 7

7. Once the pins are locked down, select File → Save Design. The changes made in

PlanAhead are saved in the lab3.ucf file in your current working directory.

8. Exit PlanAhead.


Page 9

Experiment 3

5. Design Implementation

The objective here is to generate the configuration bits-file which, when downloaded to the

FPGA chip, configures it to implement our specific design. Note: For more information

about implementing a design, see ISE Help. Select Help, ISE Help Contents, expand either

the FPGA or CPLD hierarchy in the left pane and expand the Implementing Design

hierarchy.

1. Click on your schematic file in the project navigator.

2. Double-click on Generate Programming File in the Processes window. This runs all

processes and creates the configuration bits file of this design. Be patient – this takes a

while!

3. The BitGen program creates the (halfadder.bit bitstream file. The bitstream file contains

the actual configuration data.

4. A check on the Processes for Source window denotes a process that was run

successfully. An exclamation sign indicates that the process was run and that there is a

warning for the process. More information about warnings can be obtained in the

Transcript window.

6. Timing Analysis

The objective here is to analyze the time report of the implemented design. To see the

timing report, go to Tools->Timing Analyzer->Post-Place & Route. The timing

report will be shown in the right window similar to Figure 8

Figure 8

Programming the Spartan Board


Page 10

Experiment 3

7. Board Programming

The objective here is to download the design configuration bits file to the FPGA board. The

detailed procedure is as follows,

1. Turn on your Xilnix Spartan-3AN Board and make sure that the board cable is properly

connected to the PC.

2. Double-click Generate Programming File to create a bitstream of your design

3. The BitGen program creates the halfadder.bit (a bitstream file). The bitstream file

contains the actual configuration data.

4. Click on Configure Device to expand the list, then double click on Generate Target

PROM/ACE File. A pop-up window will appear, click OK.

5. ISE will automatically run iMPACT. Double-click on Boundary Scan Mode in the

iMPACT Flows box on the left.

6. Right-click in the middle of the white window to initialize new JTAG chain. Choose

Initialize Chain. This will create and show a device chain. Click Yes if it asks to continue

and assign configuration files.

7. Choose the halfadder.bit file you generated in the proper directory. Click Open. Click

No to attach SPI or BPI PROM.

8. A window will appear “Add PROM File”, choose Cancel.

9. Another window will open, this time click Bypass. Then click OK.

10. A window will appear “Device Programming Properties”, click OK.

11. Right-click on the first chip, named xc3s700a, and choose Program. When the program

operation completes, a blue message with “Program Succeeded” appears.

12. Congratulation, your design is programmed in the Xilnix board. Go and have fun with it.

You should be able to verify the design of the circuit using switches and LEDs.

13. Show your design to the lab instructor.

14. When you close the program, it will ask you to “Save current project before exiting ISE

IMPACT”. Click NO.

15. Turn off your Xilnix Spartan-3A board after showing it to the instructor.

16. Follow the same steps that you have done with the instructor and make a 1-bit full

adder circuit. Simulate it using ISim and test it on FPGA board.

Lab Report

Print the lab report format and write a complete lab report on this printed document about

this experiment as mentioned in the document. Submit the printed circuit diagram of full

adder, simulation screen shot and timing report as an attachment with the lab report.

Experiment 4: Creating and Using Symbols

Page 1

Experiment 4

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Objectives


Get more familiar with FPGA and design tool

Learn about symbols and hierarchical design

Build Half-Adder and define it as a symbol

Use the Half-Adder symbol to build a Full-Adder, and define a symbol for it

Build a 4-bit adder using Full-Adder symbols

Material Required

Xilnix FPGA board

ISE design suite


In experiment 2, you have constructed a full-adder using IC circuits and verified it using a

prototype board. This week, you will use FPGA board to design, simulate and verify

different circuits. First, you will build a Half-Adder (HA). The function of the Half-Adder is to

add 2 input bits. Thus, the half-adder has only two inputs and two outputs. The circuit

diagram and the truth table of the half-adder are shown in figure 1 and figure 2. You will

create a symbol of this circuit and name it as “HalfAdder”.

Figure 1: Logic diagram of half-adder

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Table 1: Truth table of half-adder



Page 2

Experiment 4

Then you will design a full-adder (FA) using the symbol you created. You might already

know that full-adder adds three bits and produces two output bits. Figure 2 shows the

circuit diagram of the full-adder. Note that you need two half-adders and one 2-input OR-

gate. Similarly, you will create a symbol for the full adder to be used as one unit and call it

“FullAdder”.

Figure 2: Logic diagram of a 1-bit full-adder

Finally, using N full-adders, you can create a circuit that adds two N-bit numbers. The carry-

in of each Full Adder is the carry-out of the previous Full Adder. This type of adder is called

a ripple carry adder (RCA). In this lab, you will build a 4-bit binary adder using the four 1-bit

full-adder symbols you have created previously. The logic diagram of the 4-bit adder is

shown in Figure 3.

Procedure

The procedure of this lab is divided into 5 main parts as follows,

1. In part I, you will build and verify a Half-Adder circuit

2. In part II, you will build a symbol of Half-Adder

3. In part III, you will build a Full-Adder using Half-Adder symbols

4. In part IV, you will build a Full-Adder symbol

5. In part V, you will build a 4-bit adder using Full-Adder symbols

Note: you may refer to the lab guide for detailed step-by-step procedure

C4

C3 C1 C2

Full

Adder

Full

Adder

Full

Adder

Full

Adder

A3 B3 A2 B2 A1 B1 A0 B0 C0

S0 S1 S2 S3

Figure 3: Logic diagram of a four-bit adder


Page 3

Experiment 4

Part I

Objective: Build and verify the operation of the H.A. circuit

1. Start ISE Design Suite, Create a new project. Choose Schematic as Top-level source

type and set project settings properly (Section II part 1 in lab guide).

2. Create a new source of type Schematic and name it “HalfAdder”

3. Draw the logic diagram of the half-adder in the schematic editor window as shown

in Figure 1

4. Append I/O markers properly. Name the inputs A and B, and the outputs, S and C

5. When you finish, save and run the behavioral simulator Isim

6. Use the following Tcl commands to add force clock to the inputs (or do it through

“Force Clock” method as you have done before in previous experiment).

● isim force add {/HalfAdder/A} 0 -radix bin -value 1 -radix bin -time 500 ns -repeat 1 us

● isim force add {/HalfAdder/B} 0 -radix bin -value 1 -radix bin -time 250 ns -repeat 500 ns

7. Run the simulation for 1 us, then verify the output signals. Close ISim if your design

entry simulation is correct. Otherwise, go back and correct the mistakes, if any.

8. Choose any of the board switches and LEDs and note down their site numbers.

Using PlanAhead, assign I/O ports in your design entry to the selected switches and

LEDs.

9. Generate Bit file, and Program your board.

10. Verify half-adder functionality on the board.

Part II

Objective: Define a higher level symbol of the H.A.

1. To create a symbol of your half-adder, in ISE Schematic Editor, go to Tools-

>Symbol Wizard

2. Click on Using schematic options and choose your schematic file from the

dropdown list. Click Next.

3. Edit Symbol name, name it “HalfAdder”. Make sure that all pin definitions are

correct. Click Next.

4. Click Next on the layout page, then Finish in the Preview page

5. Now your symbol is already added to the symbol library in your project. You can

find it under categories (will have the long path of your file) or simple type its name

in Symbol name filter.


Page 4

Experiment 4

Part III

Objective: Build a F.A. using H.A. symbol

1. Create a new source (of type Schematic) and name it “FullAdder”.

2. Draw the logic diagram of the full-adder in the schematic editor window, as shown

in Figure 2, using the H.A symbol created in Part II.

3. Append I/O markers properly. Name the inputs A, B, and Cin, and the outputs, S

and Cout.

4. When you finish, save and run the behavioral simulator Isim.

5. Use the following Tcl commands to add force clock to the inputs (or do it through

“Force Clock” method as you have done before in previous experiment).

isim force add {/FullAdder/A} 0 -radix bin -value 1 -radix bin -time 1000 ns -repeat 2 us

isim force add {/FullAdder/B} 0 -radix bin -value 1 -radix bin -time 500 ns -repeat 1 us

isim force add {/FullAdder/Cin} 0 -radix bin -value 1 -radix bin -time 250 ns -repeat 500 ns

6. Run the simulation for 1 us and then verify the output signals. Close ISim if your

design entry simulation is correct. Otherwise, go back to your design entry and

correct any mistakes.


Using PlanAhead, assign I/O ports in your design entry to the selected switches

and LEDs.


9. Verify full-adder functionality on the board.

Part IV

Objective- Define a F.A. symbol

1. To create a symbol of your full-adder, in ISE Schematic Editor, go to Tools-

>Symbol Wizard

2. Click on Using schematic options and choose your schematic file from the

dropdown list. Click Next.

3. Edit Symbol name, name it “FullAdder”. Make sure that all pins definitions are

correct. Click Next.

4. Click Next on the layout page, then Finish in the Preview page

5. Now your symbol is already added to the symbol library in your project. You can

find it under categories (will have the long path of your file) or simple type its name

in Symbol name filter.


Page 5

Experiment 4

Part V

Objective: Build a 4-bit adder using F.A. symbols

1. Create a new source of type Schematic and name it “fourBitAdder”

2. Draw the logic diagram of 4-bit adder in the schematic editor window, as shown in

Figure 3, using F.A symbol created in Part IV

3. Append I/O markers properly. Name the inputs A0, A1, A2, A3, B0, B1, B2, and B3

accordingly. Name the outputs S0, S1, S2, S3, and Cout.

4. Connect the first carry in C0 to ground (gnd) to make it permanently zero.

5. When you finish, save and run the behavioral simulator Isim

6. Verify the simulation results using proper input signals. You should test different

input signals to ensure correct functionality of the adder.


Using PlanAhead, assign I/O ports in your design entry to the selected switches

and LEDs


9. Verify 4-bit full-adder functionality on the board.

Lab Report


this experiment as mentioned in the document. Attach all the three simulation snapshots

and all the circuit diagrams.

Experiment 5: Introduction to Sequential Circuits

Page 1

Experiment 5

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Objectives

In this experiment, you will learn about:

Sequential circuits

Counter circuits

The use of Liquid Crystal Display (LCD)

The bouncing problem

Solving the bouncing problem with a debouncing circuit

Material Required

PC with Xilinx software installed

FPGA Board

Debouncing circuit block

LCD Display block and other related files


Sequential Circuits:

A combinational circuit is a circuit whose outputs depend only upon the present

inputs but a sequential circuit is a circuit whose outputs depend upon present input

as well as past inputs. In other words, the outputs of the circuit have sequential

behavior. An example of such a circuit is a binary counter. In a binary counter, the

output is incremented or decremented by 1 with each clock pulse and therefore the

new output always depends upon the previous output of the circuit along with the

clock pulse.


Figure 5.1: Block diagram of combinational circuit


Page 2

Experiment 5

Sequential circuits are important because only combinational logic is not enough

for synthesizing a sophisticated digital system. A sequential circuit is nothing but

the conjunction of a combinational circuit along with a storage facility or memory

element. The memory element stores the past values of the outputs of the circuit

and thus provides a way to feed them back to the circuit as inputs.

Examples of sequential circuits are counters, registers, sequence detectors, traffic

signal controllers, vending machines, etc.

One requirement common to many digital circuits is counting, both forward and

backward. Examples include digital clocks and timers watches which are found in a

range of appliances from microwave ovens, washing machines, to automobiles.

Here we are going to use a 4-bit binary (Mod-16) counter circuit available in the

Xilinx software library.

Procedure

This lab is divided into three main parts:

I. Study of a counter circuit operation using manual clock push button and

recognizing the bouncing problem.

II. Use of a debouncing circuit to solve the bouncing problem.

III. Use of the FPGA board LCD display (instead of LEDs) to display the output of

the counter.

Figure 5.2: Block diagram of sequential circuit


Page 3

Experiment 5

Part I -Study of bouncing problem by using a counter circuit.

In this part of the experiment, a 4-bit up counter will be used with manual clocking

to observe the bouncing problem of the manual clock push button.

Start a new project.

Get a 4-bit counter CB4CE (with clear CLR and chip enable CE) from the

library of Xilinx software in your schematic drawing.

Connect the clock input “Clk” to a push button.

Connect the clear input “CLR” to another push button.

Connect the CE to VCC to make it enabled all the time.

Connect the five outputs Q0, Q1, Q2, Q3, and CEO to five LEDs in such an

order that Q0 should be the least significant bit.

Now test your circuit by pressing the manual clock push button. It should

count up from 0 to 15 in binary on 4 LEDs.

Clear should make the count 0 whenever it is pressed.

While compiling the project if manual clock gives any error then you have

to add the following command as the last command in your .ucf file by

double clicking on .ucf file:

NET “CLK” CLOCK_DEDICATED_ROUTE = FALSE;

Even though the counter should count up one time when the clock push

button is pressed only once, observe that it actually counts up by more

than one due to bouncing problem.

Figure 5.3: 4-bit Counter with Chip Enable and Clear


Page 4

Experiment 5

Bouncing Problem:

A big problem with mechanical switches (especially push buttons) is that when the

switch is moved to a new position it strikes the metal contact and physically

bounces a few times due to elasticity. This is called contact bounce or simply

bouncing problem.

If a switch is to turn on a lamp or start a fan or motor, then contact bounce is not a

problem because these devices are slow. But if a switch is used as input to a digital

counter, a personal computer, or a micro-processor based piece of equipment, then

contact bounce must be considered. The reason for concern is that the time it takes

for contacts to stop bouncing is measured in milliseconds and digital circuits can

respond in nanoseconds.

Solution:

To solve this problem there are different ways which are called “debouncing”. We

are solving it here by using a piece of code written in Verilog language. It is

basically a counter. The logic used is that when this counter detects the first

transition (change in the position of switch), it starts counting 50,000 cycles of the

on board clock (50 MHz) to create a delay before it outputs the final value of the

switch. This delay time is enough for the bounces to disappear.

How to use it?

It is very simple. Just add Verilog file debouncing.v to the project. Create a symbol

of it as shown in the Figure 5.5and use it. It has two inputs; the noisy signal

(noisyclk) and the system clock (sysclk). The output is the clean version of the noisy

signal. Connect push button that you are using for manual clock to the noisy clock

and system clock (E12) of the FPGA board to the system clock input of the

debouncing circuit. Connect output (cleanclk) to the clock input of your circuit.

Figure 5.4: Bouncing problem of a mechanical switch


Page 5

Experiment 5

Part II - Solving of the bouncing problem with a debouncing circuit.

In this part, a special circuit will be used to solve the bouncing problem.

Get the debouncing.v file from WebCT and add source to your project.

Create a symbol of it.

Add the debouncing symbol in your circuit as shown in the figure.

Delete the Clk input pad from the circuit and connect “cleanclk” to the

clock of the counter.

Edit the .ucf file as mentioned above. Sysclk should be the system clock

E12 and noisyclk should be the push button.


count up from 0 to 15 in binary on 4 LEDs without any bouncing

problem.

Figure 5.5: The symbol of debouncing circuit

Figure 5.6: Counter with debouncing circuit


Page 6

Experiment 5

Part III – Use of LCD Display

In this part of experiment, an LCD block (code) will be used to show the results on

LCD display instead of LEDs.

Delete the five output pads of the counter circuit.

Get the LCD related Verilog file (.v) and the .ucf file from WebCT and copy

these in your project folder.

Add the Verilog file to your project (by add source) and then make the

symbol of it.

Add this symbol in your circuit in such a way that the five inputs naming

I0, I1, I2, I3, I4 of LCD_block should be connected to the 4 Q outputs and

CEO output of the counter.

Connect the clock of LCD_block to the system clock.

Connect the reset of LCD_block to the clear of counter.

Add the output pads to all the outputs of this block and name these pads

with the same names of the outputs of the block as shown in the figure.

Edit the .ucf file by adding the commands at the end of your .ucf file

which are given in the .ucf file downloaded from webCT.


count up from 0 to 15 in Decimal on LCD display.

Lab Report


this experiment as mentioned in the document.

Figure 5.7: LCD_block added to the circuit.

Experiment 6: Clock and Clock Frequency

Page 1

Experiment 6

Clock and Clock Frequency

Objectives


Learn the concept of clock and clock frequency

Learn how to use oscilloscope

Construct a circuit to generate lower frequency clocks using counters

Learn the concept of carry out and count enable

Use multiplexers to choose among different clock frequencies

Use of buses and bus taps

Material Required


Spartan3AN FPGA board

CC16CE (4-bit Counter) and M4_1E (4 X 1 MUX) symbols

Oscilloscope


1. Clock signal

Sequential circuits are controlled by a periodic control signal, called the “clock”. This signal

allows memory elements to change their states at either the rising or the falling edges of this

signal (Figure 6.1). This clock signal is generated by a built-in clock on the FPGA board.

Figure 6.1: Clock signal

Spartan3A FPGA has a global built-in clock frequency of 50 MHz (20 ns period). This clock is

too fast to be monitored with human eyes. Thus, we need a circuit to reduce this frequency

to lower frequencies that we can observe using human eyes. In this lab, you will design a

clock division circuit that reduces this frequency to different slower frequencies.

Experiment 6:

1

0

Rising clock edge

Falling

clock edge

Clock Period = T seconds Clock frequency = # of clock cycles / seconds

=


Page 2

Experiment 6

You will observe the clock signal from your board using an electronic test instrument called

oscilloscope. A typical oscilloscope, Figure 6.2, is divided into four sections; the display,

vertical controls, horizontal controls, and trigger controls. A probe is connected with

oscilloscope from one end and to the output you want to monitor on the other end. In this

lab, you will probe an output pin on your board to monitor the 50 MHz signal.

Figure 6.2: Oscilloscope

2. Frequency division

Consider a 2-bit counter (also known as Mod4 counter), the counter count sequence is

shown in Figure 6.3. The period of the Q0 signal is double the period of the clock, i.e.

frequency of Q0 =

. Similarly, the period of the Q1 signal is four times the period of the

clock, i.e. Q1 =

. Thus we can effectively use Q1 bit to generate a clock that is divided by 4,

as shown in Figure 6.3.

Figure 6.3: Clock, Q0, and Q1 signals

Generally speaking, we can divide a clock by 2n if we take the output clock from the nth-bit of

an n-bit counter. A simple equation for finding the value of n to generate 1.5 Hz clock is as

follows,

50 MHz/2n ≈ 1.5 Hz

After calculation, n is found to be 25. Since the largest counter available in Xilinx library is

16-bit counter (e.g. CC16CE), we need to cascade two 16-bit counters. Cascading is done by

exploiting CEO (Chip Enable output) signal. CEO is at logic high when the counter reaches its

highest count (i.e. FFFF) as shown in Figure 6.4. CEO pin is connected to CE (Chip Enable) pin

on the next counter to activate the counter as shown in Figure 6.4. The two counters share

the same clock source. The 1.5 Hz clock signal is taken from the 9th output of the second 16-

bit counter. The 8th pin will provide a clock signal of 3 Hz and so on.


Page 3

Experiment 6

Figure 6.4: CEO signal of a 4-bit counter

Figure 6.5: 1 Hz frequency division circuit

3. Multiplexer

Multiplexer is a circuit that has 2n inputs and a single output. Only one of the 2n inputs is

passed to the single output based on the value of n-bit select inputs. The truth table and

graphic symbol of a 4-to-1 multiplexer is shown in Figure 6.6, where I0, I1, I2, and I3 are the

inputs, and S0 and S1 are the select lines. In part III, you will use the output of a 4-to-1

multiplexer to choose from four different frequencies (i.e. 1.5 Hz, 3 Hz, 6 Hz, and 12 Hz)

generated by the frequency division circuit. The output of the multiplexer will be connected

to one of board LEDs. To observe different frequencies, you will use two switches connected

to the input select lines to pass signals with different frequencies to the LED.

Inputs Output

S1S0 I3 I2 I1 I0 Out

00 X X X 0 0

00 X X X 1 1

01 X X 0 X 0

01 X X 1 X 1

10 X 0 X X 0

10 X 1 X X 1

11 0 X X X 0

11 1 X X X 1

Figure 6.6: Truth table and graphic symbol of 4x1 multiplexer

I0

S1

Out

I1

I2

I3

S0


Page 4

Experiment 6

Procedure

1. In part I, you will observe the FPGA board main clock signal using oscilloscope

2. In part II, you will build the frequency division circuit

3. In part III, you will observe the different frequency signals using a 4-to-1 multiplexer

Part I

Objective- To observe the FPGA board main clock signal using oscilloscope

1. Start ISE Design Suite and create new project

2. Create a new source of type Schematic, call it (Oscilloscope), and draw the circuit shown

in Figure 6.7

3. Choose BUF from the symbol list and place it on your schematic window

4. Place I/O markers properly and name it as shown

5. Start Plan Ahead software and assign site E12 to Clock and V14 (upper-most pin of

accessary header J20 as shown in Figure 6.8) to Output. Note: “output” is a reserved

word so make “O” capital.

6. Generate the Bit-file, and Program your board

7. Place the probe from your oscilloscope on the Output pin (V14) and ground of probe to

the GND of J20. Observe the clock signal output on your oscilloscope screen. You should

get a waveform with frequency of 50MHz on your oscilloscope screen

Figure 6.7: Circuit for Testing With Oscilloscope

Figure 6.8: Accessory Header J20 and Location of V14

Part II

Objective- To build a frequency division circuit

1. Create a new source of type Schematic, name it (OneHz), and draw the circuit shown in

Figure 6.5.

2. Choose CC16CE 16-bit counter and place two of them on your schematic window.

3. Place VCC, GND and I/O markers properly. Name the input marker to the first counter as

clock.

4. Wire the two counters as shown. Name the wire connecting the CEO pin of the first

counter to the CE pin of the second counter as CountEnable.

Prob

Ground

of Prob


Page 5

Experiment 6

5. The output of the last counter is a bus of 16-bits. Name the output markers with Q(15:0).

6. Start ISim. Apply a clock signal to clock input with a leading edge value of 0, trailing edge

value of 1 and Period of 20 ns (50 MHz).

7. Run the simulation and observe the wave signals on clock, countEnable and Q. You

should run the simulation for a long time (2s or more) to observe the change in pin Q9.

Verify that your circuit is correct.

8. Close ISim if your design entry generated the expected output wave signals.

9. Create a symbol of your frequency divider circuit, name it (OneHz), and save it (refer to

the lab guide for how to create a symbol).

Part III

Objective- To observe the different frequency signals using a 4-to-1 multiplexer

1. Create a new source of type Schematic, name it (MUX), and draw the circuit as in Figure

6.9

a. Choose M4_1E 4-to-1 multiplexer and place it on your schematic window

b. Find the symbol “OneHz” you created in part II and place it on your schematic

window

c. Connect VCC to the enable (E) pin of M4_1E. Place I/O markers properly and

name them as shown in Figure 6.9.

d. Extend a wire out from the output of the OneHz symbol. Note that the wire is

automatically widened. The wire is actually a bus.

e. To rename the bus, click on the bus at your schematic draw and then click on

Rename Selected Bus in the vertical toolbar. Click on Rename the branch then

type Q(15:0) in the New Base Name of Bus then click Apply then OK.

f. Double-click on the bus to make sure that the name is applied. If not then redo

step e.

2. To get different frequencies from the frequency division circuit (OneHz), you need to

properly choose the pin that gives the required frequency. For example, pin 9 will

provide frequency of 1.5 Hz. Pin 8 provides frequency of 3 Hz and so on. You need to

create Bus Tap in order to wire the output pins to the output bus of OneHz symbol as

follows:

a. Click on the Add Bus Tap icon in the vertical toolbar, or click Add->Bus Tap, set

the orientation to Right.

b. Click on the bus in your schematic draw once. The Selected Bus Name will be

Q(15:0)

c. Using the left and right arrows under Net Name, choose Q(9) one tap to the bus

as shown in the Figure 6.9.

d. The net name will be decremented automatically to Q(8). Place three more bus

taps below the first tap (you will place Q(8), Q(7), and Q(6)).

e. Connect each tap to the inputs lines of the M4_1E in proper order.

f. Click on Net Name in the vertical toolbar and choose Name the branch from

the menu to the left.

g. Using left and right arrows under Name to choose Q(9). Click on the first wire

you draw in step c to give the wire net name.

h. Similarly, name the rest of the wires Q(8), Q(7), and Q(6) as shown in the Figure

6.9.


Page 6

Experiment 6

i. Double-click on each wire to ensure that they are named correctly

3. Run the simulation for enough time. Apply different inputs to SW1 and SW0 and verify

that the output at LED0 is correct

4. Start PlanAhead and assign the board clock (E12) to your clock input. Connect LED0,

SW0, and SW1 to proper sites on your board

5. Generate the Bit-file, and Program your board

6. Verify the output on the LED on your board by toggling the input switches

7. Turn off your board and Close ISE design suite

Figure 6.9 The Final Circuit

Lab Report


this experiment as mentioned in the document. Also make a table as shown below and write

the proper values in it.

SW0 SW1 Bus Tap Frequency

0 0 Q( ) Hz

0 1 Q( ) Hz

1 0 Q( ) Hz

1 1 Q( ) Hz

Experiment 7: Synchronous and Asynchronous Counters

Page 1

Experiment 7

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Objectives


Learn the difference between synchronous and asynchronous counter reset

Learn how to use count-enable (CE) and count-enable-out (CEO) signals

Build synchronous / asynchronous Modulo-10

Build Modulo-6 and Modulo-12 counters

Build Modulo-60 counter

Build a (hours, minutes, seconds) timer

Learn about comparator circuit

Build a circuit to get a lower frequency of 1KHz and 1Hz from 50MHz

Learn about the clock without any gating

Use LCD to display the timer circuit output

Material Required


Spartan3AN FPGA board

CB4CE (4-bit counter with asynchronous clear), CB4RE (4-bit counter with synchronous

clear), COMP16 (16-bit comparator), constant and few gate symbols

LCD Verilog files provided by instructor


1. Synchronous clear and asynchronous clear

Some counters are provided with a “Clear” control input. With this capability,

the counter can be “cleared” (be put in the all 0s state) when the clear input is

activated.

There are two types of “Clear” inputs; Synchronous and Asynchronous.

When a Synchronous “Clear” input is activated, the “Clear-ing” action does not

take place immediately but rather “Clear-ing” is delayed till the arrival of the

next clock pulse (Clearing is synchronized with the clock signal).

Conversely, when an Asynchronous “Clear” input is activated, the “Clear-ing”

action is activated immediately without waiting for the next clock pulse

(Clearing is NOT synchronized with the clock signal).



Page 2

Experiment 7

2. Synchronous and Asynchronous Modulo-10 Counter

The CE input of a counter is a “Count Enable” signal that should be active for

the counter to count; otherwise the counter maintains its count without

change irrespective of the number of received clock pulses.

Modulo-10 counter (also called BCD counter) is a counter that has 10 possible

states; counting from 0 to 9 then back to 0.

A modulo-10 counter can be built using a 4-bit (modulo-16) binary counter.

To do this, the counter is cleared to its initial value 0000 after the counter

reaches a count of 9 (1001 in binary) and maintains this value for a full clock

period.

For counters with Synchronous “clear” input, this is achieved by detecting the

count 9 (1001 in binary) using an AND-gate. The output of this AND gate is

then used as the clear input to the Mod-16 binary counter. Once the count of

9 is detected, the clear input = 1 which clears the counter when the NEXT

clock pulse is received.

For counters with Asynchronous clear input, this is achieved by detecting the

count 10 (1010 in binary) using an AND-gate. The output of this AND gate is

then used as the clear input to the Mod-16 binary counter. Once the count of

TEN is detected, the clear input = 1 which clears the counter IMMEDIATELY.

4-bit cascadable binary counter with clock enable and synchronous clear

symbol (CB4RE) is used to design Mod10 synchronous clear counter. The

counter is cleared in the next clock cycle. Hence, state 10 will be active until

the next clock cycle as shown in Figure 1. The waveform is shown in Figure 2.

4-bit cascadable binary counter with clock enable and asynchronous clear

symbol (CB4CE) is used to design Mod10 asynchronous clear counter. The

counter is cleared once Q1 and Q3 are high as shown in Figure 3. The

waveform is shown in Figure 4.

CEO pin is used to signal when the counter reaches its maximum count.

CEO is active high when counter reaches count 9 in Synchronous clear

counter. In Asynchronous clear counter, CEO is active high when counter

reaches 10.

Figure 1: Synchronous clear Modulo-10 counter


Page 3

Experiment 7

Figure 2: Waveform of modulo-10 synchronous clear counter

Figure 3: Asynchronous clear Modulo-10 counter

Figure 4: Waveform of modulo-10 asynchronous clear counter

Figure 5: Synchronous clear Modulo-10 counter with manual and auto-reset


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Experiment 7

3. Modulo-6, Modulo-12, and Modulo-60 Counters

Similar to modulo-10 counter, modulo-6 and modulo-12 counters can be

built using modulo-16 counters by choosing the proper inputs of the AND

gate to clear the counter.

Modulo-60 counters can be built using cascaded modulo-10 (for the least

significant digit LSD) and modulo-6 (for the most significant digit MSD)

counters.

The Chip Enable Output (CEO) signal of the modulo-10 counter is connected

to the Count Enable (CE) pin of the modulo-6 counter. Note that the CEO is

ANDed with the main CE. Thus, the modulo-6 counter (MSD) digit is

incremented once every 10 counts of (LSD).

The CEO signal of modulo-60 counter is obtained by ANDing the CEO of

modulo-10 and CEO of modulo-6 counters, i.e. CEO is active high when MSD

is 5 and LSD is 9 (59).

The circuit diagram of the modulo-60 counter is shown in Figure 6.

Figure 6: Modulo-60 counter circuit diagram

4. Timer and LCD display

Using the developed modulo-60 and modulo-12 counters, you will build a

timer for hours, minutes, and seconds (HH:MM:SS).

You need to cascade two modulo-60 counters and one modulo-12 counter to

build the timer.

Using the provided LCD Verilog file, you need to instantiate the LCD symbol

provided in your Schematic to display the time on the board’s LCD display.

The LCD module has 20 data inputs that should receive the BCD digits of the

hours, minutes and seconds from the counters as shown in Figure 10.


Page 5

Experiment 7

5. 1Hz and 1 KHz pulse generator

The clock pins of all modules must be only connected to the FPGA board

system clock.

We need to build a 1 Hz (clock period of 1s) and a 1 KHz (clock period of 1

ms) pulse generator to enable the symbols.

This can be done using a 16-bit counter with clock enable and asynchronous

clear and a 16-bit comparator. The pulse is generated if the count reaches a

specific constant. The constant is a 16-bit number that corresponds to a

specific clock period.

The FPGA board system clock has a frequency of 50 MHz, clock period of

20ns. To derive a clock period of 1ms (1KHz Frequency), the constant must be

1ms/20ns = (50000)10 = (C350)16

Using the 1KHz pulse generator, 1Hz pulse generator can be built by dividing

the period by (1000)10 = (03E8)16 (since 1KHz = 1000Hz)

Figures 7 and 8 show the 1 KHz and 1 Hz pulse generators, respectively. Note

that the 16-bit counter in Figure 7 is clocked by the FPGA board system clock

and enable with Vcc. While the 16-bit counter in Figure 8 is also clocked by

the FPGA board system but enabled by the 1 KHz signal of Figure 7.

Figure 7: Generating a 1 KHz pulse

Figure 8: Generating a 1 Hz pulse


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Experiment 7

Procedure

The procedure in this lab is divided into four main parts:

1. In part I, you will build a 1Hz, and 1KHz pulse generator to be used as Enable

signal for the counters.

2. In part II, you will build and create symbols of modulo-10, modulo-6, and

modulo-12 counters.

3. In part III, you will build modulo-60 counter.

4. In part VI, you will build hours, minutes, and seconds timer and display time

on LCD in the form (HH:MM:SS).

Part I Objective- to build a 1Hz and 1 KHz pulse generator

1. Start ISE and create a new Project.

2. Add a new Schematic source and name it “OneKHz”.

3. Draw the circuit in Figure 7.

4. To add a constant, choose “constant” from the symbols library and place it in

the Schematic. Double click on the symbol to change the value of the

constant accordingly.

5. Create a symbol and name it “OneKHz”.

6. Repeat the same for Figure 8, create a symbol, and name it “OneHz”

7. Save these two symbols for later use (in later experiments as well).

Part II Objective- to build modulo-10, modulo-6, and modulo-12 counters

1. Add a new Schematic source and name it “Mod10”.

2. Draw the circuit in Figure 5.

3. Simulate the design and verify if it is correct.

4. Create a symbol of this design and name it “Mod10’.

5. Repeat steps 2-5 to draw (with necessary changes in the circuit) modulo-6

and modulo-12 counters. Create symbols for them and name them “Mod6”

and “Mod12”, respectively.

Part III Objective- to build and create symbol of modulo-60 counter

1. Add a new Schematic source and name it “Mod60”.

2. Draw the circuit as in Figure 6 using the created Mod6 and Mod10 in part II.

3. Create a symbol of this design and name it “Mod60”.

4. Simulate the design to verify if it is correct.

Part VI Objective- to build hours, minutes, seconds timer and display it at LCD


Page 7

Experiment 7

1. Add a new Schematic source and name it “Timer”.

2. Add two “Mod60” counters and one “Mod12” counter in your Schematic.

3. Add “OneKHz” symbol.

4. Connect the clock pins of all symbols to the system clock. Note: Only main

clock is allowed to be connected to the clock pins of each symbol.

5. Cascade the counters properly to build HH:MM:SS timer. The first Mod60

counter serves as second timer. The second Mod60 counter serves as minutes

timer. The Mod12 serves as hours timer.

6. Import the LCD_block verilog file provided to you by the instructor to your

project. Also import the .ucf file.

7. Create the symbol of LCD_Block and use it as shown in the Figure 10.

8. Add LCD_block symbol to your schematic and connect input pins probably -

H(3:0) is the hours, M(3:0) is LSB of minutes, M(7:4) is the MSB of minutes,

S(3:0) is the LSB of seconds, and S(7:4) is MSB of seconds.

9. Connect the Reset pin to the reset of all blocks.

10. Add proper I/O markers and give them the corrospnding names of the pins.

11. Use the .ucf file, add two commands lines; one for the system clock (E12) and

other for a push button for reset.

12. Generate the configuration-bit file and program your board.

13. Verify the timer on the LCD on your board.

Bonus: Replace the OneKHz symbol with OneHZ symbol and see the output.

Figure 10: Final diagram of hours, minutes, and seconds timer with LCD block

Lab Report


this experiment as mentioned in the document.

Experiment 8: Reaction Timer Part-1

Page 1

Experiment 8

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Objectives


Study of Flip-Flops

More on MSI parts: register, shift register, down counter

Use the datapath and control unit design method

Use of frequency dividers to count time units

Generate random numbers using Linear Feedback Shift Register (LFSR)

Material Required


Spartan3AN FPGA Board

OneKHz and OneHz signals from previous experiment


Reaction timer:

The reaction timer is a circuit that measures human response time to a given event.

We shall develop the reaction timer as a game where:

A player starts the game.

After a random delay, an LED will turn on.

As soon as the LED is on, the player responds by pushing a button.

The circuit measures the time between the LED turning on and the player’s

response.

The response time is displayed on the LCD with a message classifying the player’s

response as either: fast, medium or slow.

This design will be developed in four consecutive experiments. The first one will

generate the random time between the starting signal and the LED turning on. In

the second experiment, a circuit will be built to measures the player’s response

time. The third will integrate the two components with a control unit to coordinate

component activities. The fourth experiment will add an extra challenge.



Page 2

Experiment 8

In the fourth experiment, the circuit will randomly turn on one of four LEDs and the

user has to push a corresponding push button (or switch) out of four push buttons.

In addition to measuring the response time, the circuit will check if the pressed

button is the correct one corresponding to the LED that was turned on. Thus it

measures both human accuracy and speed.

Flip-flop:

A Flip-flop is a component that is capable of storing a single bit. It is an edge-

triggered device. That means it will save the input data when an edge is received

(an edge is a transition from 1 to 0 or 0 to 1). It has two types: positive edge-

triggered (saves the input data bit when a transition from 0 to 1 occurs) and

negative-edge-triggered (saves when a transition from 1 to 0 occurs). The signal

that controls when to save is called clock.

Flip-flops differ in types and input control signals. The one that will be used is the

positive edge-triggered D flip-flop. The basic D flip-flop has two inputs (clock and

D) and one output Q. The flip-flop stores the value at the D input when it receives a

positive clock edge (also known as rising edge). The stored data is maintained until

the next positive clock edge.

The flip-flop may have other control inputs. Three of these are discussed next.

Clear (CLR or reset): this control signal forces the flip-flop to store a 0 (Q = 0). It can

be active high (force Q to 0 when CLR is 1) or active low (force Q to 0 when CLR is

0). It can be synchronous (waits for next active edge to clear the flip-flop) or

asynchronous (clears immediately).

Preset (P): this control signal forces the flip-flop to store a 1 (Q = 1). It has the same

properties as clear (can be active high or active low, synchronous or asynchronous).

Enable (E or CE or EN): this control signal enables or disables the flip-flop operation.

If enable is inactive the flip-flop stored bit cannot be changed. Enable can be active

high or active low.

The following diagram shows a positive edge-triggered D flip-flop with an active

high asynchronous clear and active high enable together with its function table.

Inputs Q+ Output (after

positive clock edge)

CLR CE D C Q

1 X X X 0

0 0 X X No Change

0 1 D D

Table 1: Characteristics table of D-Flip Flop (FDCE)

Figure 1: D flip-flop with active high

asynchronous clear

is the positive edge of clock


Page 3

Experiment 8

Register:

A register consists of a number of D flip-flops with their control inputs connected

together but with independent data (D) inputs i.e. it is a multi-bit storage. A 4-bit

register is made of four D flip-flops with their corresponding controls connected

together. Thus the 4-bit register will have one clock, one clear, one CE (Chip

Enable), four D inputs and four Q outputs.

Figure 2: Symbol of 4-bit register

Shift Register:

A shift register is a register with special internal connection. The D input for a flip-

flop is connected to the Q output of the previous flip-flop. The first flip-flop takes

its input from an external input pin. If there is a 4-bit shift register and the input

sequence was (starting from right) 10010101, the output of shift register will be:

Clock cycle Serial input Q0 Q1 Q2 Q3

0 1 0 0 0 0

1 0 1 0 0 0

2 1 0 1 0 0

3 0 1 0 1 0

4 1 0 1 0 1

5 0 1 0 1 0

6 0 0 1 0 1

7 1 0 0 1 0

8 X 1 0 0 1

Figure 3: Internal connections of a 4-bit

register

Figure 4: Connection of a 4-bit shift register


Page 4

Experiment 8

Generating random numbers:

Random numbers can be generated using a component called Linear Feedback

Shift Register (LFSR). It is a shift register with some XOR or XNOR gates that modify

the bits as they traverse the shift register. Numbers generated by an LFSR are

pseudo random. An n-bit LFSR generates periodic sequences of maximum period

equal to 2n – 1. After the period is finished, the sequence will repeat itself. The

placement of XOR gates defines the period of the LFSR. An example of a maximal

period LFSR is shown in figure 5. The flip-flops used have an active high preset to

initialize the register to the 1111 state. For this LFSR 0000 is a jam case (cannot

move from that state).

Figure 5: A 4-bit LFSR with maximum period using flip-flops

If this LFSR is initialized to Q0Q1Q2Q3 = 1111, the output sequence will be:

Cycle Q3+ Q2+ Q1+ Q0+=

Q3⊕Q2 Value

1 1 1 1 1 15

2 1 1 1 0 14

3 1 1 0 0 12

4 1 0 0 0 8

5 0 0 0 1 1

6 0 0 1 0 2

7 0 1 0 0 4

8 1 0 0 1 9

9 0 0 1 1 3

10 0 1 1 0 6

11 1 1 0 1 13

12 1 0 1 0 10

13 0 1 0 1 5

14 1 0 1 1 11

15 0 1 1 1 7

16 1 1 1 1 15

Note:

Connect all

components

first and

leave

hanging line

for markers.

Add I/O

markers at

the end.

15 14

12

8

1

2

4 9 3

6

13

10

5

11

7

Figure 6: Sequence of the discussed LFSR

Peri

od

= 1

5 “

max

imal”

0 1 2 3


Page 5

Experiment 8

Procedure

The procedure in this lab is divided into three main parts:

1. Build a 5-bit LFSR to generate random numbers.

2. Use a down counter to capture the LFSR output and wait for that amount of

random time. Integrate part I of the reaction timer.

3. Test Reaction Timer Part I by turning on an LED after random delay.

Part I–Build a 5-bit LFSR 1. Start a new project.

2. Add a new schematic source and name it “LFSR”.

3. Draw a circuit similar to Figure 5. It should have 5 flip-flops and the XOR inputs

should be from Q1 and Q4. Output of XOR should be same as in Figure 5.

Answer the following question:

Q1. Why a 5-bit LFSR is better than 4-bit LFSR?

4. Simulate the circuit and verify the sequence is maximal (i.e., period = 31).

5. Create a symbol of the design and name it “LFSR”.

Part II a–Counting seconds using a down counter A down counter is a counter that counts in reverse order (e.g., a 2-bit down counter

will count 3,2,1,0,3,…).

1. Create a new schematic source and name it “part1” and add it to the project.

2. Use the part CB2CLED (2-Bit Loadable Cascadable Bidirectional Binary Counter with

Clock Enable and Asynchronous Clear). This counter can count up or down based on

a control signal.

3. Right–click the part and select symbol -> symbol info.

4. This page shows information about the part and how it works.

5. Note the control input that selects the counting direction properly. Connect this

input (to Gnd or Vcc) such that it functions as a down counter.

6. Simulate the design and verify the count.

7. In the simulation observe the zero (TC) output. It should be 1 whenever the count

reaches zero.

Part II b–Integrate part I of the reaction timer Part I of the reaction timer will take two bits from the LFSR (a random number from

0 to 3). Then, that random number is loaded in the down counter as its initial value.

The counter starts counting down from that number until it reaches zero at a rate of

one number every second. When the zero output becomes 1, the random time is

done.

1. Draw the circuit shown in Figure 7 in the schematic “part1” that you already have

added to the project. Answer the following questions:

Q2. What is the function of LD_rand (L) input?

Q3. Why the output Hz of OneHz is ANDed with EN_rand and connected to CE?

Q4. What block generates the HZ_EN signal?

Q5. LD_rand and EN_rand are going to be generated by a circuit that will be built

later. What is that circuit?

2. Create a schematic symbol of the design and name it “part1”.


Page 6

Experiment 8

Figure 7: Reaction Timer Part 1

Part III–Testing Part I of the circuit

In this part, “Part 1” of the reaction timer is going to be tested to make the LED turn

on after a random time.

1. Create a new schematic, name it “test_part1”, and add it to the project.

2. Add the LFSR, the OneKHz and part1 to the schematic. Also add a flip-flop.

3. Connect the parts as shown in the Figure 8.

Answer the following questions:

Q6. What is the use of flip-flop FDC?

Q7. Why an Inverter is used between LED and EN_rand?

4. Connect PB (Push Button) and reset to push buttons, LED to an LED and Clk to the

system clock “E12”.

5. When PB is pressed, LED will turn off and turn on again after random time.

6. Run your design on the board and have fun.

Figure 8: Testing “Part 1” of Reaction Timer

Lab Report


this experiment as mentioned in the document. Also answer the questions which are asked.


Page 1

Experiment 9

RReeaaccttiioonn TTiimmeerr

PPaarrtt 22––RReessppoonnssee TTiimmee

Objectives


More MSI parts: Saturating BCD counter

Comparing BCD numbers

Material Required



OneKHz and mod10 symbols from previous labs



This is the second experiment of the “Reaction Timer” series. In this experiment, a

circuit will be built to measure the player’s response time by using a saturating

counter. A saturating counter is the counter which counts up to its maximum value,

then stops, rather than going back to zero and starts again.

So a 3-digit BCD saturating counter will be built which counts from 0 to 999 and

enabled using the 1 KHz pulse generated from the previous labs. Therefore, the

counter is a millisecond timer that saturates at 999ms. A user response comparator

will also be built which determines how fast the user presses the USER push button

after the counter starts counting. A top-level block diagram is shown in Figure 1.

Figure 1: Top-level block diagram of Experiment 9


3-digit

saturating BCD

counter

User Response

Comparator

CE

Reset

Clk Q0

Q1

Q2

SLOW

MEDIUM

FAST


Page 2

Experiment 9

1. 3-digit BCD saturating counter:

It is based on the Mod10 counter built in experiment 7 with adding a new output

called EQ9. It is different from CEO because it does not depend on CE. CEO cannot

be used for that purpose since it will make a combinational loop.

The counter stores the current status of the count. If the counter reaches value 9, it

produces a signal “EQ9” using an AND gate. The counter is asynchronously reset if

the user presses a reset button.

To design a 3-digit BCD counter, 3 BCD counters are cascaded by enabling the next

stage BCD counter when the value of the previous counter reaches 9, i.e. CEO signal

is high.

The output of the 3-digit saturating BCD counter is connected to the LCD for

display.

2. User response comparator:

Response comparator is needed to compare the value of the counter against the

response time of the user.

Once the user presses the USER push button, the response comparator circuit

checks the value of the counter and evaluates the user response time.

Three signals are generated to categorize user response time as fast, medium, or

slow where:

1. Fast: if the user response time is less than 300 ms

2. Medium: if the user response time is greater than 300 ms but less than 600 ms

3. Slow: if the user response time is between 600 ms and 999 ms

Combinational logic can be designed to generate the three signals. Hint: two k-

maps will be enough (one for fast and one for medium or slow).

The input of the circuit is the MSD of the 3-digit saturating BCD counter.

The MSD will be stored in a 4-bit register with Chip Enable (CE) pin is connected to

the user (USR) push button.

Procedure

The procedure in this experiment is divided into four parts:

1. Build a 3-digit BCD saturating counter.

2. Build the response time circuit that determines if the user’s response is fast,

medium, or slow.

3. Integrate the components of Part2.

4. Test Part2 and show Results on the LCD.

Part I–Build a 3-digit BCD saturating counter 1. Start a new project.

2. Add a new Schematic source and name it “Mod10” or add the Mod10 schematic

from experiment 7.

3. Draw (or update) the circuit as in Figure 2, and answer the following questions:

Q1. What is the function of the EQ9 output?

Q2. What is the difference between the EQ9 and CEO?

4. Create a Schematic symbol and name it “Mod10”.

5. Connect 3 “Mod10” symbols as shown in Figure 3 to create a 3-digit BCD counter:


Page 3

Experiment 9

Q3. What will CE input of first Mod10 counter be connected to?

Q4. What are the inputs of the 3-input NAND gate? And what is its functionality?

Q5. How is each BCD counter enabled?

6. Simulate the design and verify the count.

Figure 2: Circuit diagram of a Mod10 (BCD) counter

Figure 3: Circuit diagram of 3-digit BCD counter

Part II– Build the response time circuit that determines if the user’s

response is fast, medium, or slow 1. Add a new Schematic source and name it “ResponseSpeed”.

2. The input is a 4-bit bus which will be connected to the MSD (Q2) from the 3-digit BCD

counter.

3. Derive the K-map for each of the following output signals:

a. Fast if the response time is less than 300ms

b. Slow if the response time is greater than 600ms

c. From the above two signals, generate the “medium” signal


Page 4

Experiment 9

4. Draw the circuit obtained from the k-maps in the schematic.

5. Create a Schematic symbol and name it “ResponseSpeed”.

6. Simulate the design and verify the output.

Note: For simulation, you will get an error for forcing the values of bus. Add Mod-10 counter that

was generated in Part I. Connect the Q input of ResponseSpeed to the Q output of the Mod-10

counter. Simulate it with proper clk and CE inputs. After simulation, remove Mod-10 counter.

Part III–Integrate the components of Part2 1. Add a new source and name it “Part2”.

2. Connect the “BCD_Sat_Cnt” and “ResponseSpeed” as shown in Figure 4. Answer the

following questions:

Q6. Why a 4-bit register is used before the response speed circuit?

Q7. Why only Q2 is used in ResponseSpeed?

Q8. Why is the 4-bit flip-flop CE pin is connected to USR push button?

3. Add a 4-bit flip-flop “FD4RE” symbol and connect it to Q3 of the BCD_Sat_Cnt.

4. Create a symbol of Part2.

Figure 4: Circuit diagram of Reaction Timer Part 2

Part IV–Test Part2 1. Add a new source and give it a name, this should be your top-module file.

2. Add LCD Verilog files provided for you to the project.

3. Create LCD_Block symbol from LCD_block_singleFile.v file.

4. Connect Part2 and LCD_Block properly according to the pins’ names, SYNRST

should also be connected to reset.

5. Use OneKHz symbol from experiment 7, to enable the 3-digit BCD counter.

6. Verify the circuit on your board.

Lab Report




Page 1

Experiment 10

RReeaaccttiioonn TTiimmeerr PPaarrtt 33––TThhee CCoonnttrrooll UUnniitt aanndd IInntteeggrraattiioonn

Objectives


States and finite state machines (FSM)

Design a control unit as an FSM

Integrate the design to a full reaction timer

Material Required



StatCAD software


The data path files from previous two experiments


Control Unit Circuit as FSM:

A finite-state machine (FSM) or simply a state machine is a mathematical model used to

design digital logic circuits. In general, a state machine is any device that stores the status

of something at a given time and can operate on input to change the status and/or cause

an action or output to take place for any given change. The machine is in only one state at

a time; the state it is in at any given time is called the current state. It can change from one

state to another when initiated by a triggering event or condition, this is called a

transition.

In this experiment, the circuit of control unit for reaction timer is required to build as FSM.

This FSM should control the whole circuit of reaction timer that you have built in the last

two labs. The easiest way is to first draw the state diagram for this FSM.

Procedure

The procedure in this lab is divided into two main parts:

I. Making the state diagram and generating the Verilog code. Adding it to the project

after creating symbol of it.



Page 2

Experiment 10

II. Integrating the circuits of last two experiments with the controller circuit/symbol

generated in the first part of this experiment.

Part I–Build the FSM (possibly by StateCAD) In this part of the experiment, the FSM control unit of the reaction timer circuit will be

made. But before making the state diagram, identify the needed circuit states, the FSM

inputs, and outputs.

There are 3 inputs to the FSM: Start, Zero and User:

Start is the signal which starts the operation of the reaction timer circuit.

Zero is a signal generated when the output of the down counter reaches zero.

User is the signal generated when the user pushes the button.

There are 6 outputs from the FSM: LD_rand, EN_rand, LED, EN_user_cnt, synrst and error:

LD_rand is the signal to load random number in the down counter.

EN_rand is the signal to start and enable the random delay counter to count.

LED is the signal to turn ON the LED.

EN_user_cnt is the signal to start and enable the counter to measure the time taken by

the user to push the button.

synrst is the synchronous reset for the BCD counters.

error is the output signal if the user pushes the button before the light turns ON.

1. Draw the state diagram of control unit of reaction timer circuit using the StatCAD

tool as shown in Figure 10.1. After completing the state diagram, right-click on the

white area of the screen, click “Configuration…” and remove check mark in front of

“Retain Output Values” under “Options”.

2. Generate the Verilog file of that and then import it in your project as “Add Source”,

then make the symbol of it as shown in Figure 10.2.

Figure 10.1 State diagram of reaction timer controller circuit.


Page 3

Experiment 10

3. Answer the following questions:

Q1. Write the function of each state?

Q2. Why synchronous reset is used to reset BCD counters not the asynchronous?

Q3. What is the use of AND and OR gate in the circuit of Figure 10.3?

Part II – Integrate the reaction timer In this part of the experiment, the circuits of last 2 experiments will be integrated with the

FSM control unit to build a complete reaction timer.

Make a new project with the name Exp 10.

Add new source as schematic.

Use the symbol of control unit and the symbols of other circuits that you have made

in the last 2 experiments (as part1 and part2) as shown in the Figure 10.3.

Add the LCD block and make the necessary additions in the ucf file for LCD display.

Use a push button for reset, another push button for start and a third push button

for the user (for response).

Use an LED that will turn on at a random time to see the user’s reaction/response.

Use another LED for showing error.

Push the start button, after random delay an LED will turn ON. The user has to push

the “user” button as soon as the LED turns ON. The time taken by the user after LED

turns ON will be displayed on the LCD display in milliseconds and also if he is Fast,

Medium or Slow. If the user pushed the button before the LED turn on, another LED

for error should turn ON.

Enjoy playing with it.

Figure 10.2 Symbol of reaction timer controller circuit.


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Experiment 10

Lab Report



Figure 10.3 Integration of Controller unit and the last two experiments.


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Experiment 11

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Objectives


Complete the final design of the reaction timer with extra challenge

Enhancement of Reaction Timer to 4 LED’s and 4 switches

Decoders, encoders and priority encoder

Design of a 4-to-2 priority encoder

Material Required



Experiment 10 files

LCD display block and other related files


Random LED Turning On

In this experiment, the reaction timer circuit will be extended to choose from four

different LED’s and turn on a single LED after random delay. Then the user must turn on

the corresponding switch within the time. The message “FAST”, “MEDIUM”, or “SLOW”

will be shown on the LCD according to his response. If the user turns on a wrong switch,

“WRONG” message will be displayed on the LCD.

The LED to be turned on is randomly chosen using any two bits of the LFSR, the bits in

LFSR that are left from Part1. The 2 bits are stored in a register that is enabled by the LED

signal from the control unit. The output of the register is connected to a 2x4 decoder to

turn on a single LED among four possible LEDs.

A decoder is a combinational circuit that expands the binary number to a larger number

of outputs. An n to 2n decoder has n inputs and 2n outputs. At any moment, the output

of the decoder represents the minterm formed by the input. E.g., in a 2 to 4 decoder, if

the input is 00 then only output 0 will be 1 and all other outputs will be 0.

Opposite to decoder, an encoder is a multi-input combinational logic circuit that

converts the logic level "1" data at its inputs into an equivalent binary code at its output.



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Experiment 11

One of the main disadvantages of standard encoders is that they can generate the

wrong output code when there is more than one input is present as logic level "1". One

simple way to overcome this problem is to "Prioritize" the level of each input pin and if

there was more than one input at logic level "1" the actual output code would only

correspond to the input with the highest designated priority. Then this type of digital

encoder is known as a Priority Encoder.

Priority Encoder with Valid Bit

A priority encoder is a circuit that compresses multiple binary inputs into smaller number

of outputs. E.g. 4 to 2 encoder takes 4-bits inputs and gives 2-bits output. Valid bit is

high when at least one input is high. The truth table and circuit diagram is shown in

Figure 1.

Figure 1: Truth table and circuit diagram of 4-to-2 priority encoder with valid bit

Priority encoder is needed to examine the user’s input. If the valid bit is high, it means

that the user turned on a switch. The output of the priority encoder is compared with the

two bits of the LFSR in order to determine if the user turned on the correct switch. The

output of the comparator is connected to the LCD to display proper message.

Procedure

The procedure in this lab is divided into three main parts:

I. Designing 4-to-2 priority encoder with valid bit for user’s input.

II. Turning on a single LED and comparing the user’s input with the LED circuits.

III. Integrating with the main circuit.

Part I–Designing a 4-to-2 priority encoder for user’s input

1. Open Expt. 10 project.

2. Add a new Schematic file and name it “Encoder”.

3. Draw the circuit in Figure 1 and create its symbol.


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Experiment 11

Part II–Building a circuit for turning on LED and comparing the

user’s input

1. Add a new Schematic file and name it “Part4”.

2. Draw the circuit in Figure 2, and create a symbol and name it “Part4”.

3. The register FD4CE is used to save the user’s response. It saves the encoded input

when the valid output of the decoder is high that is the first input of the AND

gate. After the value is saved it should not change until the next game begins.

Therefore, the valid output is stored with the value and used to disable the next

value from being saved.

4. Answer the following questions:

Q1. Why the inputs D2 and D3 of FD4CE are connected to ground?

Q2. When EQ output of Comp2 will be “1”?

Q3. Will it make any difference if the outputs of two registers are swapped

which are connected to A0, A1 and B0, B1 inputs of comparator?

Q4. What is the use of AND gate and OR gate in Figure 2?

Figure 2: Circuit to choose LED and compare the user's input

Part III–Integrating with the main circuit

1. Add “Part4” symbol.

2. Connect D0 and D1 to any 2 unconnected bits of the LFSR.

3. Connect the LED pin of the control unit to the LED_EN pin of Part4.

4. Connect VALID pin to the USR net, note that you need to remove the user I/O

marker from the schematic and from the ucf file.


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Experiment 11

5. Connect EQ pin of Part4 to EQ pin of the LCD_block.

6. Connect four switches to SW0-SW3 and assign proper site locations.

7. Connect four LEDs to LED0-LED3 and assign proper site locations.

8. Enjoy playing it.

Figure 3: Complete Circuit of Reaction Timer

Lab Report

Print the lab report format and write a complete lab report on this printed document

about this experiment as mentioned in the document. Also answer the questions which

are asked.

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1

COE 203: Digital Logic Lab

Experiment # ______

Experiment Title: ______________________________

Section: ______ Team: Name:____________________________ ID#:_________________

Name:____________________________ ID#:_________________

Introduction: <Don't copy-paste from the lab manual>

• List the objectives of the experiment and the circuit to be designed to achieve each objective.

Circuit: /65 Report: /25 Neatness: /5

Teamwork: /5

Total: /100

2 Design:

Describe the following: 1. The design of your circuit. 2. The procedures followed in the design. 3. Mention if there were any design alternatives? If yes, which of these alternatives

did you adopt? Justify your choice.

3 Testing & Troubleshooting: Describe the procedures followed in testing your design. Don't simply write "we tried it and it worked,"

• The test configuration

but instead describe

• Applied test data • Output verification <Discuss how did you conclude that it was working correctly>

For each problem faced, describe:

• The problem • Cause of the problem • How did you troubleshoot the problem • Describe your solution and whether it has fixed the problem.

4 Team Work:

• Task division (who did what) • Team discussion

Experiment Evaluation: Comments/Justification Usefulness (good/ok/useless)

Time/duration (mins)/(Long/reasonable/short)

Suggest modifications/improvements

5 Conclusion: In your own words:

• Summarize the work accomplished. • Summarize what have you learned from this experiment. Attachments (give list): • Simulation results (Images / Tabulations).

AAppppeennddiixx BB

1

COE 203: Digital Logic Lab

Experiment # ______

Experiment Title: ______________________________

Section: ______ Team: Name:____________________________ ID#:_________________

Name:____________________________ ID#:_________________

Introduction: <Don't copy-paste from the lab manual>

• List the objectives of the experiment and the circuit to be designed to achieve each objective.

Circuit: /65 Report: /25 Neatness: /5

Teamwork: /5

Total: /100

2 Design:

Describe the following: 1. The design of your circuit. 2. The procedures followed in the design. 3. Mention if there were any design alternatives? If yes, which of these alternatives

did you adopt? Justify your choice.

3 Testing & Troubleshooting: Describe the procedures followed in testing your design. Don't simply write "we tried it and it worked,"

• The test configuration

but instead describe

• Applied test data • Output verification <Discuss how did you conclude that it was working correctly>

For each problem faced, describe:

• The problem • Cause of the problem • How did you troubleshoot the problem • Describe your solution and whether it has fixed the problem.

4 Answer the questions which are asked in the lab manual for this experiment. Write the question first and then the answer.

5 Team Work:

• Task division (who did what) • Team discussion

Experiment Evaluation: Comments/Justification Usefulness (good/ok/useless)

Time/duration (mins)/(Long/reasonable/short)

Suggest modifications/improvements

6 Conclusion: In your own words:

• Summarize the work accomplished. • Summarize what have you learned from this experiment. Attachments (give list): • Simulation results (Images / Tabulations).

Documents

King Fahd University of Petroleum & Minerals - KFUPMmasud/text/COE203_LAB_MANUAL.pdf · King Fahd University of Petroleum & Minerals ... LAB Manual: COE 203: ... (schematic capture,