ITRS Design ITWG 2012 1 Design + System Drivers Update Design ITWG ITRS Public Conference Hsinchu, 5 Dec 2012

ITRS Design ITWG 2012 1

Design + System Drivers Update

Design ITWG

ITRS Public ConferenceHsinchu, 5 Dec 2012


MTMroadmap

RF+AMS Driver continued

UpdatedDrivers(MPU, SoC,…)

Upgraded DFM, SL, verification sections

Power design technology roadmap

Consumer Stationary,Portable,Networking Drivers

Past Trajectory (2004-2011)

1. Increasingly quantitative roadmap2. Increasingly complete driver set3. Increasing MTM content

2

2004

2005

2006

2007

ExploreDesign metrics

Design Technology metrics

Revised Design metrics

Revised Design Technology Metrics

ConsumerPortableDriver

Consumer Stationary, PortableDrivers

Consumer Stationary,Portable,Networking Drivers

More Than Moore (MTM)analysis + iNEMI

Driver study

System DriversChapter

DesignChapter

2008

Revised Design MetricsDFM extension

Updated Consumer Stationary,Portable,and Networking Drivers

MTM extension+ iNEMI+ SW !!

2009

AdditionalDesign MetricsDFM ExtensionSystem level extension

Updated Consumer Stationary,Portable architecture,and Networking Drivers

MTM extension+ iNEMI synch+ SW !!

MTMRF+AMS Driver start

UpdatedConsumer SOC and MPU Drivers

Upgraded RF+AMS section

2010

2011


Work Toward 2013 and BeyondDesign Chapter

• Version 2 of the Power-Aware Design Technology roadmap• Version 2 of the 3D IC design technology roadmap• Design technology for More Than Moore fabrics (SW, AMS/RF, MEMS)• Updates of LCP, DFT, Design Verification, Design for Resilience• Design of on-chip memory hits the wall at 16nm HP

System Drivers Chapter• Rethinking the MPU Driver: Core + LLC + “uncore”; microserver class• Revising the SOC-Consumer Portable Driver• Elimination of SOC-Networking, SOC-Consumer Stationary drivers ? • Update of Embedded Memory• Continue development of AMS/RF “sub-driver” of SOC-CP Driver

Cross-TWG• CTSG: node timing pull-in, A-factor updates for FinFET, vertical devices• How will FinFET, UTBB SOI timing change PPA projections?• Renewal of the PIDS HP, LP roadmaps (compact modeling interaction) • 3D effort with other TWGs







Design Cost Roadmap

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2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026

ITRS 2011 Cost Chart

Total HW Engineering Costs + EDA Tool Costs Total SW Engineering Costs + ESDA Tool Costs

Total HW Engineering Costs + EDA Tool Costs (smoothed) Total SW Engineering Costs + ESDA Tool Costs (smoothed)

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Design Power Roadmap


Low-Power Design Technology Roadmap

NEW: approximate computing, adaptivity, power gating replacement, dark silicon, extreme heterogeneity, …


NEW in Low-Power Design Tech RoadmapApproximate Computing

• Variable-accuracy computing (e.g., flexibly from 64b 16b)• 4D computing: reconfiguration on the fly• AVS ? (e.g., part of DVFS) Margin reduction?

Adaptivity•Recapture overdesign from wearout, variation marginsPower Gating Replacement

• HVT device as power switch hits headroom, area wall ?Dark Silicon

• “normally-off computing” = “extreme power gating”


“Dark Silicon” Analysis in 2001 ITRS• Power management gap amount of (switched)

logic content in an SOC goes to zero• Challenge: keeping the chip value above zero

Today: turn on only 2-6% of logic on SOC !


NEW in Low-Power Design Tech RoadmapApproximate Computing

• Variable-accuracy computing (e.g., flexibly from 64b 16b)• 4D computing: reconfiguration on the fly• AVS ? (e.g., part of DVFS) Margin reduction?

Adaptivity•Recapture overdesign from wearout, variation marginsPower Gating Replacement

• HVT device as power switch hits headroom, area wall ?Dark Silicon

• “normally-off computing” = “extreme power gating”Extreme Heterogeneity• “coprocessor-dominated architectures”

• (pervasive heterogeneity; energy-efficiency from specialization; HW accelerators)

• “10 x 10”, “13 dwarves”, …• Intel “accelerators for MPU” vs. Tensilica (or, GPUs,

xPUs)


Design Tech for More Than Moore Fabrics

• Key areas: SW, AMS/RF, MEMS, 3D / novel packaging

• Current design technology still insufficient; must broaden beyond current ideas

• New 3D / TSV design flows• New multi-physics modeling, simulation, analysis tools

• Example: thermal / mechanical analysis (base station)

• Example: MEMS + electrical analysis (mobile gaming)

• Example: sensors + signal processing (industrial, medical)

• Example: software + HW simulation (data center network)


Memory as a Key Factor in Future DT

Figure DESN12 Possible Variability Abstraction Levels

PhysicalPhysical

DeviceDevice

GateGate

ChipChip

Bit CellBit Cell

CircuitCircuit ArrayArray


Memory as a Key Factor in Future DT

Figure DESN8 Variability-Induced Failure Rates for Three Canonical Circuit Types


Memory Design Hits The Wall• SRAM hits a brick wall at ~16nm M1 HP

• Area overhead: discrete fin sizing to meet stability targets• Vccmin(SRAM) > Vddmin(logic) due to variability need assist

structures, 8T, or 10T structures for 20nm and beyond • Increased leakage due to increased Vccmin(SRAM) and Vt tradeoffs

• eDRAM, L3 (SRAM), L2 (SRAM) subsystem replacements• STT-RAM – density, non-volatility (~low leakage)• FLASH RRAM• Exploiting 3D integration (monolithic, TSV) schemes

• Logic, register files, L1• Power gating strategies• Backup strategies for retention (transfering data to STT-RAM before

power-off)• Implications for memory hierarchy, architecture, design

• Different sizing of memory subsystems to reflect the energy/latency tradeoffs

• Multi-physics models to analyze Vccmin(SRAM)• Exploiting nonvolatility and fine-grain power gating in logic circuits







Changes to MPU Model

Item Current 2011 model

Proposed 2013 model

Die area 140mm2 (CP), 260mm2 (HP)

140mm2 (CP), 260mm2 (HP)

Area ratio Core :: 1 Core : LLC : UnCore :: 1: 1: 1

LLC NA 12MB (2011) + 1.4x every tech node[Borkar10, Borkar07]

UnCore NA Uncore Scaling

SRAM A-factor (USRAM)

60F2 (6T), 84F2 (8T) (bulk)

60F2 (6T), 84F2 (8T) (bulk, FinFET)40F2 (6T), 56F2 (8T) (high-density FinFET) ***

* CP – Cost-Performance; HP – High Performance** L2$ and L1$ is per core


“Uncore” (increasing portion of MPU) consists of:– Memory controller(s)

– Graphics and display controller(s)

– I/O and bus interface controller(s)

Updated MPU Model: UnCore Scaling

Item Proposed model

Memory controller N/2 (CP), N (HP); N = # cores[Borkar07, Borkar11, 80-core, IVB]

Graphics and Display controller 2x every tech node[NHM, SNB, NVIDIA]

I/O and bus interface controller N/6[SNB, IVB]

Logic (# transistors) growth Same as core

Logic density Same as core

SRAM (# bitcells) growth 512MB * # GPU-Cores[IVB, NVIDIA]

SRAM density Same as core


New Drivers Catching Up to “Old” Ones ?

1. “SoC-ification” of Drivers brings similarities2. Need to isolate the parameters driven by each (and only) driver


New Drivers Replacing “Old” Ones ?

1. Potential future system driver list (Markets dimension)a) High performance computing MPU – “Office/Server”b) Mobile (Application) MPU – “Consumer Portable”c) Low power computing MPU – “Microserver”


SoC MPU Convergence: MicroServers ?

• Observation: “mobile” computing SoCs competing in server space

• Beginning to be used in data centers and cloud computing

• Extreme core efficiency (active power < 4W, sleep power < 0.5W)

• #Cores, frequency scaling similar to conventional MPUs

• Microserver product class (Calxeda, Marvell, Intel, …)

re-examine the MPU model – or possibly create a new driver !

• Clock frequency growing at 1.5X every 2 years

• Number of cores growing at 2X every 4 years

• Networking-like SoC scaling: off-chip latency, accelerators, L3 cache

• Power budget under 4W per core (HPC example)

• Off-chip bandwidth as high as 200+ Gbps


A&DNetwork Consumer/Mobile

Office/Server

Medical Automotive ConsumerStationary

MPU

PE/DSP

AMS

Memory

Fabrics

Markets

System Drivers – So Many ?

1. Fabs will be filled primarily by 2-3 major applications


A&DNetwork Consumer/Mobile

Office/Server

Medical Automotive ConsumerStationary

MPU

PE/DSP

AMS

Memory

Fabrics

Markets

System Drivers – So Many ?

1. Fabs will be filled primarily by 2-3 major applications2. Drivers will follow suit – applications drive technology


Evolution of System Drivers Inventory

1. Upcoming years may see a smaller list of key Drivers2. As fabs consolidate, applications and drivers do so as well3. All remaining applications will ride on existing technology curve

System Driver (Market based) Technology Parameters Driven Potential action

High performance (computing) MPU

Frequency, number of cores, memory architecture

Keep

Mobile / consumer MPU Leakage power efficiency Keep

Low power computing MPU “Microserver”

Operating power efficiency Introduce?

Networking switch Number of I/Os / total I/O BW Keep?

Various fabrics (memory, AMS)

Various fabric-specific parameters

Keep

Networking MPU Number of cores, I/O BW Keep??


Qualitative changes in SoC-CP– High resolution, large screen size video interface require high performance GPU– Cloud-based service over wireless connection eliminates dedicated PEs for speech,

character and image recognition, dictionary, etc.

SoC-CP model– Current model: CPU + PE + Peripheral (+ RF, AMS)

– Next model: CPU + GPU + Logic Block + IO Peripheral

+ Baseband

(+ RF, AMS)

SOC-CP Model Revision

2D/3D graphics

Audio codec, Video codec,

Security

Multi-band multi-protocol SDR

DRAM-IF, USB, MIPI, HDMI, LVDS…


More Than Moore – AMS/RF “Subdriver”

Several emphases in DT, DFT: System verification, Hetero systems

Plan: paste high-level block model from AMS/RF -- “core model”

– Hope to obtain model from additional groups, market analysis

– E.G. WiFi/GPS/cellular/BT/NFC front-end blocks, tuner/demodulator

blocks







Ongoing for 2013 revision– Initial draft models developed in April 2012

Many issues to work through– Gridded layout with device grid, metal grid alignment– Dummy poly isolation– Unimportant design rules become important – e.g., gate contact to

active contact spacing– SRAM devices have integral sizing, no Vt control except with Lgate

biasing challenge to maintaining SRAM A-Factor– Current densities and resistivity CD (width) scaling of VDD, VSS traces– Comprehension of wiring loads in future designs– Specs for high-performance, low-power cell libraries

A-Factor Updates (e.g., FinFET)


Device Model / PIDS interaction

• Agreed to only one low power device in the roadmap

• Removed LOP device flavor from 3 to 2 devices

• Still questioning how much CD variation can be tolerated

• Should Design content change as we move toward 450 mm ?

• Should Design care about node definitions ?

• (foundry names vs. ITRS)


• Observation: 14 years to get beyond-CMOS idea to products• ITRS groups must start to think about and act on beyond-2020

devices and their use in design • (“technology” by itself is not a complete solution)

• What will be the earliest insertions into which products?• MRAM replaces SRAM• 3D with vertical nanowires (7nm) bring BEOL interfacing

challenge (and: P, N in different vs. same layers?)• Spintronics

• Demands Design ITWG collaboration with PIDS, Litho, Interconnect, ERD/ERM – and expanding the scope of ITRS

Beyond 2020


1. Design technology continues on roadmap of low-power techniques

2. Design ITWG still clarifying impact of new devices (FinFET A-factor)

3. Design technology for 3D continues to spread across chapter

4. Design technology for resilience a fundamental portion of DFM

5. More Than Moore fabrics will require increasingly specialized DT

6. Memory an increasingly important factor for design technology

7. Still pushing to integrate AMS/RF on SoC/SiP despite 3D prospects

8. System Drivers: SoC-CP revision – and will soaring applications (DTV,

microservers) overhaul the driver list ?

9. ITRS groups must think about Beyond-CMOS based products and

insertion points

Summary: 2012 Design / SysDrivers Messages


THANK YOU


Systems

ICs

System – Device Domain Space

Chip level System level

Techrequirements

Marketrequirements

System DemandWill drive device demand

Documents

ITRS Design ITWG 2012 1 Design + System Drivers Update Design ITWG ITRS Public Conference Hsinchu, 5 Dec 2012