IOS-484 User's Manual - Acromag | Embedded Computing ... · IOS-484 I/O Server Module User’s Manual Counter Timer Module ... number of programming environments including Visual

IOS-484 Counter Timer Module

USER’S MANUAL

ACROMAG INCORPORATED Tel: (248) 295-0310

30765 South Wixom Road Fax: (248) 624-9234

P.O. BOX 437

Wixom, MI 48393-7037 U.S.A.

[email protected] Copyright 2009-2011, Acromag, Inc., Printed in the USA.

Data and specifications are subject to change without notice. 8500-850-B11C007

IOS-484 I/O Server Module User’s Manual Counter Timer Module __________________________________________________________________

_________________________________________________________________________________________ Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:[email protected] http://www.acromag.com

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IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power, wiring, component, sensor, or software failure in the design of any type of control or monitoring system. This is very important where property loss or human life is involved. It is important that you perform satisfactory overall system design and it is agreed between you and Acromag, that this is your responsibility.

1.0 General Information

KEY IOS-484 COUNTER/TIMER FEATURES............ 4 IOS MODULE Win32 DRIVER SOFTWARE………… 5 IOS MODULE LINUX SOFTWARE…………………… 5

2.0 PREPARATION FOR USE

UNPACKING AND INSPECTION...…………………... 6 BOARD CONFIGURATION..........................………... 6 CONNECTORS........……………………………………. 6

IOS Field I/O Connector (P2)…....…………... 6 I/O Noise and Grounding Considerations....... 8

3.0 PROGRAMMING INFORMATION

IOS IDENTIFICATION SPACE.....…….……………… 9 MEMORY MAP..............................................………... 10

Board Control Register..................................... 12 Interrupt Status/Clear Register........………….. 12 Counter Trigger Register.................................. 13 Counter Stop Register...……………….……….. 14 Counter Read Back Register....………………... 14 Counter Constant A Register.………………..... 14 Counter Constant B Register............................ 14 Digital Input Register……….............................. 15 Digital Output Register………........................... 15 Interrupt Vector Register………........................ 15

COUNTER CONTROL REGISTER............................. 16 Quadrature Position Measurement…............... 17 Pulse Width Modulation......……...……...……... 20 Watchdog Timer Operation.……………...…….. 22 Event Counting Operation..........................…... 24 Frequency Measurement Operation................. 26 Input Pulse Width Measurement………………. 28 Input Period Measurement.…………………….. 30 One-Shot Pulse Mode.........…………………….. 32

TABLE OF CONTENTS

The information of this manual may change without notice. Acromag makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Further, Acromag assumes no responsibility for any errors that may appear in this manual and makes no commitment to update, or keep current, the information contained in this manual. No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag, Inc.

IOS-484 I/O Server Module User’s Manual Counter Timer Module ___________________________________________________________________


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PROGRAMMING EXAMPLES………………………… 34 Quadrature Position Measurement Example.. 34 Pulse Width Modulation Example....…...……... 35 Watchdog Timer Operation Example............... 36 Event Counting Operation Example................. 38 Frequency Measurement Operation Example. 39 Input Pulse Width Measurement Example....... 40 Input Period Measurement Example................ 42 One-Shot Pulse Mode Example........................ 43

4.0 THEORY OF OPERATION

FIELD INPUT/OUTPUT SIGNALS…...……………….. 46

Counter/Timers…………………...........………... 46 Digital I/O…………………….………………..…… 46

5.0 SERVICE AND REPAIR

SERVICE AND REPAIR ASSISTANCE...…………... 47 PRELIMINARY SERVICE PROCEDURE...………….. 47 WHERE TO GET HELP.............................................. 47

6.0 SPECIFICATIONS

PHYSICAL.................................................................. 48 ENVIRONMENTAL....…….…………………………….. 48 COUNTER/TIMERS……...............................…….….. 49 DIGITAL I/O……………………………………………… 50

DRAWINGS

IOS-484 BLOCK DIAGRAM.........….….... 51 RS485 I/O CONNECTIONS………………. 52

Trademarks are the property of their respective owners.

TABLE OF CONTENTS



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The I/O Server Module (IOS) Series IOS-484 module provides support

for five independent 16-bit multifunction counter/timers. Each counter/timer can be configured for quadrature position measurement, pulse width modulated output, watchdog timer, event counter, frequency measurement, pulse width measurement, period measurement, or one shot pulse output.

Important Note: The following IOS model are accessories to the IOS Server Models: IOS-7200, IOS-7200-WIN, IOS-7400, and IOS-7400-WIN; which are cULus Listed. This equipment is suitable for use in Class I, Division 2, Groups A, B, C, and D or non-hazardous locations only.

MODEL Counters I/O Type OPERATING TEMPERATURE RANGE

IOS-484 5 16-bit RS485/RS422 -40C to +85C

TTL/Differential I/O – The IOS-484 model has only RS485/RS422 I/O available. Mixed TTL and RS485/RS422 I/O are available on the IOS-483. The IOS-482 Counter/Timer I/O is available as TTL only.

Quadrature Position Measurement – Three input signals can be used to determine bi-directional motion. The sequence of logic high pulses for two input signals, A and B, indicate direction and a third signal (index) is used to initialize the counter. X1, X2, and X4 decoding is also implemented. X1 decoding executes one count per duty cycle of the A and B signals, while X2, and X4 execute two and four counts per duty cycle, respectively.

Pulse Width Modulation – Each counter can be programmed for pulse width modulation. The duration of the logic high and low levels of the output signal can be independently controlled. An external gate signal can also be used to start/stop generation of the output signal.

Watchdog Timer – Each counter can be configured as a countdown timer for implementation as a watchdog timer. A gate-off signal is available for use to stop the count down operation. Interrupt generation upon a countdown to zero condition is available.

Event Counter – Each counter can be configured to count input pulses or events. A gate-off signal is provided to control count-up or count down with each event. Interrupt generation upon programmed count condition is available.

Frequency Measurement – Each counter can be configured to count how many active edges are received during a period defined by an external count enable signal. An interrupt can be generated upon measurement complete.

Conduction Cooled Module - I/O modules employ advanced thermal technologies. A thermal pad and module cover wicks heat away from the module and transfers the energy to a heat spreading friction plate. Heat moves to the enclosure walls where it is dissipated by the external cooling fins.

1.0 GENERAL INFORMATION

Table 1.1: The IOS-484 module temperature range

KEY IOS-484 COUNTER/TIMER FEATURES



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Pulse-Width or Period Measurement – Each counter can be configured to measure pulse-width or waveform period. In addition, an interrupt can be generated upon measurement complete.

One-Shot and Repetitive One-Shot – A one-shot pulse waveform may also be generated by each counter. The duration of the pulse and the delay until the pulse goes active is user programmable. A repetitive one-shot can be initiated with repetitive trigger pulses.

Programmable Interface Polarity – The polarities of the counter’s external trigger, input, and output pins are programmable for active high or low operation.

Internal or External Triggering – A software or hardware trigger is selectable to initiate quadrature position measurement, pulse width modulation, watchdog countdown, event counting, frequency measurement, pulse-width measurement, period measurement, or one shot.

Digital I/O – The IOS-484 has 3 RS485/RS422 outputs and 1 RS485/RS422 input available for use.

Acromag provides a software product (sold separately) to facilitate the development of Windows Embedded Standard applications interfacing with I/O Server Modules installed on Acromag Industrial I/O Server systems. This software (Model IOSSW-DEV-WIN) consists of a low-level driver and Windows 32 Dynamic Link Libraries (DLLS) that are compatible with a number of programming environments including Visual C++, Visual Basic.NET, Borland C++ Builder and others. The DLL functions provide a high-level interface to the IOS carriers and modules eliminating the need to perform low-level reads/writes of registers, and the writing of interrupt handlers.

Acromag provides a software product (sold separately) consisting of

Linux software. This software (Model IOSSW-API-LNX) is composed of Linux libraries designed to support applications accessing I/O Server

Modules installed on Acromag Industrial I/O Server systems The software is implemented as a library of ―C‖ functions which link with existing user code

KEY IOS-484 COUNTER/TIMER FEATURES

IOS MODULE Win32 DRIVER SOFTWARE

IOS MODULE LINUX SOFTWARE

2.0 PREPARATION FOR USE



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Upon receipt of this product, inspect the shipping carton for evidence of mishandling during transit. If the shipping carton is badly damaged or water stained, request that the carrier's agent be present when the carton is opened. If the carrier's agent is absent when the carton is opened and the contents of the carton are damaged, keep the carton and packing material for the agent's inspection.

For repairs to a product damaged in shipment, refer to the Acromag

Service Policy to obtain return instructions. It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped. This board is physically protected with packing material and electrically protected with an anti-static bag during shipment. However, it is recommended that the board be visually inspected for evidence of mishandling prior to applying power.

Power should be removed from the board when installing IOS modules,

cables, termination panels, and field wiring. Refer to the following discussion for configuration and assembly instructions. Model IOS-484 Counter/Timer Boards have no jumpers or switches to configure—all configuration is through software commands.

P2 provides the field I/O interface connector for mating IOS modules to the carrier board. P2 is a 50-pin female receptacle header (AMP 173279-3 or equivalent) which mates to the male connector of the carrier board (AMP 173280-3 or equivalent). This provides excellent connection integrity and utilizes gold-plating in the mating area. The field and logic side connectors are keyed to avoid incorrect assembly.

P2 pin assignments are unique to each IOS model (see Table 2.1) and normally correspond to the pin numbers of the field-I/O interface connector on the carrier board (you should verify this for your carrier board).

UNPACKING AND INSPECTION

WARNING: This board utilizes static sensitive components and should only be handled at a static-safe workstation.

BOARD CONFIGURATION

CONNECTORS IOS Field I/O Connector (P2)



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Pin Description

Pin Number

Pin Description

Pin Number

RS485/RS422

In1_A+ 1 In4_B- 26

In1_A- 2 In5_B+ 27

In2_A+ 3 In5_B- 28

In2_A- 4 In1_C+ 29

In3_A+ 5 In1_C- 30

In3_A- 6 In2_C+ 31

In4_A+ 7 In2_C- 32

In4_A- 8 In3_C+ 33

In5_A+ 9 In3_C- 34

In5_A- 10 In4_C+ 35

In1_B+ 11 In4_C- 36

In1_B- 12 In5_C+ 37

In2_B+ 13 In5_C- 38

In2_B- 14 DIn1+ 39

In3_B+ 15 DIn1- 40

In3_B- 16 Out5+ 41

Out1+ 17 Out5- 42

Out1- 18 DOut1+ 43

Out2+ 19 DOut1-

44

Out2- 20 DOut2+ 45

Out3+ 21 DOut2-

46

Out3- 22 DOut3+ 47

Out4+ 23 DOut3-

48

Out4- 24 D.N.C. 1

49

In4_B+ 25 GND

50

Table 2.1: IOS-484 Field I/O Pin Connections The IOS-484 has 5 RS485/RS422 16-bit counters available. Additionally, it has 1 RS485 Digital Input and 3 RS485 Digital Outputs. The Digital I/O’s are emphasized in bold italics.

1. Do Not Connect: Pin has direct connection to FPGA. Reserved for programming purposes. (TDI#) Pin has active pull-up.



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The IOS-484 is non-isolated between the logic and field I/O grounds since output common is electrically connected to the IOS module ground. Consequently, the field I/O connections are not isolated from the carrier board and backplane. Two ounce copper ground plane foil has been employed in the design of this model to help minimize the effects of ground bounce, impedance drops, and switching transients. However, care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections.

To minimize high levels of EMI the signal ground connection at the field

I/O port (pin 50) should be used to provide a path for induced common-mode noise and currents. The ground path provides a low-impedance path to reduce emissions.

EIA RS485/RS422 communication distances are generally limited to less

than 4000 feet. To minimize transmission-line problems, all nodes connected to the cable must use minimum stub length connections. The optimal configuration for the RS485/RS422 bus is a daisy-chain connection from node 1 to node 2 to node 3 to node n. The bus must form a single continuous path, and the nodes in the middle of the bus must not be at the ends of long branches, spokes, or stubs. See RS485 I/O Connections for example connection and termination practices.

Transmission line signal reflections can be minimized with proper

termination. The EIA RS485/RS422 standard allows up to 32 driver/receivers to be connected to a single bus. Termination resistors should only be used at the two extreme ends of the bus and not at each of the nodes of the bus. Termination resistors are not provided on the IOS-484. They can be added to the field wiring as near to the IOS module as possible.

CONNECTORS

I/O Noise and Grounding Considerations



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This Section provides the specific information necessary to program and operate the IOS-484 module.

Each IOS module contains identification (ID) information that resides in

the ID space per the IOS module specification. This area of memory contains 32 bytes of information at most. Both fixed and variable information may be present within the ID space. Fixed information includes the "IOS" identifier, model number, and manufacturer's identification codes. Variable information includes unique information required for the module. The IOS-484 ID space does not contain any variable (e.g. unique calibration) information. ID space bytes are addressed using only the odd addresses in a 64 byte block (on the ―Big Endian‖ VMEbus). Even addresses are used on the ―Little Endian‖ PC ISA or PCI buses.

The IOS-484 ID Space is shown in Table 3.1. Note that the base-

address for the IOS module ID space (see your carrier board instructions) must be added to the addresses shown to properly access the ID information. Execution of an ID Space Read operation requires 0 wait states.

Hex Offset From ID Base

Address

Numeric Value (Hex)

Field Description

00 49

02 50

04 41

06 48

08 A3 Acromag ID Code

0A 47 IOS Model Code1

0C 00 Not Used (Revision)

0E 00 Reserved

10 00 Not Used

12 00 Not Used

14 0C Total Number of ID

PROM Bytes

16 E8 CRC

18 to 3E yy Not Used

3.0 PROGRAMMING INFORMATION

IOS Identification Space (Read Only)

Table 3.1: IOS-484 ID Space Identification (ID)

1. The IOS model number is represented by a two-digit code within the ID space. The IOS-484 is represented by 47 Hex.



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This board is addressable in the IOS space to monitor and control the

status and configuration of up to five 16-bit counter/timers. Additionally, there are Digital I/O available for use. The IOS-484 has one RS485/RS422 digital input and three RS485/RS422 digital outputs. All the Digital I/O’s are controlled by the Digital Registers. The I/O space may be as large as 64, 16-bit words (128 bytes) using address lines A1..A6, but the IOS-484 uses only a portion of this space.

The memory space address map for the IOS-484 is shown in Table 3.2. Note that the base address for the IOS-484 in memory space must be added to the addresses shown to properly access the IOS-484 registers. Accesses are generally performed on a 16-bit basis (D0..D15), but 8-bit (D0..D8) (EO) accesses are possible in most cases.

HIGH Base

Addr.+

HIGH Byte D15 D08

LOW Byte D07 D00

LOW Base

Addr.+

01 Board Control Register 00

03 Counters Interrupt Status/Clear

Register 02

05 Counter Trigger Register 04

07 Counter Stop Register 06

09 Counter 1 Control Register 08

0B Counter 2 Control Register 0A

0D Counter 3 Control Register 0C

0F Counter 4 Control Register 0E

11 Counter 5 Control Register 10

13 ↓

1B Not Used

1

12 ↓

1A

1D Counter 1 Read Back Register 1C

1F Counter 2 Read Back Register 1E

21 Counter 3 Read Back Register 20



27 ↓

2F Not Used

1

26 ↓

2E

MEMORY MAP

Table 3.2: IOS-484 Memory Map

1. The IOS-484 will return 0 for all addresses that are "Not Used".



11

31 Counter 1 Constant A Register 30





3B ↓

43 Not Used

1

3A ↓

42

45 Counter 1 Constant B Register 44



4B Counter 4 Constant B Register 4A

4D Counter 5 Constant B Register 4C

4F ↓

57 Not Used

1 4E ↓

56

59 Not Used1

Digital Input

Register 58

5B Not Used1

Digital Output

Register 5A

5D Not Used1

Interrupt Vector

Register 5C

5F ↓

7F Not Used

1 5E ↓

7E

MEMORY MAP

1. The IOS-484 will return 0 for all addresses that are "Not Used".



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Board Control Register (Read/Write)- (Base + 00H)

This read/write register is used to identify the IOS48x model, set the carrier operational frequency, and for software reset. The function of each of the board control register bits is described in Table 3.3. This register can be read or written with either 8-bit or 16-bit data transfers. A power-up or system reset sets board control register bit 0 to logic 0.

BIT FUNCTION

0 IOS Carrier Clock Speed (Read/Write Bit) 0 = 8MHz Carrier 1 = 32MHz Carrier This bit must be set correctly for proper operation.

1 to 7 Not Used1

10, 9, 8

Identify IOS48x model. (Read Only Bits) 111 = IOS-482 100 = IOS-483 001 = IOS-484 11 to 14 Not Used

1

15 Software Reset: Write logic ―1‖ to this bit to reset the IOS-484.1

Interrupt Status/Clear Register (Read/Write) – (Base +02H)

This read/write register is used to determine the pending status of the Counter/Timer interrupts, and release pending interrupts

The Counter/Timer interrupt status/clear bits 0 to 9 reflect the status of each of the Counter/Timers. A ―1‖ bit indicates that an interrupt is pending for the corresponding counter/timer. The Counter/Timer and its corresponding interrupt Pending/Clear bits are as shown in Table 3.4.

BIT FUNCTION

0 Counter/Timer 1 Interrupt Pending/Clear





5-15 Not Used1

CONTROL REGISTERS

CAUTION: Bit 0 of the Board Control Register must be set correctly for proper module operation.

Table 3.3: Board Control Register

1. All bits labeled “Not Used” and the Software Reset bit will return logic “0” when read.

Table 3.4: IOS-484 Counter/Timer Interrupt Status/Clear

1. All bits labeled “Not Used” will return logic “0” when read.



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Read of this bit reflects the interrupt pending status of the counter timer logic.

0 = Interrupt Not Pending 1 = Interrupt Pending

Write a logic ―1‖ to this bit to release a counter timer pending interrupt. A counter timer pending interrupt can also be released by disabling interrupts via bit-15 of the Counter Control registers.

A Counter/Timer that is not interrupt enabled will never set its interrupt

status flag. A Counter/Timer interrupt can be cleared by writing a ―1‖ to its bit position in the Interrupt Status/Clear Register (writing a ―1‖ acts as a reset signal to clear the set state). The interrupt will be generated again, if the condition which caused the interrupt to occur remains. Writing ―0‖ to a bit location has no effect. That is, a pending interrupt will remain pending.

Writing to this register is possible via 16-bit or 8-bit data transfers. A power-up or system reset clears all interrupts, setting all bits in the Interrupt Status/Clear Register to logic 0.

Counter Trigger Register (Write) - (Base + 04H)

This register is used to implement software triggering for all counter/timers. Writing a 1 to the counter’s corresponding trigger bit of this register will cause the counter function to be triggered. Table 3.5 identifies the trigger bit location corresponding to each of the counters. The contents of this register are not stored and merely act to trigger the corresponding counters.

BIT FUNCTION

0 Counter 1 Trigger1





5-15 Not Used1

Triggering may be used to initiate quadrature position measurement, pulse width modulation, watchdog timer (initiates countdown), event counting, frequency measurement, pulse-width measurement, period measurement, or one-shot.

Writing to this register is possible via 16-bit or 8-bit data transfers.

CONTROL REGISTERS

Table 3.5: IOS-484 Counter Trigger Register

1. All bits will return logic “0” when read.



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Counter Stop Register (Write) - (Base + 06H)

This register is used to stop the counters of one or a group of Counter/Timers. Writing a 1 to the counter’s corresponding stop bit of this register will cause the counter to be disabled. That is, bits 2, 1, and 0 of the counter control register are cleared to ―000‖ thus disabling the counter. Table 3.6 identifies the stop bit location corresponding to each of the counters. The bits of this register are not stored and merely act to stop the corresponding counter when set logic high.

BIT FUNCTION

0 Counter 1 Stop1

1 Counter 2 Stop1

2 Counter 3 Stop1

3 Counter 4 Stop1

4 Counter 5 Stop1

5-15 Not Used1

Writing to this register is possible via 16-bit or 8-bit data transfers.

Counter Read Back Register (Read Only)

This read-only register is a dynamic function register that returns the current value held in the counter. It is updated with the value stored in the internal counter each time it is read.

The internal counter is generally initialized with the value in the Counter

Constant Register, and its value is incremented or decremented according to the application.

The addresses corresponding to the Counter Read Back registers are given in Table 3.2. This register must be read using 16-bit accesses.

Counter Constant A Register (Read/Write)

This read/write register is used to store the counter/timer constant A value (initial value) for the various counting modes. It is necessary to load the constant value into the counter in one clock cycle. Thus, access to this register is allowed on a 16-bit basis, only. The addresses corresponding to the Counter Constant A registers are given in Table 3.2.

Counter Constant B Register (Read/Write) This read/write register is used to store the counter/timer constant B

value. It is necessary to load the constant value into the counter in one clock cycle. Thus, a 16-bit write access is required. The addresses corresponding to the Counter Constant B registers are given in Table 3.2.

CONTROL REGISTERS

Table 3.6: IOS-484 Counter Stop Register

1. All bits will return logic “0” when read.

Note that the Counter Constant Registers are cleared (set to 0) following a system or software reset.



15 Digital Input Register (Read) – (Base + 58H) This 8-bit read only register contains the value of the digital RS485/RS422 inputs. A read value of one symbolizes a logic ―high‖ while a value of zero represents a logic ―low‖. Table 3.7 identifies the position of the available input bits.

BIT FUNCTION

0 DIn11 (RS485/RS422)

1-7 Not Used2

Reading this register is possible via 16-bit or 8-bit data transfers.

Digital Output Register (Read/Write) – (Base + 5AH) This 8-bit read/write register contains the value of the digital RS485/RS422 outputs. To set a digital output ―high‖ write a one to the proper bit position. To set the value logic ―low‖ write a zero to the proper bit. On power-up output bits are initialized to logic "1‖. Table 3.8 identifies the position of the available output bits.

BIT FUNCTION

0 DOut11 (RS485/RS422)

1 DOut21 (RS485/RS422)

2 DOut31 (RS485/RS422)

3-7 Not Used2

Writing to this register is possible via 16-bit or 8-bit data transfers. A software or hardware reset will set bits 0 to 2 to logic ―1‖.

Interrupt Vector Register (Read/Write) - (Base + 5CH)

The Interrupt Vector Register maintains an 8-bit interrupt pointer for all channels configured as input channels. The Vector Register can be written with an 8-bit interrupt vector as seen in Table 3.9. This vector is provided to

the carrier and system bus upon an active INTSEL cycle. Reading or writing to this register is possible via 16-bit or 8-bit data transfers.

Interrupt Vector Register

MSB LSB 07 06 05 04 03 02 01 00

Interrupts are released on access to the Interrupt Status register. Issue of a software or hardware reset will clear the contents of this register to 0.

CONTROL REGISTERS

Table 3.7: IOS-484 Digital Input Register

1. Digital Input bit will read logic “1” if left unconnected.


Table 3.8: IOS-484 Digital Input Register

1. Bit is initialized to logic “1”.


Table 3.9: IOS-483 Interrupt Vector Register



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Counter Control Register (Read/Write)

This register is used to configure counter/timer functionality. It defines the counter mode, output polarity, input polarity, clock source, debounce enable, and interrupt enable.

The IOS-484 has five 16-bit Counter/Timers. The Counter/Timers have

Differential (RS485/RS422) I/O. The memory map addresses corresponding to the control registers are given in Table 3.2. The Counter Control Register is cleared (set to 0) following a reset, thus disabling the counter/timer. Reading or writing to this register is possible via 16-bit or 8-bit data transfers.

Eight modes of operation are provided: quadrature position measurement, pulse width modulation, watchdog timer, event counting, frequency measurement, pulse width measurement, period measurement, and one-shot pulse mode. The following sections describe the features of each method of operation and how to best use them.

COUNTER CONTROL REGISTER



17

Quadrature Position Measurement

The counter/timers may be used to perform position measurements from quadrature motion encoders. Bits 2 to 0 of the Counter Control Register set to logic ‖001‖ configure the counter for quadrature measurement.

A quadrature encoder can have up to three channels: A, B, and Index.

When channel A leads channel B by 90 in a quadrature cycle, the counter

increments. When channel B leads channel A by 90 in a quadrature cycle, the counter decrements. The number of increments or decrements per cycle depends on the type of encoding: X1, X2, or X4.

An X1 encoding Increment occurs on the rising edge of channel A when channel A leads channel B. An X1 encoding decrement occurs on the falling edge of channel A when channel B leads channel A.

For X2 encoding, two increments or decrements (on each edge of channel A) result from each cycle. The counter increments when A leads B and decrements when B leads A.

For X4 encoding, four increments or decrements (on each edge of channel A and B) result from each cycle. The counter increments when A leads B and decrements when B leads A.

Quadrature measurement must be triggered internally via the Counter Trigger Register at the base address + offset 04H. An initial software trigger starts quadrature position measurement operation.

InA and InB input signals are used to input the channel A and channel B input signals, respectively. The counter will increment when channel A leads channel B and will decrement when channel B leads channel A. Three rates of increments and decrements are available X1, X2, and X4 which are programmed via counter timer control register bits 5 and 4. Channel B is enabled for input by setting bit-6 to a logic ―1‖.

InC can be used for the Index signal. Encoders that have an index channel can cause the counter to reload with the Counter Constant B value in a specified phase of the quadrature cycle. Reload can be programmed to occur in any one of the four phases in a quadrature cycle. You must ensure that the Index channel is high during at least a portion of the phase you


Figure 3.1: Shows a quadrature cycle and the resulting increments and decrements for X1, X2, and X4 encoding.

4



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specify for reload. The phase can be selected via the counter timer control register bits 9, 8, and 7 as seen in Table 3.10.

An interrupt can be generated upon index reload, or when the counter

value equals the constant value stored in the Counter Constant A Register. Interrupts must be enabled via the interrupt enable bit-15 of the Counter Control Register. The interrupt type must also be selected via bits 10 and 11 of the Counter Control Register. The interrupt will remain pending until released by setting the required bit of the Counter/Timer Interrupt Status/Clear register or setting bit-15 of the Counter Control register to ―0‖. Note that interrupts in Quadrature Position Measurement are generated whenever the interrupt conditions exists. If a pending interrupt is cleared, but the interrupt conditions still exists, another interrupt will be generated.

Bit(s) FUNCTION

2,1,0 Specifies the Counter Mode: 001 Quadrature Position Measurement

3 Output Polarity (Output Pin ACTIVE Level):

0 Active LOW (Default)1

1 Active HIGH

5, 4 InA / Channel A 00 Disabled (Default)

01 X1 Encoding

10 X2 Encoding

11 X4 Encoding

6 InB / Channel B 0 Disabled (Default) 1 Enabled

9,8,7 InC / Index: Channel Interrupt/Reload occurs when Index signal=1 and the A & B input signals are as selected below. See Control bits 11 & 10 for additional interrupt/load control.

000 Disabled (Default) 101, 110, and 111 also Disable

001 A = 0 , B = 1

010 A = 1 , B = 0

011 A = 1 , B = 1

100 A = 0 , B = 0

11,10 Interrupt Condition Select 00 No Interrupt Selected

01 Interrupt on counter equal Constant A Register.

10 Interrupt on Index and reload on Index

11

Interrupt on Index but do not reload counter on Index.

12 Not Used (bit reads back as 0)

13 Input Debounce Enable

0 Disabled (Default) – No Debounce Applied to any Input.

1

Enabled – Reject A, B, or Index Pulses less than or equal to 2.5s.


15 Interrupt Enable

0 Disable Interrupt Service (Default)

1 Enable Interrupt Service


QUADRATURE POSITION MEASUREMENT

The quadrature measurement value can be read from the Counter Read Back Register.

Table 3.10: Counter Control Register (Quadrature Position Measurement)

1. The default state of the output pin is high (output has pullup resistor installed). Bit 3 specifies the active output polarity when the output is driven.



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The Counter Control register bits 11 and 10 are used to control the

operation of the counter output signal. With bits 11 and 10 set to ―01‖, the output signal will be driven active while the counter equals the counter Constant A value. With bit 11 set to logic ―1‖ the output signal will be driven active while the index condition remains true.

Encoder output signals can be noisy. It is recommended that the InA,

InB, and InC input signals be debounced by setting bit-13 of the Counter

Control register to logic ―1‖. Noise transitions less than 2.5s will be removed with debounce enabled.


QUADRATURE POSITION MEASUREMENT



20

Pulse Width Modulation

Pulse width modulated waveforms may be generated at the counter timer output. The pulse width modulated waveform is generated continuously. Pulse Width Modulation generation is selected by setting Counter Control Register bits 2 to 0 to logic ―010‖.

Counter Constant A value controls the time until the pulse goes active.

The duration of the pulse is set via the Counter Constant B register. Note that a high pulse will be generated if active high output is selected while a low pulse will be generated if active low output is selected.

The counter goes through a countdown sequence for each Counter

Constant value. When the 0 count is detected, the output toggles to the opposite state. Then the second Counter Constant value is loaded into the counter, and countdown resumes, decrementing by one for each rising edge of the clock selected via Control Register bits 12, 11, and 10. For example, a counter constant value of 3 will provide a pulse duration of 3 clock cycles of the selected clock. Note, when the maximum internal clock frequency is selected (8MHz or 32MHz), a delay of one extra clock cycle will be added to the counter constant value.

InA can be used as a Gate-Off signal to stop and start the counter and

thus the pulse-width modulated output. When InA is enabled via bits 5 and 4 of the control register for active low Gate-Off input, a logic low input will enable pulse-width modulation counting while a logic high will stop PWM counting. When InA is enabled for active high Gate-Off operation, a logic high will enable PWM counting while a logic low will stop PWM counting.

InB can be used to input an external clock for use in PWM. Bits 7 and 6

must be set to either logic ―01‖ or ―10‖. Additionally, the clock source bits 12, 11, and 10 must be set to logic ―101‖ to enable external clock input. PWM can alternatively be internally clocked using control register bits 12, 11, and 10. Available frequencies vary depending on the carrier operational frequency.

InC can be used to externally trigger Pulse Width Modulation generation.

Additionally PWM can be triggered internally via the Counter Trigger Register at the base address + offset 04H. An initial trigger, software or external, causes the pulse width modulated signal to be generated. After an initial trigger do not issue additional triggers. Triggers issued while running will cause the Constant A and B values to load at the wrong time. In addition, changing the Control register setting while running can also cause the Constant A and B values to load at the wrong time.

If the Interrupt Enable bit of the Counter Control Register is set (bit 15), an interrupt is generated when the output pulse transitions from low to high and also for transitions from high to low. Thus, an interrupt is generated at each pulse transition.




21

Bit(s) FUNCTION

2,1,0 Specifies the Counter Mode: 010 Pulse Width Modulation



1 Active HIGH

5, 4 InA Polarity / Gate-Off Polarity 00 Disabled (Default)

01 Active LOW In A=0 Counter is Enabled In A=1 Counter is Disabled

10 Active HIGH In A=0 Counter is Disabled In A=1 Counter is Enabled

11 Disabled

7, 6 InB Polarity / External Clock Input 00 Disabled (Default) 01 External Clock Enabled

10 External Clock Enabled

11 Disabled

9,8 InC Polarity / External Trigger

00 Disabled (Default)

01 Active LOW External Trigger

10 Active HIGH External Trigger

11 Disabled

12,11,10 Clock Source2

Carrier Operational Freq. 8MHz 32MHz

000 Internal @ (Default) 0.5MHz 2MHz

001 Internal @ 1MHz 4MHz




101 External Clock Up to 2MHz Up to 8MHz



1

Enabled – Reject Gate-Off or Trigger Pulses (noise) less than or equal to 2.5s.


15 Interrupt Enable




PULSE WIDTH MODULATION

Table 3.11: Counter Control Register (Pulse Width Modulation)

1. The default state of the output pin is high (output has pullup installed). Bit 3 specifies the active output polarity when the output is driven.

2. The available clock sources are determined by the operational frequency of the carrier board. For an 8MHz carrier, bit 0 of the Board Control Register located at the base address plus an offset of 0H must be set low. For a 32MHz carrier, the bit must be set high.



22

Watchdog Timer Operation

The watchdog operation counts down from a programmed (Counter Constant A) value until it reaches 0. While counting, the counter output will be in its active state (the output polarity is programmable). Upon time-out, the counter output will return to its inactive state, and an optional interrupt may be generated. Watchdog operation is selected by setting Counter Control Register bits 2 to 0 to logic ―011‖.

A timed-out watchdog timer will not re-cycle until it is reloaded and then

followed with a new trigger. Failure to cause a reload would generate an automatic time-out upon re-triggering, since the counter register will contain the 0 it previously counted down to.

InA input can be used to reload the counter with the Constant A register

value. InA reload input is enabled via Control register bits 5 and 4. The counter can also be reloaded via a software write to the Counter Constant A register. Writing to the Counter Constant A register will load the value directly into the counter even if watchdog counting is actively counting down.

InB can be used to input an external clock for watchdog timing. Bits 7

and 6 must be set to either logic ―01‖ or ―10‖. Additionally, the clock source bits 12, 11, and 10 must be set to logic ―101‖ to enable external clock input. The timer can alternatively be internally clocked using control register bits 12, 11, and 10. Available frequencies vary depending on carrier operational frequency.

InC can be used to either continue/stop watchdog counting or as an external trigger input. When control register bits 9 and 8 are set to logic ―11‖, InC functions as a Continue/Stop signal. When the Continue/Stop signal is high the counter continues counting (when low the counter stops counting). Alternately, when control register bits 9 and 8 are set to logic ―01‖ or ―10‖, the InC input functions as an external trigger input. The watchdog timer may also be internally triggered (via the Trigger Control Register at the base address + offset 04H).

When triggered, the counter/timer contents are decremented by one for each clock cycle, until it reaches 0, upon which a watchdog timer time-out occurs. For example, a counter constant value of 30 will provide a time-out delay of 30 clock cycles of the selected clock. However, due to the asynchronous relationship between the trigger and the selected clock, one clock cycle of error can be expected. The counter can be read from the Counter Read Back register at any time during watchdog operation.

Upon time-out, the counter output pin returns to its inactive state. The

IOS-484 will also issue an interrupt upon detection of a count value equal to 0, if enabled via bit-15 of the Counter Control Register. This could be useful for alerting the host that a watchdog timer time-out has occurred and may need to be reinitialized. The interrupt will remain pending until the watchdog timer is reinitialized and the interrupt is released by setting the required bit of the Counter/Timer Interrupt Status/Clear register.




23

Bit(s) FUNCTION

2,1,0 Specifies the Counter Mode: 011 Watchdog Function



1 Active HIGH

5, 4 InA Polarity / Counter Reload 00 Disabled (Default)

01 Active LOW In A=0 Counter Reinitialized In A=1 Inactive State

10 Active HIGH In A=0 Inactive State In A=1 Counter Reinitialized

11 Disabled

7, 6 InB Polarity / External Clock Input




11 Disabled



01 Active LOW Trigger

10 Active HIGH Trigger

11 Gate-Off (Continue when high/Stop when low)










0

Disabled (Default) – No Debounce Applied to any Input.

1

Enabled – Reject Reinitialize or Trigger Pulses (noise) less than or equal to 2.5s.


15 Interrupt Enable



WATCHDOG TIMER OPERATION


Table 3.12: Counter Control Register (Watchdog Timer)





24

Event Counting Operation

Positive or negative polarity events can be counted. Event Counting is selected by setting Counter Control Register bits 2 to 0 to logic ―100‖ and setting bits 12 to 10 to logic ―000‖.

Input pulses or events occurring at the input InB of the counter will

increment the counter until it reaches the Counter Constant A value. Upon

reaching the count limit, an output pulse of 1.75s will be generated at the counter output pin, and an optional interrupt may be generated. Additionally, the internal event counter is cleared. The counter will continue counting, again from 0, until it reaches the Counter Constant A value. Once triggered, event counting will continue until disabled via Control register bits 2 to 0.

InA can be used as a Gate-Off signal to stop and start event counting. When InA is enabled via bits 5 and 4 of the control register for active low Gate-Off input, a logic low input will enable event counting while a logic high will stop event counting. When InA is enabled for active high Gate-Off operation, a logic high will enable event counting while a logic low will stop event counting.

InB is used as the event input signal. Active high or low input events can

be selected via Control register bits 7 and 6. A minimum event pulse width (InB) of 125ns is required for correct pulse detection with input debounce disabled. Programmable clock selection is not available in event counter mode.

InC can be used to either control up/down counting or as an external

trigger input. When control register bits 9 and 8 are set to logic ―11‖, InC functions as an Up/Down signal. When the Up/Down signal is high the counter is in the count down mode (when low the counter counts up). The counter will not count down below a count of zero. Alternately, when control register bits 9 and 8 are set to logic ―01‖ or ―10‖, the InC input functions as an external trigger input. Event counting may also be internally triggered (via the Trigger Control Register at the base address + offset 04H).

The Counter Constant A Register holds the count-to value (constant).

Reading the Counter Read Back Register will return the current count (variable). The Counter Constant A value must not be left as 0. The counter upon trigger starts counting from 0 and since the counter would match the count-to value the counter resets and starts counting from zero again.

If the Interrupt Enable bit of the Counter Control Register is set (bit 15), an interrupt is generated when the number of input pulse events is equal to the Counter Constant A register value. The internal counter is then cleared and will continue counting events until the counter constant A value is again reached and a new interrupt generated. An interrupt will remain pending until released by setting the required bit of the Counters Interrupt Status/Clear register at the base address + offset 02H. A pending interrupt can also be cleared, by setting Control register bit-15 to logic low.




25

Bit(s) FUNCTION

2,1,0 Specifies the Counter Mode: 100 Event Counting



1 Active HIGH

5, 4 InA Polarity / Gate-Off 00 Disabled (Default)

01 Active LOW In A=0: Continue Counting In A=1: Stop Counting

10 Active HIGH In A=0: Stop Counting In A=1: Continue Counting

11 Disabled

7, 6 InB Polarity / Event Input 00 Disabled (Default) 01 Active LOW Events

10 Active HIGH Events

11 Disabled





11 Up when logic low /Down when logic high Count Control

12,11,10 Specifies the Counter Mode: 000 Event Counting



1

Enabled – Reject Gate-Off, Event Input, Up/Down or Trigger Pulses (noise) less than or equal to 2.5s.


15 Interrupt Enable




EVENT COUNTING OPERATION

Table 3.13: Counter Control Register (Event Counting)




26

Frequency Measurement Operation

Frequency Measurement is selected by setting Counter Control Register

bits 2 to 0 to logic ―100‖ and setting bits 12 to 10 to logic ―111‖. The counter counts how many InB edges (low to high or high to low) are received during the InA enable interval. The frequency is the number of counts divided by the duration of the InA enable signal.

InA is used as an enable signal to start frequency measurement. The

InA signal must be a pulse of known width. When InA is configured (via bits 5 and 4 of the control register) as an active low enable input, a logic low input will enable frequency measurement while a logic high will stop frequency measurement. When InA is configured as an active high enable signal, a logic high will enable frequency measurement while a logic low will stop frequency measurement.

InB is used to input the signal whose frequency is to be measured. Input

pulses occurring at input InB of the counter are counted while the enable signal present on InA is active. When the InA signal goes inactive, the

counter output will generate a 1.75s output pulse and an optional interrupt.

InC can be used as an external trigger input. When control register bits 9 and 8 are set to logic ―01‖ or ―10‖, the InC input functions as an external trigger input. Frequency measurement may also be internally triggered (via the Trigger Control Register at the base address + offset 04H). An initial trigger, software or external, starts frequency measurement upon the active edge of the InA enable signal.

The Counter Constant A Register is not used for frequency

measurement. Do not write to this register while the counter is actively counting since this will cause the counter to be loaded with the Constant A value.

Reading the Counter Read Back Register will return the current count

(variable). A minimum event pulse width (InB) is required for correct pulse detection with input debounce disabled. A carrier operating at 8MHz requires an 125ns event pulse, while a carrier operating at 32MHz requires an 31.25ns event pulse. With debounce enabled, a minimum event pulse

width of 2.5s is required for correct pulse detection. Programmable clock selection is not available for frequency measurement.

If the Interrupt Enable bit-15 of the Counter Control Register is set, an

interrupt is generated when the input InA enable pulse goes inactive. An interrupt will remain pending until released by setting the required bit of the Interrupt Status/Clear register at the base address + offset 02H. A pending interrupt can also be cleared, by setting the Counter Control register bit-15 to logic low.




27

Bit(s) FUNCTION

2,1,0 Specifies the Counter Mode: 100 Frequency Measurement



1 Active HIGH

5, 4 InA Polarity / Enable Pulse of Known Width 00 Disabled (Default)

01 Active LOW Pulse

10 Active HIGH Pulse

11 Disabled

7, 6 InB Polarity / Signal Measured/Counted 00 Disabled (Default) 01 Active LOW Pulse Counted

10 Active HIGH Pulse Counted

11 Disabled





11 Disabled

12,11,10 Specifies the Counter Mode: 111 Frequency Measurement



1

Enabled – Reject Frequency Input Enable, or Trigger Pulse (noise) less than or equal to 2.5s.


15 Interrupt Enable




FREQUENCY MEASUREMENT OPERATION

Table 3.14: Counter Control Register (Frequency Measurement)

1. The default state of the output pin is high (output has pullup resistor installed). Bit 3 specifies the active output polarity when the output is driven.



28

Input Pulse Width Measurement

Setting bits 2 to 0 of the Counter Control Register to logic ―101‖ configures the counter for pulse-width measurement. After pulse-width measurement is triggered, the first input pulse is measured.

InA is used to input the pulse to be measured. An active low or high

pulse can be measured. InB can be used to input an external clock for Pulse-Width Measurement.

Bits 7 and 6 must be set to either logic ―01‖ or ―10‖. Additionally, the clock source bits 12, 11, and 10 must be set to logic ―101‖ to enable external clock input. Pulse Width Measurement can alternatively be internally clocked using control register bits 12, 11, and 10. Available frequencies vary depending on carrier operational frequency.

InC can be used to externally trigger Pulse Width Measurement.

Additionally, Pulse Width Measurement can be triggered internally via the Counter Trigger Register at the base address + offset 04H. An initial trigger, software or external, starts pulse width measurement at the beginning of the next active pulse.

For pulse-width measurement, the pulse-width being measured serves as an enable control for an up-counter whose value can be read from the Counter Read Back Register. When triggered, the counter is reset and then increments by one for each clock pulse while the input signal level remains in the active state (high or low according to the programmed polarity of input InA). The resultant pulse-width is equivalent to the count value read from the Counter Read Back Register, multiplied by the clock period. An output pulse will be generated at the counter output pin to signal the completion of

a given measurement. Note that the measured pulse may be in error by 1 clock cycle.

Reading a counter value of 0xFFFF hex indicates that the pulse duration

is longer than the current counter size and clock frequency can measure. Upon reading of this overflow value you must select a slower frequency and re-measure.

An interrupt can be generated upon completion of a given pulse width

measurement (the pulse has returned to the opposite polarity), if enabled via the interrupt enable bit of the Counter Control Register (bit 15). The interrupt will remain pending until released by setting the required bit of the Interrupt Status/Clear register at the base address + offset 02H. A pending interrupt can also be cleared, by setting the Counter Control register bit-15 to logic low.




29

Bit(s) FUNCTION

2,1,0 Specifies the Counter Mode: 101 Pulse-Width Measurement



1 Active HIGH

5, 4 InA Polarity / Pulse Polarity to be Measured 00 Disabled (Default)

01 Active LOW Pulse is Measured

10 Active HIGH Pulse is Measured

11 Disabled

7, 6 InB Polarity / External Clock Input 00 Disabled (Default) 01 External Clock Enabled


11 Disabled





11 Disabled











1

Enabled – Reject Input Pulse Measured or Trigger Pulses (noise) less than or equal to 2.5s. Using Debounce will add an error of up to 800ns when used for input pulse measurement.


15 Interrupt Enable




INPUT PULSE WIDTH MEASUREMENT

Table 3.15: Counter Control Register (Input Pulse Width Measurement)





30

Input Period Measurement

The counter/timer may be used to measure the period of an input signal at the counter input InA. Setting bits 2 to 0 of the Counter Control Register to logic ―110‖ configures the counter for period measurement. The first input cycle after period measurement is triggered will be measured.

InA is used to input the signal to be measured. Period measurement can

be initiated on the active low or high portion of the waveform. The period of signal is the time the signal is low added to the time the signal is high, before it repeats.

InB can be used to input an external clock for period measurement. Bits

7 and 6 must be set to either logic ―01‖ or ―10‖. Additionally, the clock source bits 12, 11, and 10 must be set to logic ―101‖ to enable external clock input. Period measurement can alternatively be internally clocked using control register bits 12, 11, and 10. Available frequencies vary depending on carrier operational frequency.

InC can be used to externally trigger period measurement. Additionally,

Period Measurement can be triggered internally via the Counter Trigger Register at the base address + offset 04H. An initial trigger, software or external, starts period measurement at the beginning of the next active period.

The period being measured serves as an enable control for an up-counter whose value can be read from the Counter Read Back Register. When triggered the counter is reset. Then, the active polarity of InA starts period measurement. The counter increments by one for each clock pulse during the input signal period (InA). The resultant period is equivalent to the count value read from the Counter Read Back Register, multiplied by the

clock period. A 1.75s output pulse will be generated at the counter output pin to signal the completion of a given measurement. Note that the

measured period may be in error by 1 clock cycle. Reading a counter value of 0xFFFF hex indicates that the pulse duration

is longer than the current counter size and clock frequency can measure. Upon reading of this overflow value you must select a slower frequency and re-measure.

An interrupt can be generated upon completion of a given period

measurement, if enabled via the interrupt enable bit of the Counter Control Register (bit 15). The interrupt will be generated upon completion of the first complete waveform cycle after the counter is triggered. The interrupt will occur even if an external clock is selected but no clock signal is provided on InB. The count value will be zero in this case. The interrupt, once driven active, will remain pending until released by setting the required bit of the Interrupt Status/Clear register at the base address + offset 02H. A pending interrupt can also be cleared, by setting Counter Control register bit-15 to logic low.




31

Bit(s) FUNCTION

2,1,0 Specifies the Counter Mode: 110 Period Measurement

3 Output Polarity (Output Pin ACTIVE Level): 0 Active LOW (Default)

1

1 Active HIGH

5, 4 InA Polarity / Signal Measured 00 Disabled (Default)

01 Active LOW portion of the signal starts period measurement.

10 Active HIGH portion of the signal starts period measurement.

11 Disabled

7, 6 InB Polarity / External Clock Input 00 Disabled (Default) 01 External Clock Enabled 10 External Clock Enabled 11 Disabled





11 Disabled

12,11,10 Clock Source









0

Disabled (Default) – No Debounce Applied to any Input.

1

Enabled – Reject Source or Trigger Pulses (noise) less than or equal to 2.5s. Using Debounce will add an error of up to 800ns when used for period measurement.


15 Interrupt Enable




INPUT PERIOD MEASUREMENT

Table 3.16: Counter Control Register (Input Period Measurement)





32

One-Shot Pulse Mode

One-Shot pulse mode provides an output pulse that is asserted one time

or repeated each time it is re-triggered. One-Shot generation is selected by setting Counter Control Register bits 2 to 0 to logic ―111‖.

The Counter Constant A value controls the time until the pulse goes active. The duration of the pulse high or low is set via the Counter Constant B value. Note that the Constant B value defines the logic high pulse width, if active high output is selected, and a low pulse if active low output is selected.

The counter goes through a full countdown sequence for each Counter

Constant value. When the 0 count is detected, on the next rising-edge of the clock, the output toggles to the opposite state, and the Counter Constant B value is loaded into the counter and countdown resumes, decrementing by one each clock cycle. For example, a counter constant value of 7 will provide a pulse duration of 7 clock cycles of the selected clock, then 125ns will be added for the count detection of 0. Note that this extra delay is only 31.25ns for 32MHz carrier operation.

InA can be used as a Gate-Off signal to stop and start the counter and,

thus output. When InA is enabled via bits 5 and 4 of the control register for active low Gate-Off input, a logic low input will enable the one-shot counter while a logic high will stop the one-shot counter. When InA is enabled for active high Gate-Off operation, a logic high will enable the one-shot counter while a logic low will stop the one-shot counter.

InB can be used to input an external clock for use in one-shot. Bits 7

and 6 must be set to either logic ―01‖ or ―10‖. Additionally, the clock source bits 12, 11, and 10 must be set to logic ―101‖ to enable external clock input. One-Shot pulse mode can alternatively be internally clocked via control register bits 12, 11, and 10. Available frequencies vary depending on carrier operational frequency.

InC can be used to externally trigger One-Shot pulse mode. Additionally,

a one-shot pulse can be triggered internally via the Counter Trigger Register at the base address + offset 04H. An initial trigger, software or external, causes the one-shot signal to be generated with no additional triggers required. Additional triggers must not be input until the one shot pulse has completed count down of the Constant B value.

If the Interrupt Enable bit-15 of the Counter Control Register is set, an interrupt is generated when the pulse transitions from low to high and also when the pulse transitions from high to low. The interrupt will remain pending until released by setting the required bit of the Interrupt Status/Clear register at the base address + offset 02H. A pending interrupt can also be cleared, by setting the Counter Control register bit-15 to logic low.




33

Bit(s) FUNCTION

2,1,0 Specifies the Counter Mode: 111 One-Shot Generation



1 Active HIGH

5, 4 InA Polarity / Gate-Off Polarity 00 Disabled (Default)

01 Active LOW In A=0 Output Enabled In A=1 Output Disabled

10 Active HIGH In A=0 Output Disabled In A=1 Output Enabled

11 Disabled

7, 6 InB Polarity / External Clock Input




11 Disabled





11 Disabled











1 Enabled – Reject Gate-Off or Trigger Pulses (noise) less than or equal to 2.5s.


15 Interrupt Enable




ONE-SHOT PULSE MODE

Table 3.17: Counter Control Register (One-Shot Pulse)


2. The available clock sources are determined by the operational frequency of the carrier board. For an 8MHz carrier, bit 0 of the Board Control Register located at the base address plus an offset of 0H must be set low. For a 32MHz, carrier the bit must be set high.



34

The following section provides sample applications for each of the counter modes of operation. This includes I/O pin assignments, register settings, required calculations, and waveform diagrams. All examples assume 8MHz carrier operation, even addressing, and that all values are read and written in hex. These assumptions may differ depending on the system and software being used.

Quadrature Position Measurement Example The objective for this example is to employ Quadrature Position Measurement using 16-bit Counter 1. Suppose that an encoder, connected to the shaft of a motor, provides three signals. Two of the signals (A and B)

are out of phase by 90 and provide directional information. For this example, Channel A will always lead B. The third signal C is an Index pulse that is active every four revolutions (A pulses). Assume that X2 encoding is used and on the index pulse, when Channel A and B are equal to one, an active high output and interrupt are generated, and the counter is reloaded to zero. Additionally, debounce is enabled.

1. Connect the inputs/output to the following pins (unpowered):

Pin # Connection Pin # Connection Description

1 In1_A(+) 2 In1_A(-) Channel A

11 In1_B(+) 12 In1_B(-) Channel B

29 In1_C(+) 30 In1_C(-) Index

17 Out1(+) 18 Out1(-) Output

2. Write the following information, A9E9H, to Counter 1 Control Register located at base address plus an offset of 08H.

Bits Logic Operation

2,1,0 001 Sets the counter to Quadrature Position Measurement.

3 1 Sets the output to active high.

5,4 10 Sets encoding to X2 and enables Channel A (InA).

6 1 Enables Channel B (InB).

9,8,7 011 Sets the Index condition to occur when A=1 and B=1.

11,10 10 Provides for interrupt and reload to occur on index.

12 0 Not used.

13 1 Enables input debounce on InA, InB, and InC.

14 0 Not used.

15 1 Enables interrupts.

3. Write the 32-bit value 0H to Counter 1 Constant B Register located at base address plus an offset 44H for the counter reload value.

The Constant B Register contains the reload value of the counter. Therefore, in this example, when an index pulse occurs and Channel A and B are equal to one, the counter loads zero. This value relies on the specific application.

PROGRAMMING EXAMPLES

Table 3.18: Quadrature Pin Assignments for Counter 1

Table 3.19: Quadrature Counter Control Register 1 Settings



35 While Counter Constant A is not used in this example, it has other applications in Quadrature Position Measurement. Refer to the description of Quadrature mode for further information. 4. The following is a waveform diagram of this example. Since Quadrature mode does not accept external triggers, assume that a software trigger has already occurred.

i i

Output

InB

InC

InA

Interrupts When the index condition is true the counter will reload the value in Counter Constant B register, and an interrupt is generated. The output remains active for as long as the Index condition holds true. For further information on encoder counting, index pulse conditions, interrupts, and outputs, see the Quadrature Position Measurement description.

Pulse Width Modulation Example The objective for this example is to create a pulse width modulated with

an active high pulse of 2s and a low pulse of 6s using 16-bit Counter 3. The counter has an external active high gate-off, trigger, and clock signals. The output is active high. Assume the external clock has a frequency of 500KHz. The Gate-Off signal will become active after 2 PWM cycles. Additionally, debounce and interrupts are enabled.



5 In3_A(+) 6 In3_A(-) Gate-Off

15 In3_B(+) 16 In3_B(-) Ext. Clock

33 In3_C(+) 34 In3_C(-) Ext. Trigger


2. Write the following information, B66AH, to Counter 3 Control Register located at base address plus an offset of 0CH.


2,1,0 010 Sets the counter to Pulse Width Modulation mode.


5,4 10 Enable the Gate-Off input (InA) to active high.

7,6 01 Enables the external clock input (InB).

9,8 10 Enables the external Trigger Input (InC) to active high.

12,11,10 101 Sets the clock to an external source.

13 1 Enables input debounce on InA and InC.


Figure 3.2: Quadrature waveform

In the figure each ―i‖ represents an interrupt

Table 3.20: PWM Pin Assignments for Counter 3

Table 3.21: PWM Counter Control Register 3 Settings



36

14 0 Not used.


3. Write the 16-bit value 3H to Counter 3 Constant A Register located at base address plus an offset 34H for the non-active portion of the pulse, and 1H to Counter 3 Constant B Register located at base address plus an offset 48H for the active portion of the pulse.

In order to determine the necessary Counter Constant values first calculate the period of the selected clock (internal or external). The period is calculated by taking the inverse of the clock frequency. In this case,

1/500KHz is equal to 2s. Then take the total time for the low portion of the

pulse and divide it by the clock period. For this example, 6s/2s is equal to 3. Convert this value to Hex and the result is the total count that is placed in the appropriate Counter Constant Register. Since it has been stipulated that the pulse is active high, 3H is written to Counter 3 Constant A Register, which contains the value for the non-active (low) portion of the pulse. The same procedure is used to calculate the Constant B value. Take the total period of the high portion of the pulse and divide it by the period of the clock.

Here 2s/2s is equal to 1. Converting to hex, 1H is written to Counter 3 Constant B Register since it contains the active (high) portion of the pulse. 4. The following is a waveform diagram of this example.

i ii i

Output

InB

InC

InA

Interrupts

Note that the InA and InC inputs run off the internal 8MHz (or 32MHz) clock. Those signals may not be synchronous with the selected clock. For further information, see the Pulse Width Modulation Operation description.

Watchdog Timer Operation Example The objective for this example is to create a Watchdog Timer with a

countdown length of 10s using 16-bit Counter 5 with an external active high counter reload, clock, and active low trigger signals. The output is active high. Assume the external clock has a frequency of 500KHz. The counter reload and trigger signals are periodic. Additionally, debounce and interrupts are enabled.


Figure 3.3: PWM waveform

In the figure an ―i‖ represents an interrupt



37



9 In5_A(+) 10 In5_A(-) Reload




2. Write the following information, B56BH, to Counter 5 Control Register located at base address plus an offset of 10H.


2,1,0 011 Sets the counter to Watchdog mode.


5,4 10 Enable the Counter Reload input (InA) to active high.


9,8 01 Enables the external Trigger Input (InC) to active low.


13 1 Enables input debounce on InA and InC.

14 0 Not used.


3. Write the 16-bit value 5H to Counter 5 Constant A Register located at the base address plus an offset of 38H. In order to determine the correct Constant A Register value, first calculate the period of the selected clock. The period is calculated by taking

the inverse of the clock frequency. In this case, 1/500KHz is equal to 2s. Then take the total duration of the watchdog timer and divide it by the clock

period. For this example, 10s/2s is equal to five. Converted to Hex, this is the number to write to the Counter 5 Constant A Register. 4. The following is a waveform diagram of this example.

i i

Output

InB

InC

InA

Interrupts

In Watchdog mode, the counter must be loaded (InA) and then triggered (InC) for each cycle. While this can be done internally or externally, failure to follow this procedure will cause unpredictable results.


Table 3.22: Watchdog Pin Assignments for Counter 5

Table 3.23: Watchdog Counter Control Register 5 Settings

Counter Constant B Register is not used in Watchdog mode.

Figure 3.4: Watchdog waveform




38

Note that the InA and InC inputs run off the internal 8MHz (or 32MHz) clock. Those signals may not be synchronous with the selected clock. For further information, see the Watchdog Timer Operation description.

Event Counting Operation Example The objective for this example is to create an Event Counter that will count the number of active high events on InB using 16-bit Counter 5. The output is active low. Additionally the counter has an active low Gate-Off and an active low External Trigger. After every five events, the event counter interrupts. 1. Connect the inputs/output to the following pins (unpowered):



27 In5_B(+) 28 In5_B(-) Event Input



2. Write the following information, 8194H, to Counter 5 Control Register located at base address plus an offset of 10H.


2,1,0 100 Sets the counter to Event Counting mode.

3 0 Sets the output to active low.

5,4 01 Enable the Gate-Off input (InA) to active low.

7,6 10 Enables the Event input (InB) to active high.


12,11,10 000 Sets the counter to Event Counting mode.

13 0 Disables input debounce on InA, InB, and InC.

14 0 Not used.


3. Write the 16-bit value 5H to Counter 5 Constant A Register located at the base address plus an offset of 38H. In Event Counting, when the Constant A Register is equal to the value in the Counter 5 Read Back Register, in this case located at base address plus an offset of 24H, there is an output pulse and an interrupt. Furthermore, when this condition occurs, the counter resets to zero and starts incrementing again. For this example, an interrupt and output pulse will occur every five events. Therefore 5H is written to the Counter 5 Constant A Register. Note that all values are stored and read in Hex.


Table 3.24: Event Counting Pin Settings for Counter 5

Table 3.25: Event Counter Control Register 5 Settings

Counter Constant B Register is not used in Event Counting mode.



39 4. The following is a waveform diagram of this example.

ii

Output

InB

InC

InA

Interrupts The Gate-Off signal is used in this example to pause the counter. While the Gate-Off signal is non-active (logic high), the counter and output

will remain constant. Additionally, the output pulse is active for 1.75s upon the detection of the final event. For further information, see the Event Counting Operation description.

Frequency Measurement Operation Example The objective for this example is to use the Frequency Measurement Operation using 16-bit Counter 4. The enable signal and the signal measured are active high. Additionally, the counter has an active low External Trigger. The output of the counter is active low and interrupts and

debounce are enabled. Assume the enable pulse has a duration of 50s. 1. Connect the inputs/output to the following pins (unpowered):


7 In4_A(+) 8 In4_A(-) Enable Input

25 In4_B(+) 26 In4_B(-) Signal Input



2. Write the following information, BDA4H, to Counter 4 Control Register located at base address plus an offset of 0EH.


2,1,0 100 Sets the counter to Frequency Measurement.

3 0 Sets the output to active low.

5,4 10 Sets the Enable Pulse input (InA) to active high.

7,6 10 Enables the Signal input (InB) to active high.


12,11,10 111 Sets the counter to Frequency Measurement mode.

13 1 Enables input debounce on InA, InB, and InC.

14 0 Not used.




Figure 3.5: Event Counting waveform

Table 3.26: Frequency Measurement Pin Assignments for Counter 4

Table 3.27: Frequency Measurement Control Register 4 Settings



40

3. Do not write to either of the Counter 4 Constant Registers. They are not required for frequency measurement and writing to them can cause errors. 4. The following is a waveform diagram of this example.

i

Output

InB

InC

InA

Interrupts The frequency of the signal is calculated by dividing the value in the Counter 4 Read Back Register, located at base address plus an offset of 22H, by the duration of the InA enable signal. Note that the value in the Read Back Register is stored in Hex and requires conversion to decimal for

calculations. In this case the pulse length is 50s. The value in the Read Back Register is 9, since there were nine high pulses during the enable

signal. Therefore, the frequency is 9/50s, which is equal to 180KHz. Note that the counter must be re-triggered before the next frequency measurement can take place. Additionally, the output pulse is active for

1.75s. Since debounce was enabled the output pulse will occur 2.5s after the completion of the enable signal. For further information, see the Frequency Measurement Operation description.

Input Pulse-Width Measurement Example The objective for this example is to use the Pulse-Width Measurement Operation using 16-bit Counter 2. The pulse to be measured is active low. Additionally the counter has an external clock and an active low External Trigger. The output of the counter is active high and interrupts are enabled. Assume the external clock has a frequency of 100KHz. 1. Connect the inputs/output to the following pins (unpowered):


3 In2_A(+) 4 In2_A(-) Pulse Input





Figure 3.6: Frequency Measurement waveform


Table 3.28: Pulse-Width Measurement Pin Assignments for Counter 2



41 2. Write the following information, 959DH, to Counter 2 Control Register located at base address plus an offset of 0AH.


2,1,0 101 Sets the counter to Pulse-Width Measurement.


5,4 01 Sets the Pulse input (InA) to active low.




13 0 Disables input debounce on InA and InC.

14 0 Not used.


3. Do not write to either of the Counter 2 Constant Registers. They are not required for pulse-width measurement and writing to them can cause errors. 4. The following is a waveform diagram of this example.

i

Output

InB

InC

InA

Interrupts

The length of the low portion of the InA pulse is calculated by multiplying the number in the Counter 2 Read Back Register, located at base address plus an offset of 1EH, by the period of the selected clock. Note that the value in the Read Back Register is stored in Hex and requires conversion to decimal for calculations. In this case the value in the Read Back Register is 9, since there were nine high pulses during the active InA signal. The period of the clock is calculated by taking the inverse of the frequency of the clock. For this example, the frequency was 100KHz. Therefore the clock

period is 1/100KHz, which is equal to 10s. The clock period multiplied by

the Read Back Register 10s x 9, is equal to 90s, the duration of the active

low InA pulse. This value may be in error by 1 clock period. Note that the InA and InC inputs run off the internal 8MHz (or 32MHz) clock. Those signals may not be synchronous with the selected clock. The

output pulse is active for 1.75s. If debounce was enabled, the output pulse

will occur 2.5s after the completion of the input pulse. Additionally, the counter must be re-triggered before any further measurements take place. For more information, see the Pulse-Width Measurement description.


Table 3.29: Pulse-Width Measurement Control Register 2 Settings

Figure 3.7: Pulse-Width Measurement waveform




42

Input Period Measurement Example The objective for this example is to use the Input Period Measurement operation using 16-bit Counter 1. The high-to-low transition of the input signal will begin measurement. Additionally, the counter has an external clock and an active high External Trigger. The output of the counter is active high and interrupts are enabled. Assume the external clock has a frequency of 250KHz. 1. Connect the inputs/output to the following pins (unpowered):


1 In1_A(+) 2 In1_A(-) Pulse Input




2. Write the following information, 965EH, to Counter 1 Control Register located at base address plus an offset of 08H.


2,1,0 110 Sets the counter to Input Period Measurement.


5,4 01 Sets the Pulse input (InA) to active low.





14 0 Not used.


3. Do not write to either of the Counter 1 Constant Registers. They are not required for input period measurement and writing to them can cause errors. 4. The following is a waveform diagram of this example.

i

Output

InB

InC

InA

Interrupts


Table 3.30: Input Period Measurement Pin Assignments for Counter 1

Table 3.31: Input Period Measurement Control Register 1 Settings

Figure 3.8: Input Period Measurement waveform




43 The period of one cycle of the InA waveform is calculated by multiplying the number in the Counter 1 Read Back Register, located at the base address plus an offset of 1CH, by the period of the selected clock. Note that the value in the Read Back Register is stored in Hex and requires conversion to decimal for calculations. In this case the value in the Counter 1 Read Back Register is 8, since there were eight high pulses during one InA period. The period of the clock is calculated by taking the inverse of the frequency of the clock. For this example, the frequency was

250KHz. Therefore, the clock period is 1/250KHz, which is equal to 4s.

The clock period multiplied by the Read Back Register 4s x 8, is equal to

32s (the period of the InA waveform). This value may be in error by 1 clock period. Note that the InA and InC inputs run off the internal 8MHz (or 32MHz) clock. Those signals may not be synchronous with the selected clock. The

output pulse is active for 1.75s. If debounce was enabled, the output pulse

will occur 2.5s after the completion of the input signal. Additionally, the counter must be re-triggered before any further measurements take place. For more information, see the Input Period Measurement description.

One-Shot Pulse Mode Example The objective for this example is to use the One-Shot Pulse mode using

16-bit Counter 2. The output pulse is active high with the low portion 20s

long and the high portion 5 s long. Additionally, the counter has an external clock, an active high Gate-off signal, and an active high External Trigger. Interrupts are enabled. Assume the external clock has a frequency of 200KHz. 1. Connect the inputs/output to the following pins (unpowered):






2. Write the following information, 966FH, to Counter 2 Control Register located at base address plus an offset of 0AH.


2,1,0 111 Sets the counter to One-Shot Pulse generation mode.


5,4 10 Sets the Gate-Off input (InA) to active high.





14 0 Not used.



Table 3.32: One-Shot Pulse Pin Assignments for Counter 2

Table 3.33: One-Shot Pulse Control Register 2 Settings



44

3. Write the 16-bit value 4H to Counter 2 Constant A Register located at base address plus an offset 32H for the non-active portion of the pulse, and 1H to Counter 2 Constant B Register located at base address plus an offset 46H for the active portion of the pulse.

In order to determine the necessary Counter Constant values first calculate the period of the selected clock (internal or external). The period is calculated by taking the inverse of the clock frequency. In this case,

1/200KHz is equal to 5s. Then take the total time for the low portion of the

pulse and divide it by the clock period. For this example, 20s/5s is equal to 4. Convert this value to Hex and the result is the total count that is placed in the appropriate Counter Constant Register. Since it has been stipulated that the pulse is active high, 4H is written to the Counter 2 Constant A Register, which contains the value for the non-active (low) portion of the pulse. The same procedure is used to calculate the Constant B value. Take the total period of the high portion of the pulse and divide it by the

period of the clock. For this example 5s/5s is equal to 1. Converting to hex, 1H is written to Counter 2 Constant B Register since it contains the active (high) portion of the pulse. 4. The following is a waveform diagram of this example.

i i ii

Output

InB

InC

InA

Interrupts

The Gate-Off signal (InA) is used as a pause mechanism. The counter register and output remain constant while the Gate-Off signal is active. In this example, this occurs when InA is logic low. Note that the InA and InC inputs run off the internal 8MHz (or 32MHz) clock. Those signals may not be synchronous with the selected clock. For further information, see the One-Shot Pulse Mode description.


Figure 3.9: One-Shot Pulse waveform




45

Table 3.34: Counter Timer Modes Overview

Function

Description

Pulse Width

Modulation/

One-Shot

Watchdog Event

Counting

Frequency

Measure

Pulse

Measure

Period

Measure

Quadrature

Position

Measure

InA Input Gate-Off for

start/stop

control

Counter

Reload

Gate-Off for

start/stop

control

Enable

Frequency

Measurement

for Set

Duration

Next complete

pulse after

trigger is

measured.

Next complete

period after

trigger is

measured.

Channel A

InB Input External Clock External

Clock

Event Input Signal

Measured/

Counted

External Clock External Clock Channel B

InC Input External

Trigger

External

Trigger or

Gate-Off for

start/stop

control

External

Trigger or

Up/Down

Count Control

External

Trigger

External

Trigger

External

Trigger

Index

Internal

Software Trig

Starts

Waveform

Generation

Starts

Count

Down

Start Event

Counting

Start

Frequency

Measurement

on next active

edge of InA

signal.

Next complete

pulse after

trigger is

measured.

Next complete

period after

trigger is

measured.

Starts

Quadrature

Measurement

Counter Timer

Output

Output

Waveform

Output is

active from

trigger until

terminal

count.

1.75s pulse

is output upon

reaching the

count limit

1.75s pulse

is output upon

end of

frequency

measurement

1.75s pulse

is output upon

end of pulse

measurement

1.75s pulse

is output upon

end of period

measurement

Output pulse

while index or

programmed

count limit

remains true.

Constant A

Reg

Count down

from value

loaded.

Defines

duration until

active pulse

Counts

down from

value

loaded.

Must

always load

before

trigger.

Note that

InA input

can be

used to

reload.

Count Limit.

Input events

are counted

up to the

count limit.

An interrupt

can be

generated

when the

counter

equals the

Constant A

value.

Constant B

Reg

Count down

from value

loaded.

Defines

duration of

active pulse

Constant B

can be

reloaded on

occurrence of

an Index

signal.

Counter Read

Back Reg

Gives the

Count value

at the time

of the read.

Gives the

Count value at

the time read.

Gives count

value

reflecting

measurement

Gives count

value

reflecting

pulse

measured

Gives count

value

reflecting

period

measured

Gives count

value

reflecting

position

measurement

Interrupt On Edge

Transitions

On

Terminal

Count of 0

Upon reach of

count limit

Upon end of

enable pulse

Upon end of

pulse

measurement

Upon end of

period

measurement

On Index or

Constant A

count limit.



46

This section contains information regarding the hardware of the IOS-484. A description of the basic functionality of the circuitry used on the board is also provided. Refer to the IOS-484 Block Diagram as you review this material.

A Field Programmable Gate-Array (FPGA) installed on the IOS Module

provides an interface to the carrier board per IOS Module specification ANSI/VITA 4 1995. The interface to the carrier board allows complete control of all board functions.

The field I/O interface to the IOS module is provided through connector P2 (refer to Table 2.1). These pins are tied to the inputs and outputs of EIA RS485/RS422 line transceivers or TTL transceivers. RS485 signals received are converted from the required EIA RS485/RS422 voltages signals to the TTL levels required by the FPGA. Likewise TTL signals are converted to the EIA RS485/RS422 voltages for data output transmission. The FPGA provides the necessary interface to the RS485/RS422 transceivers or TTL transceivers for control of data.

The field I/O interface to the carrier board is provided through connector P2 (refer to Table 2.1). Field I/O points are NON-ISOLATED. This means that the field return and logic common have a direct electrical connection to each other. As such, care must be taken to avoid ground loops (see Section 2 for connection recommendations). Ignoring this effect may cause operational errors, and with extreme abuse, possible circuit damage.

Differential RS485/RS422 input control signals In_A, In_B, and In_C are available for the five 16-bit counters of the board. See Table 2.1 for the list of these signals and their corresponding pin assignments.

Counter timer out signals OUT1 to OUT5 are differential RS485/RS422 signals output from the five 16-bit counters. See Table 2.1 for the output signals and their corresponding pin assignments.

Digital input/output signals DIN1 and DOut1 to 3 are differential RS422

signals. The signals are available via the P1 field I/O connector. See Table 2.1 for the list of these signals and their corresponding pin assignments.

4.0 THEORY OF OPERATION

FIELD INPUT/OUTPUT SIGNALS

COUNTER/TIMERS

DIGITAL I/O



47

Surface-Mounted Technology (SMT) boards are generally difficult to repair. It is highly recommended that a non-functioning board be returned to Acromag for repair. The board can be easily damaged unless special SMT repair and service tools are used. Further, Acromag has automated test equipment that thoroughly checks the performance of each board. When a board is first produced and when any repair is made, it is tested, placed in a burn-in room at elevated temperature, and retested before shipment.

Please refer to Acromag's Service Policy Bulletin or contact Acromag for

complete details on how to obtain parts and repair.

Before beginning repair, be sure that all of the procedures in Section 2, Preparation For Use, have been followed. Also, refer to the documentation of your carrier/CPU board to verify that it is correctly configured. Replacement of the module with one that is known to work correctly is a good technique to isolate a faulty module. Acromag’s Applications Engineers can provide further technical assistance if required. When needed, complete repair services are also available from Acromag. If you continue to have problems, your next step should be to visit the Acromag worldwide web site at http://www.acromag.com. Our web site contains the most up-to-date product and software information.

Go to the ―Support‖ tab to access:

Application Notes

Frequently Asked Questions (FAQ’s)

Product Knowledge Base

Tutorials

Software Updates/Drivers An email question can also be submitted from within the Knowledge Base of directly from the ―Contact Us‖ tab. Acromag’s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed at the bottom of this page. If needed, complete repair services are also available.

5.0 SERVICE AND REPAIR

SERVICE AND REPAIR ASSISTANCE

PRELIMINARY SERVICE PROCEDURE

CAUTION: POWER MUST

BE TURNED OFF

BEFORE REMOVING OR

INSERTING BOARDS

WHERE TO GET HELP

www.acromag.com



48

Physical Configuration Single I/O Server Module Length 4.030 in. (102.36 mm) Width 1.930 in. (49.02 mm) Board Thickness 0.062 in. (1.59 mm) Height 0.500 in. (12.7 mm)

Power Requirements

Module IOS-484

5V (5%)

Typical 410mA

Max. 480mA

+/-12V (5%)

Not used

Operating Temperature: -40 to 85C.

Relative Humidity: 5-95% Non-Condensing.

Storage Temperature: -55C to +125C.

Non-Isolated: Logic and field commons have a direct electrical connection.

Resistance to RFI: Complies with EN61000-4-3 (3 V/m, 80 to 1000MHz

AM & 900MHz. Keyed) and European Norm EN50082-1 with no digital

upsets.

Conducted R F Immunity (CRFI): Complies with EN61000-4-6 (3V/rms,

150kHz to 80MHz) and European Norm EN50082-1 with no digital

upsets.

Electromagnetic Interference Immunity (EMI): No register upsets under

the influence of EMI from switching solenoids, commutator motors,

and drill motors.

Surge Immunity: Not required for signal I/O per European Norm

EN50082-1.

Electric Fast Transient Immunity EFT: Complies with EN61000-4-4 Level 2

(0.5KV at field input and output terminals) and European Norm

EN50082-1.

Electrostatic Discharge (ESD) Immunity: Complies with EN61000-4-2

Level 3, (8KV enclosure port air discharge) Level 2, (4KV enclosure port

contact discharge) Level 1, (2KV I/O terminal contact discharge) and

European Norm EN50082-1.

6.0 SPECIFICATIONS

Table 6.1: Power Requirements 5V Maximum rise time of 100m seconds

ENVIRONMENTAL



49

Radiated Emissions: Meets or exceeds European Norm EN50081-1 for

class B equipment. Shielded cable with I/O connections in a shielded

enclosure is required to meet compliance.

Counter Functions: Quadrature Position Measurement, Pulse Width

Modulation, Watchdog Timer, Event Counting, Frequency Measurement,

Period Measurement, Pulse-Width Measurement, and One

Shot/Repetitive

Counter Type: - The IOS-484 has a total of five counter/timers available for

use with differential RS485/RS422 I/O.

Counters 1 through 5 have Differential RS485/RS422 input signals of

InA, InB, and InC. These differential input ports are used to control

Start/Stop, Reload, Event Input, External Clock, Trigger, and Up/Down

operations.

Fail-Safe: When differential inputs are left floating, receiver output is logic

high.

-0.2 Min to 0.2 Max: Differential Input Threshold Voltage with

–7V VCM 12V

70mV Typical: Input Hysteresis

12K Minimum Input Resistance

Termination Resistors: Termination Resistors are not provided.

Termination resistors are recommended at network end points only (see

RS485 I/O Connections for location).

Counters 1 through 5 each have a Differential RS485/RS422 Output.

The Differential output ports 6 and 7 are used for waveform output,

watchdog active indicator, or 1.75s pulse upon counter function

completion. Counter output is programmable as active high or low.

1.5 V Minimum: Differential Driver Output Voltage with 27 load:

3 V Maximum: Common Mode Output Voltage.

Selectable Counter Clock Frequencies: 8MHz, 4MHz, 2MHz, 1MHz,

0.5MHz or External up to 2MHz.

Minimum I/P Event: 125ns

Minimum Pulse Measurement: 125ns

SPECIFICATIONS

COUNTER/TIMERS

RS485/RS422 Counter Input

RS485/RS422 Input Electrical Characteristics

RS485/RS422 Counter Output

RS485/RS422 Output Electrical Characteristics

8MHz IOS Carrier Operation



50

Minimum Period Measurement: 300ns

Minimum Gate/Trigger Pulse: 125ns

Selectable Counter Clock Frequencies : 32MHz, 16MHz, 8MHz, 4MHz,

2Mhz or External up to 8MHz.

Minimum I/P Event: 31.25ns

Minimum Pulse Measurement: 31.25ns

Minimum Period Measurement: 150ns

Minimum Gate/Trigger Pulse: 31.25ns

Digital I/O: Specifications for RS485/RS422 Digital Input 1 and

RS485/RS422 Digital Outputs 1-3 are the same as the counter inputs and

outputs. See the ―RS485/RS422 Input Electrical Characteristics‖ and

―RS485/RS422 Output Electrical Characteristics‖ sections on the previous

page.

SPECIFICATIONS

32MHz IOS Carrier Operation

DIGITAL I/O

IOS

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FPGA P1

16-BIT

BUS

P2

IN A+(1-5)

IN A-(1-5)

IN C+(1-5)

IN C-(1-5)

OUT+(1-5)

OUT-(1-5)CLOCK

BUS

INTERFACE

CONTROL LOGIC

RS485/TTL CONVERSIONBUFFER

16-BIT

COUNTER #2

COUNTER #416-BIT

16-BIT

RS485/RS422 COUNTER TIMER INPUT

IN B-(1-5)

IN B+(1-5)

RS485/RS422 COUNTER TIMER OUTPUT

I/OINTERFACE


INTERFACE


COUNTER #1

COUNTER TIMER


COUNTER #5

IOS

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Documents

IOS-484 User's Manual - Acromag | Embedded Computing ... · IOS-484 I/O Server Module User’s Manual Counter Timer Module ... number of programming environments including Visual