Ionic Memory and Ionic Memory and the Future of the Future of Storage?Storage?

Michael N. KozickiMichael N. KozickiDirector, Center for Applied NanoionicsDirector, Center for Applied Nanoionics

Arizona State UniversityArizona State University

IDEMA Symposium, December 2008

Recent contributorsRecent contributors……

Sunil Baliga *Murali Balakrishnan

**Nad Gilbert +Chakku Gopalan

Deepak Kamalanathan ++Maria Mitkova

Minghan Ren Ugo Russo

Christina SchindlerSarath Chandran Puthen Thermadam

Anthony Volpe

Now with:* Seagate** DMTA+ Adesto++ Boise State

Borrowed from Forschungszentrum

Jülich

Borrowed from Politecnico di

Milano

Sponsor Sponsor

Outline of talk

• The terabit memory regime• Ionic memory basics• Device operation• Active arrays and MLC• Passive/multi layer arrays• Physical and electrical scalability• Forward thinking• Final points and questions

Terabit memory – the heart ofsolid state storage?

• Physical scalability– Assume a “chip-like” form factor with extremely compact

periphery/high array efficiency– For a 20 x 20 mm2 terabit array area and a 4 - 6F2 cell, F (half-

pitch) must be less than 10 nm– The sub-10 nm node is a long way off and the reliability of sub-

10 nm metallic wires is doubtful!– Implies F > 10 nm but then multi-level cell plus multi-layer array

is absolutely necessary to achieve density• Electrical scalability

– At the 22 nm memory half-pitch node, the supply voltage is significantly below 1V

– critical current in 22 nm wires is no more than a few tens of µA• Manufacturability

– Reliability– CMOS (BEOL) compatibility– Cost– Longevity…

• The terabit memory regime

• Ionic memory basics• Device operation• Active arrays and MLC• Passive/multi layer arrays• Physical and electrical scalability• Forward thinking• Final points and questions

In the words of Masakazu Aono…

“Heine Rohrer showed five examples of where, if the space becomes small, new phenomena happen… if the distance is very short, diffusion (atomic or ionic motion) is very fast.”

This principle lies at the heart of nanoionics

ACS Nano, Vol. 1, No. 5, 379-383 (2007)

nature materials | VOL 6 | NOVEMBER 2007 | www.nature.com/naturematerials

Rainer Waser and Masakazu Aono

…ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed…

“…the 5-nm-thick oxide film initially contained one layer of insulating TiO2 and one layer of oxygen-poor TiO2-x. In this system, oxygen vacancies act as mobile +2-charged dopants, which drift in the applied electric field, shifting the dividing line between the TiO2 and TiO2-x layers.”

Cation-based resistance-change device

Glassy electrolytehigh resistance

Tungstenelectrode

Silver/copperelectrodeMetallic electrodeposit

low resistance

+

-

MM → M+ + e-

M+ + e- → MM

e-

e-

Bias > write threshold

Ion current

MA

SS FLOW

Reverse (or hi-forward) bias dissolves electrodeposit

• The terabit memory regime• Ionic memory basics

• Device operation• Active arrays and MLC• Passive/multi layer arrays• Physical and electrical scalability• Forward thinking• Final points and questions

Ag0.4(Ge3Se7)0.6 device characteristics

1.0E+04

1.0E+05

1.0E+06

1.0E+07

1.0E+08

1.0E+09

1.0E+10

1.0E+11

-1 -0.5 0 0.5Voltage (V)

Res

ista

nce

(Ohm

s)

240 nm diameter device programmed at 1 µA

Off

On

1E+03

1E+05

1E+07

1E+09

1E+11

1E-01 1E+01 1E+03 1E+05 1E+07 1E+09

Time [s]

R(O

N) [

Ohm

]

50°C70°C

R(OFF)

10y

5 orders of magnitude change maintained after 10 years at high T

Source: Infineon

• 0.25 V threshold• Low current operation• Vast OFF to ON ratio,

Ron set by current/charge

• Excellent endurance• Solid retention

-30369

1215

1.0E+09 1.0E+10 1.0E+11

Cycles

Test

cir

cuit

curr

ent (

µA)

Endurance >>1012 cycles with no degradation evident (75 nm device)

Final resistance vs.programming current (slow sweep)

1.00E+01

1.00E+02

1.00E+03

1.00E+04

1.00E+05

1.00E-06 1.00E-05 1.00E-04 1.00E-03 1.00E-02

Current (Amps)

Resi

stan

ce (O

hms)

000001010011100101110111

Ron = Ve/ipVe is around 100 mV

Band width ∆R = ±40%

Binary coding of full range split into 4/8 bands

Dynamic (pulse) programming

Macro Model Fit to W-GeSe-Ag 0.5 µm DeviceTransimpedance Amplifier, Rf=1k (WRITE)

-0.4

-0.2

0

0.2

0.4

0.6

0 100 200 300 400 500Time (ns)

Volta

ge (V

)Lab_IN

Lab_OUT

Sim_in

Sim_out

Write

Off

On

N. Gilbert, C. Gopalan, and M. N. Kozicki, “A Macro model of Programmable Metallization Cell Devices,” Solid State Electronics, vol. 49, 1813-1819 (2005).

Dynamic (pulse) erase

Macro Model Fit to W-GeSe-Ag 0.5 µm Device Transimpedance Amplifier, Rf=1k (ERASE)

-0.8

-0.6

-0.4

-0.2

0

0.2

0 100 200 300 400 500Time (ns)

Volta

ge (V

)

Lab_in

Lab_out

Sim_out

Sim_in

Erase

On Off

N. Gilbert, C. Gopalan, and M. N. Kozicki, “A Macro model of Programmable Metallization Cell Devices,” Solid State Electronics, vol. 49, 1813-1819 (2005).

• The terabit memory regime• Ionic memory basics• Device operation

• Active arrays and MLC• Passive/multi layer arrays• Physical and electrical scalability• Forward thinking• Final points and questions

Array options

Vprog Vprog

VprogVprog Solid electrolyte element

Active (1T-1R) Passive (diode isolated)

SelectWL

Bias BL

+/- VT/2

-/+ VT/2

Selected cell has +/-half threshold voltage on row and -/+half on column for write or erase (inc. diode threshholds)

Vprog is above or below transistor drain voltage to program or erase selected cell, programming current via bit line (BL)

Programmable Metallization Cell test chip

26 ns access

ArrayRow Decode

Column Decode

Bias

ReadWrite Write

EraseErase

1T-1R array built using a 180 nm foundry CMOS process, electrolyte on M2-M3 via plugs, one additional mask over standard CMOS

Thanks to Ishai Naveh and Efraim Aloni and Tower Semiconductor, for CMOSand Nad Gilbert , Desert Microtechnology Associates, for design

N.E. Gilbert and M.N. Kozicki, “An Embeddable Multilevel-Cell Solid Electrolyte Memory Array,” IEEE Journal of Solid-state Circuits, vol. 42, no. 6, pp 1383-1391, June 2007

MLC write

Three transistors are used to create three discrete current levels to set ON resistance (gives 4 resistance states = 2 bits).

N.E. Gilbert and M.N. Kozicki, “An Embeddable Multilevel-Cell Solid Electrolyte Memory Array,” IEEE Journal of Solid-state Circuits, vol. 42, no. 6, pp 1383-1391, June 2007

MLC read

Fig. 3. Read circuit for multi-bit per cell implementations.

Device is used as reference to produce half write threshold in READ – avoids disturb.

Switchable comparators used to sense device current

N.E. Gilbert and M.N. Kozicki, “An Embeddable Multilevel-Cell Solid Electrolyte Memory Array,” IEEE Journal of Solid-state Circuits, vol. 42, no. 6, pp 1383-1391, June 2007

MLC array operation

00 01 10 11

N.E. Gilbert and M.N. Kozicki, “An Embeddable Multilevel-Cell Solid Electrolyte Memory Array,” IEEE Journal of Solid-state Circuits, vol. 42, no. 6, pp 1383-1391, June 2007

• The terabit memory regime• Ionic memory basics• Device operation• Active arrays and MLC

• Passive/multi layer arrays• Physical and electrical scalability• Forward thinking• Final points and questions

Example of multi-layer approach

1st device layer

2nd device layer

Example (from Matrix Semiconductor) showing diode isolation in a passive array of OTP structures

Solid electrolyte devices are compatible with such 3-D approaches, although passive arrays require unipolar programming or Zener diode isolation

M. Johnson et al., “512-Mb PROM With a Three-Dimensional Array ofDiode/Antifuse Memory Cells,” IEEE Journal of Solid-state Circuits, vol. 11, no. 38, 1920-1928, 2003

Zener diode isolation

<10 nA leakage at -1.5 V

Memoryturn onTurn off

Roff > 100 MΩRon ~ 75 kΩ (above diode turn on) for 10 µA programming current(Ag-Ge-S electrolyte)

Integrated diode isolation

-6.0E-07

-4.0E-07

-2.0E-07

0.0E+00

2.0E-07

4.0E-07

6.0E-07

8.0E-07

1.0E-06

-1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6

Voltage(V)

Cur

rent

(A)

Roff > 100 MΩRon ~ 400 kΩ (above diode turn on) for 1 µA programming current(Ag-Ge-Se electrolyte)

Memoryturn on

Turn off

• Off state: P-type Ag-Ge-Se on n-type Si cathode (1018 cm-3 Sb) • On state: N-type Si and Ag filament form Schottky diode

• The terabit memory regime• Ionic memory basics• Device operation• Active arrays and MLC• Passive/multi layer arrays

• Physical and electrical scalability• Forward thinking• Final points and questions

Current-mode images of CAFM switching

6.2 nA

+1V write, -10mV read 5 nm electrodeposit!

Images courtesy of Christina Schindler, Forschungszentrum Jülich

Ultra-low programming current

(a) (b)

C. Schindler et al., ”Low current resistive switching in Cu–SiO2 cells,”Appl. Phys. Lett., 92, 122910 (2008).

• The terabit memory regime• Ionic memory basics• Device operation• Active arrays and MLC• Passive arrays and multi layer• Physical and electrical scalability

• Forward thinking• Final points and questions

IBM J. RES. & DEV. VOL. 52 NO. 4/5 JULY/SEPTEMBER 2008

If the test vehicles being built with phase-change and solid electrolyte memory (already competitive with NOR flash in terms of density) can be transferred to high-yield manufacturing of memory chips and satisfy the stringent error-rate requirements of NOR flash, then these emerging NVM technologies could compete with NOR flash in the near future. In turn, as the increasing density of such a new NVM technology drives down cost, markets for NAND flash, DRAM… and server-class HDD storage could potentially be addressed.

Thank you for your attention!

Back-up slides

Schematic diagram of two-stage conducting filament formation process

Both the initial formation and radial growth are driven by ion migration, possibility of Joule heating due to current flow through the conducting filament

U. Russo, D. Kamalanathan, D. Ielmini, A. L. Lacaita, and M. N. Kozicki, in press.

Calculated RC in a Ag/Ag-Ge-S/W 1T-1R device as a function of pulse width tW

In this case the Ag-Ge-S electrolyte has been optimized for CMOS process compatibility, not speed

U. Russo, D. Kamalanathan, D. Ielmini, A. L. Lacaita, and M. N. Kozicki, in press.

Negative constant current stress

Exponential dependence (not power law – no

electromigration?)

Joule heating?

Failure time defined by 10x

increase in resistance

1 mA write current, stress current in erase direction

On-state stability/erase characteristics

Lower programmed resistance is more stable but also more difficult to erase

Departure from exponential behavior at low -Vstress

A Novel Resistance Memory with High Scalability and Nanosecond SwitchingK. Aratani, K. Ohba, T. Mizuguchi, S. Yasuda, T. Shiimoto, T. Tsushima, T. Sone, K. Endo, A. Kouchiyama, S. Sasaki, A. Maesaka, N. Yamada, and H. Narisawa, Sony CorporationA dual-layered electrolytic resistance memory has been demonstrated for the first time. Complete nanosecond switching of all cells in the 4kbit array, satisfactory retention, scalability down to 20nm, endurance up to 1E7 cycles, and preliminary 4-level operation will be presented to qualify this memory for the next generation nonvolatile memory.

Cu-Te electrolyteon

GdOx dielectric

Quantized conductance atomic switchK. Terabe,et al., NIMS, Nature, vol. 433, p. 47 (2005).

Conductive Bridging Memory Development from Single Cells to 2Mbit Memory Arrays, R. Symanczyk et al., Qimonda, NVMTS 2007A Non-Volatile 2Mbit CBRAM Memory Core Featuring Advanced Read and Program Control, H. Hönigschmid et al., Infineon/Altis, VLSI Circuits Symp. 2006

• Advanced 2 Mb core design– 1T-1R dense array designed as memory core block– 90 nm, 1.5 V CMOS technology– Minimum transistor, 8F2 cell, 0.0648 µm2

– <50 ns random read/write cycle times

1E+03

1E+05

1E+07

1E+09

1E+11

1E+13

1E-01 1E+01 1E+03 1E+05 1E+07 1E+09

Time [s]

Res

ista

nce

[Ohm

]

25°C70°C100°C

OFF

ON

10y

0100200300400500600700

1E+031E+041E+051E+061E+071E+081E+091E+101E+11

R (ON) / R (OFF) [Ohm]

Cou

nt [#

]

resolutionlimit

Sampling of 2007 VLSI Symposia papersTime Discrete Voltage Sensing and Iterative Programming Control for a 4F2 Multilevel CBRAMP. Schrögmeier*, M. Angerbauer*, S. Dietrich*, M. Ivanov*, H. Hönigschmid*, C. Liaw*, M. Markert*, R. Symanczyk*, L. Altimime*, S. Bournat** and G. Müller* *Qimonda AG, Germany and **Altis Semiconductor, FranceMLC, 90nm, 4F2, 1T1CBJ, 4Mb CBRAM core, on-pitch time-discrete voltage sensing scheme, bitline charge balancing reference, self-timed iterative program concept, random read cycle times 0.7 µs and random write cycle times 1.35 µs.

A Ta2O5 Solid-Electrolyte Switch with Improved ReliabilityT. Sakamoto*,**, N. Banno*,**, N. Iguchi*, H. Kawaura*, H. Sunamura*, S. Fujieda*, K. Terabe**,***, T. Hasegawa**,*** and M. Aono**,*** *NEC Corp., **ICORP, Japan Science & Technology Agency (JST) and ***National Institute of Material Science, JapanNanoBridge for FPGA applications, replaces Cu2S withTa2O5 for Si-process compatibility and control of threshold, high cycling endurance (>1E4) and stability (>10 years at 2.6 mA).