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I/O STANDARDS & DESIGN
Muthukumar Nagarajan02/29/08
2 IO Standards & Design
AGENDA
• GOAL• SIGNALING STANDARDS• INPUT BUFFER• OUTPUT BUFFER• I/O DESIGNS• ESD
3 IO Standards & Design
GOAL
A peek into the world of I/O standards and I/O buffer design
• Brief Introduction to Signaling (I/O) Standards• Key I/O parameters• I/O buffer designs• Analog design in I/O buffers
4 IO Standards & Design
I/O STANDARDS
• WHY I/O STANDARDS• To create a common language that IC’s can use to communicate with each other and form a system to enable a solution
• I/O STD ORG’s• Several governing bodies create communication protocols. The Electrical signaling standards (I/O std.) is one part of this protocol• Some well known organizations
• JEDEC (LVTTL, LVCMOS, HSTL, SSTL)• TIA/EIA (LVDS, VoIP)• IEEE (802 LAN/MAN)
5 IO Standards & Design
I/O STANDARDS
Data Rate (Gb/s) Data Transmission
Signaling Standard Primary Source
Electrical Standard Bus
Width Full Bus Rate Per Data
Line Data vs Clock
Single-ended or Differential
Timing Method
I2C, SMBus Philips I2C (pull-down only) 1 100-400kb/s 100-400kb/s SDR SE System CLK
SDIO SD Assoc. SDIO SDR SE
PCI, PCI-X PCI 32 2.1, 4.2 0.033,0.066,
0.133 SDR SE System CLK
PCI-Express Intel
PCI-Express 1-32 2.5-80 2.5 DDR Diff CDR
RapidIO Group "LP" LVDS 8, 16 4-12.5 1-3.125 DDR Diff Iso-Sync, CDR
HyperTransport AMD 1.2V LVDS 2-32 0.8-51.2? 0.4-1.6
(800Mhz max)
DDR Diff Iso-Sync, CDR
SRAM, SDRAM, DRAM
(LV)TTL/(LV)CMOS 4-32 0- 0-0.167 SDR SE System CLK
DDR SSTL_2+DDR 4-16 0.4-6.4 0.1, 0.2,
0.333, 0.4 DDR SE Iso-Sync
DDRII SSTL_18+DDRII 4-16 1.6-12.8 0.4-0.8 DDR SE Iso-Sync DDRIII 1.2-1.5V (Open Drain?) ? ? 0.8-1.5 ? ? ? AMB
JEDEC
Mobile-DDR Group: eg. Micron & Samsung
Group Datasheets 16, 32
0-10.66 0-0.333 DDR SE Iso-Sync
QDR Group: eg
Cypress, IDT Extended HSTL SE
RDRAM Rambus SPI-3 LVTTL/LVCMOS 32 3.3 0.104 SDR SE
SPI-4.1 HSTL, Class 1 64 12.8 0.2 SDR SE Iso-Sync SPI-4.2 LVDS 16 10 0.625 DDR Diff Iso-Sync
SFI-4.1, XSBI LVDS+SFI-4.1,10GbE 16 9.952 0.622 DDR Diff Iso-Sync SPI-5 SxI-5 4 12.5 3.125 DDR Diff CDR
SFI-4.2 SxI-5 4 12.5 3.125 DDR Diff CDR SFI-5
OIF
SxI-5 4 12.5 3.125 DDR Diff CDR OIF 6G-11G OIF LVDS DDR Diff CDR
XAUI IEEE XAUI 4 12.5 3.125 DDR Diff CDR GbE (1, 10) IEEE GbE (1 PECL, 10) 1 1,10 1,10 DDR Diff CDR
MDIO IEEE MDIO 1 0.003-0.01 0.003-0.01 SDR SE System CLK Fibre-Channel
(Parallel, Serial) (SSTL_2,PECL) 1 1-4 1-4 DDR Diff CDR
HSIO HSIO DDR Diff CDR Infiniband Infiniband 4 10 2.5 DDR Diff CDR
AGP 1-2X Intel AGP 1-2X 32 2.1, 4.2 0.066, 0.133 SDR, DDR SE System CLK
AGP 4X Intel AGP 4X (HSTL-like) 32 8.4 0.266 DDR SE Iso-Sync AGP 8X Intel AGP 8X 32 17 0.533 DDR
IEEE 1394 IEEE LVDS 1 ? Diff
USB USB
Implementors Forum
USB 1 0.01-0.4 0.01-0.4 SDR Diff System CLK
SCSI SCSI 1 SDR SE
6 IO Standards & Design
I/O BUFFER TYPE
• SINGLE ENDED• A signal (Data or Clock) that is defined by a single port/wire/net• Signal swing is Rail-to-Rail or a small swing around a fixed reference level
• DIFFERENTIAL• A signal (Data or Clock) that is defined by the difference of two signals around a common mode level• Small signal swings, High speed, Low noise
7 IO Standards & Design
INPUT BUFFER
• SINGLE ENDED (CMOS)• Basically an inverter• Designed for a specific Voltage Trip Point by simply using P vs. N FET W/L ratio
• DIFFERENTIAL• Basically a Diff. Amp.• Designed for a specific CM level and Input Swing
• FEATURES• Hysterisis to improve Noise Immunity• Input pin ESD Protection• Buffer output to drive the Chip core• Performance requirements (High speed, Low power, Low leakage, HV tolerance etc.) dictate buffer design and complexity
8 IO Standards & Design
INPUT BUFFER: TOPOLOGIES 1
9 IO Standards & Design
INPUT BUFFER: TOPOLOGIES 2
10 IO Standards & Design
INPUT BUFFER: TOPOLOGIES 3
11 IO Standards & Design
INPUT BUFFER : KEY PARAMETERS 1
• VIH – Input HIGH Level• VIL – Input LOW Level• VHYST – Hysterisis (VIH - VIL)• VREF – Input Reference Voltage• VIPP – Peak-to-Peak Input Swing• VICM – Input Common Mode Level• FMAX – Max Frequency of operation• ISB – Leakage Power• ICC – Dynamic (Active) Power
12 IO Standards & Design
INPUT BUFFER : KEY PARAMETERS 2
SSTL_3 SSTL_2 HSTL Parameter TTL/LVTTL CMOS
Class I Class II Class I Class II SSTL_18
Class I Class II Class III Class IV
Vio Various Various 3.0-3.6 2.3-2.7 1.7-1.9 1.4-1.6 Voh 2.4V 80-90%Vio 1.9V 2.1V 1.74V 1.94V Vtt+0.603 Vio-0.4V Vol 0.4V 10-20%Vio 0.7V 0.5V 0.56V 0.37V Vtt-0.603 0.4V
Ioh (mA) Various 0.1 8 16 8.1 16.2 13.4 8 16 8 8
Iol (mA) Various 0.1 8 16 8.1 16.2 13.4 8 16 24 48
Vih 2V 70%Vio Vref+0.2V Vref+0.15V Vref+0.125V Vref+0.2V
Vil 0.8V 20%Vio Vref-0.2V Vref-0.15V Vref-0.125V Vref-0.2V
Vref N/A N/A 1.3V to 1.7V 0.5*Vio 0.5*Vio+/-2%,
Vtt=Vref+/-0.04V 0.68V to 0.9V
Standard Note 1 Note 1 JESD8-8 JESD8-9b JESD8-15 JESD8-6
Rs () Various Various ~22-65 ~11-30 ~35-60 ~15-30 ~45-65 ~22-65 ~11-30 pd:~7-20 pd:~3-10
13 IO Standards & Design
OUTPUT BUFFER
• SINGLE ENDED (CMOS)• Basically an inverter• Designed to drive large loads (several pF)
• DIFFERENTIAL• Basically a Diff. Amp.• Designed for a specific CM level and Output Swing
• FEATURES• Tri-State• Output pin ESD protection• Programmable Drive strength, Slew rate• Hot Swap, HV Tolerance• Weak Pull-up, Pull-down• Signal voltage domain converter• Impedance Matching
14 IO Standards & Design
OUTPUT BUFFER: TOPOLOGIES 1
15 IO Standards & Design
OUTPUT BUFFER: TOPOLOGIES 2
16 IO Standards & Design
OUTPUT BUFFER : KEY PARAMETERS 1
• VOH – Output HIGH Level @ IOH• VOL – Output LOW Level @ IOL• IOH – Output HIGH current @ VOH• IOL - Output LOW current @ VOL• IOZ – Output pin leakage• tOR, tOF – Output Rise/Fall time• Noise (On chip Pwr/Gnd and Signal)• VOPP – Peak-to-Peak Output Swing• VOCM – Output Common Mode Level• FMAX – Max Frequency of operation• ISB – Leakage Power• ICC – Dynamic (Active) Power
17 IO Standards & Design
OUTPUT BUFFER : KEY PARAMETERS 2
SSTL_3 SSTL_2 HSTL Parameter TTL/LVTTL CMOS
Class I Class II Class I Class II SSTL_18
Class I Class II Class III Class IV
Vio Various Various 3.0-3.6 2.3-2.7 1.7-1.9 1.4-1.6 Voh 2.4V 80-90%Vio 1.9V 2.1V 1.74V 1.94V Vtt+0.603 Vio-0.4V Vol 0.4V 10-20%Vio 0.7V 0.5V 0.56V 0.37V Vtt-0.603 0.4V
Ioh (mA) Various 0.1 8 16 8.1 16.2 13.4 8 16 8 8
Iol (mA) Various 0.1 8 16 8.1 16.2 13.4 8 16 24 48
Vih 2V 70%Vio Vref+0.2V Vref+0.15V Vref+0.125V Vref+0.2V
Vil 0.8V 20%Vio Vref-0.2V Vref-0.15V Vref-0.125V Vref-0.2V
Vref N/A N/A 1.3V to 1.7V 0.5*Vio 0.5*Vio+/-2%,
Vtt=Vref+/-0.04V 0.68V to 0.9V
Standard Note 1 Note 1 JESD8-8 JESD8-9b JESD8-15 JESD8-6
Rs () Various Various ~22-65 ~11-30 ~35-60 ~15-30 ~45-65 ~22-65 ~11-30 pd:~7-20 pd:~3-10
18 IO Standards & Design
CY I/O DESIGN
• Programmable I/O’s in PSoC• I/O Ring
19 IO Standards & Design
ESD
•