Inverting amplifier: [Closed Loop Configuration]chettinadtech.ac.in/storage/15-01-03/15-01-03-10-08-05-Devilatha.pdf · Inverting amplifier: [Closed Loop Configuration] ... To design

LINEAR INTEGRATED CIRCUITS LAB

1

Inverting amplifier: [Closed Loop Configuration] Design:

ACL = Vo/Vin = - Rf / Rin; Assume Rin = ______; Gain = _______; Circuit Diagram:

Model Graph

Observation:

For input: Peak to peak amplitude of the input = volts.

Time period for 1 full cycle = sec

Frequency of the input = Hz

For output: Peak to peak amplitude of the output = volts.


Frequency of the output = Hz

CRO

+

~

+

–

–

+10V

7

6

4

v0

-10V

RF

IC741

2

3

Rin

F.G

(V)

Vin

Vo

(V)

t(sec)

t(sec)

Inverting amp


2

EX. NO: 1 DATE: _ _ /_ _ / 2010

Inverting, Non inverting and differential amplifiers.

AIM

To design Inverting, Non inverting amplifier & Differentiator using op-amp and

test its performance

APPARATUS REQUIRED

S.No Components Range Quantity

1. Op-amp IC 741 1

2. Dual trace supply (0-30) V 1

3. Function Generator (0-1) MHz 2

4. Resistors

5. Capacitors

6 CRO (0-30)

MHz

1

THEORY

INVERTING AMPLIFIER

The inverting amplifier is the most widely used of all the op-amp circuits. The

output voltage V0 is fed back to the inverting input terminal through the Rf-R1

network where Rf is the feedback resistor. Input signal Vi is applied to the inverting

input terminal through R1 and non-inverting input terminal of op-amp is grounded.

V0 = - (Rf/R1) Vi

ACL= V0/Vi = -Rf/R1

The negative sign indicates a phase shift of 1800 between Vi and V0.


3

Inverting amplifier Design


4

NON-INVERTING AMPLIFIER

The non-inverting amplifier circuit amplifies without inverting the input

signal. In this circuit, the input is applied the non-inverting input terminal &

inverting input terminal is grounded. Such a circuit is called non-inverting

amplifier. It is also a negative feedback system as output is being fed back to the

inverting input terminal.

Vo = ( 1 + Rf/R1) Vi

ACL=Vo/Vi = 1 + Rf/R1

Non inverting amplifier Design


5

Non inverting amplifier: [Closed Loop Configuration]

Design:

ACL = Vo / Vin = 1 + Rf / Rin; Assume Rin = ______; Gain = _______;

Circuit Diagram

Model Graph

Observation:

For input: Peak to peak amplitude of the input = volts.






(V)

Vin

Vo

(V)

t(sec)

t(sec)

Non-Inverting amp

CRO

+

~

+

–

–

+10V

7

6

4

v0

-10V

2

3

Rin

F.G

RF


6

DIFFERNTIAL AMPLIFIER

The differential amplifier has a unique feature that many circuits don’t have -

two inputs. This circuit amplifies the difference between its input terminals. Many

circuits that have one input, actually have another input – the ground potential. The

differential amp rejects the noise common to both signals and rescues the signal

difference between the input terminals.

Design of Differential amplifier

R1=R2=R3=Rf = R = __________

VO = Rf / R [V2 – V1]


7

Circuit Diagram

Observation:

For input 1: Peak to peak amplitude of the input = volts.



For input 2: Peak to peak amplitude of the output = volts.







8

Procedure:

1. Connect the components as per the circuit diagram.

2. Set the input voltage using F.G

3. observe the output waveform at Pin no.6

4. Connect CRO at Pin no.6 and measure 0/p voltage and note it down.

5. Plot the output waveforms

RESULT:

Pre – Lab Test (20) Remarks &

Signature

with Date

Simulation (20)

Circuit Connection (30)

Result (10)

Post – Lab Test (20)

Total (100)


9

Circuit Diagram

Model Graph:

Observation:

For sine wave input:

Peak to peak amplitude of the input = volts. Frequency of the input = Hz Peak to peak amplitude of the output = volts. Frequency of the output = Hz

For square wave input: Peak to peak amplitude of the input = volts. Frequency of the input = Hz Peak to peak amplitude of the output = volts. Frequency of the output = Hz


10

EX. NO: 2 DATE: _ _ /_ _ / 2010

INTEGRATOR AND DIFFERENTIATOR

AIM

To design an integrator & Differentiator using op-amp and test its performance.

APPARATUS REQUIRED


1. Op-amp IC 741 1



4. Resistors

5. Capacitors

6 CRO (0-30)

MHz

1

DIFFERENTIATOR:

A circuit in which output waveform is the derivative of the input waveform is known

as the differentiator or the differentiation amplifier. Such a circuit is obtained by using

operational amplifier in the inverting configuration connecting a capacitor, C1 at the

input V0= - RfC1 dVi/dt

INTEGRATOR:

The circuit performs the mathematical operation of Integration, that is, the

output waveform is the integral of input waveform.

V0 (t)= -1/R1Cf ∫Vi(t)dt+V0(0)

V0 (0) = initial output voltage


11

Differentiator:

Design:

Step1: Select fa equal to the highest frequency of the input signal to be

differentiated. Then assuming a value of C1 < 1µF. calculate the value of Rf.

Step2: Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf.

fa = KHz ; fb = KHz ;C1 = 0.1 µf; RCOMP = Rf ; RL = 10KΩ

fa = 1/ [2πRfC1]; Rf = 1/2π C1 fa ; fb = 1/ [2πR1C1];R1 = 1/2π C1 fb;R1C1 = Rf Cf;

Cf = R1C1/ Rf


12

Integrator:

Design:

Generally the value of the fa and in turn R1Cf and Rf Cf values should be selected

such that fa < fb. From the frequency response we can observe that fa is the frequency

at which the gain is 0 db and fb is the frequency at which the gain is limited. Maximum

input signal frequency = 1 KHz.

Condition is time period of the input signal is larger than or equal to Rf Cf (i.e.)

T 1 fR C≥

fb = KHz ; fa = fb/10; Rf = 10R1; RCOMP = R1; RL & R1 = 10KΩ

fa = 1/ [2πRfCf]; Rf Cf = 1msec &; Cf = 1msec/100K


13

Circuit Diagram:

Model Graph

Observation:


Peak to peak amplitude of the input = volts.


Peak to peak amplitude of the output = volts.


For square wave input:





Vin

RL

R1

+12V

-12V

Rf

Cf

Rom = R1

+

-

IC 7413

26

74

0

VO = - [1/R1Cf] ∫Vin dt

RCOMP

Vin

Vo

t

t

Model graph

t

t


14

Procedure:


2. Set the input voltage using F.G




RESULT:


Signature

with Date

Simulation (20)


Result (10)


Total (100)


15

EX. NO: 3 DATE: _ _ /_ _ / 2010

INSTRUMENTATION AMPLIFIER

AIM

To design an instrumentation amplifier Using Op-Amp & test its performance.

APPARATUS REQUIRED


1. Op-amp IC 741 3



4. Resistors

5. Capacitors

6 CRO (0-30)

MHz

1

THEORY

INSTRUMENTATION AMPLIFIER:

An instrumentation (or instrumentational) amplifier is a type of differential

amplifier that has been outfitted with input buffers, which eliminate the need for input

impedance matching and thus make the amplifier particularly suitable for use in

measurement and test equipment. Additional characteristics include very low DC

offset, low drift, low noise, very high open-loop gain, very high common-mode

rejection ratio, and very high input impedances. Instrumentation amplifiers are used

where great accuracy and stability of the circuit both short- and long-term are

required.

The electronic instrumentation amp is almost always internally composed of 3 op-

amps. These are arranged so that there is one op-amp to buffer each input (+,−), and

one to produce the desired output with adequate impedance matching for the


16

function.Consider all resistors to be of equal value except for Rgain. The negative

feedback of the upper-left op-amp causes the voltage at point 1 (top of Rgain) to be

equal to V1. Likewise, the voltage at point 2 (bottom of Rgain) is held to a value equal to

V2. This establishes a voltage drop across Rgain equal to the voltage difference between

V1 and V2. That voltage drop causes a current through Rgain, and since the feedback

loops of the two input op-amps draw no current, that same amount of current through

Rgain must be going through the two "R" resistors above and below it. This produces a

voltage drop between points 3 and 4 equal to:

The regular differential amplifier on the right-hand side of the circuit then takes this

voltage drop between points 3 and 4, and amplifies it by a gain of 1 (assuming again

that all "R" resistors are of equal value). Though this looks like a cumbersome way to

build a differential amplifier, it has the distinct advantages of possessing extremely

high input impedances on the V1 and V2 inputs (because they connect straight into the

noninverting inputs of their respective op-amps), and adjustable gain that can be set

by a single resistor. Manipulating the above formula a bit, we have a general

expression for overall voltage gain in the instrumentation amplifier:

Though it may not be obvious by looking at the schematic, we can change the

differential gain of the instrumentation amplifier simply by changing the value of one

resistor: Rgain. The overall gain can be changed by changing the values of some of the

other resistors, but this would necessitate balanced resistor value changes for the

circuit to remain symmetrical. Please note that the lowest gain possible with the above

circuit is obtained with Rgain completely open (infinite resistance), and that gain value

is 1.


17

Circuit Diagram

Observation











18

Instrumentation amplifier Design:

, R=________, Rgain=___________-


19

Procedure:


2. Set the input voltage using F.G .





20

RESULT:

Contents Marks obtained Signature Prelab test(20) Postlab test(20) Simulation(25) Circuit connection and result(35)

Total


21

Circuit diagram

Model graph


22

EX. NO: 4 DATE: _ _ /_ _ / 2010

ACTIVE LOWPASS, HIGHPASS AND BANDPASS FILTERS.

AIM

To design an active low pass, high pass and band pass filter Using Op-Amp &

test its performance.

APPARATUS REQUIRED

S.No Components Range Quantity 1. Op-amp IC 741 1 2. Resistors 3. Capacitor O.01µf 2 4. CRO 1 5. Power Supply ± 15V 1 6. Probe 2 7. Bread Board 1

Thoery

LPF: A LPF allows only low frequency signals up to a certain break-point fH to pass

through, while suppressing high frequency components. The range of frequency

from 0 to higher cut off frequency fH is called pass band and the range of frequencies

beyond fH is called stop band.

Design Procedure:

1. Choose the cutoff frequency wc or fc

2. Pick c1, choose value <=0.1 µF

3. Make C2=2C1

4. Calculate R=0.707/wcC1

5. Choose Rf=2R


23

LPF Design:

Procedure:

LPF:

1. Connections are given as per the circuit diagram.

2. Input signal is connected to the circuit from the signal generator.

3. The input and output signals of the filter channels 1 and 2 of the CRO are

connected.

4. Suitable voltage sensitivity and time-base on CRO is selected.

5. The correct polarity is checked.

6. The above steps are repeated for second order filter


24

Tabulation Second order LPF Vin= S.No Frequency (Hz) O/p voltage(v) Gain=Vo/Vin Gain=20log(Vo/Vin)


25

HPF:

A high-pass filter, or HPF, is an LTI filter that passes high frequencies well but

attenuates (i.e., reduces the amplitude of) frequencies lower than the filter's cutoff

frequency. The actual amount of attenuation for each frequency is a design parameter

of the filter. It is sometimes called a low-cut filter or bass-cut filter.

Design Procedure:

1.Choose a cutoff frequency wc or fc.

2. Let C1=C2=C and choose a convenient value.

3. Calculate R1 from R1=1.414/wcC

4. Select R2=(1/2)R1

5 . To minimize dc offset , let Rf=R1

Design of HPF


26

Circuit diagram:

Model graph:


27

Tabulation Second order HPF Vin=

Procedure:

1. Connections are given as per the circuit diagram.

2. Input signal is connected to the circuit from the signal generator.

3. The input and output signals of the filter channels 1 and 2 of the CRO are

connected.

4. Suitable voltage sensitivity and time-base on CRO is selected.


6. The above steps are repeated for second order filter.

S.No Frequency (Hz) O/p voltage(v) Gain=Vo/Vin Gain=20log(Vo/Vin)


28

Circuit diagram:

Model graph


29

BPF:

A band-pass filter is a device that passes frequencies within a certain range and

rejects (attenuates) frequencies outside that range.

BPF Design:


30

Circuit diagram:

Model graph:


31

Tabulation:- BPF Vin= S.No Frequency (Hz) Vo(volts) Gain=20log(Vo/Vin)

Procedure:

BPF:-

1. The input signal is connected to the circuit from the signal generator.

2. The input and output signals are connected to the filter.

3. The suitable voltage is selected.


5. The steps are repeated.


32

RESULT:

Contents Marks obtained Signature Prelab test(20) Postlab test(20) Simulation(25) Circuit connection and result(35)

Total


33

Circuit Diagram

Observation

Output:




.

2

+10V

IC741

R

+

CRO

C

3

–10V

10KΩΩΩΩ

R1

R2

11.6ΩΩΩΩ

VO4

7–

6

10 kΩΩΩΩ

0.05µf


34

Ex. No 5 DATE: _ _ /_ _ / 2010

Astable ,Monostable Multivibrators and Schmitt trigger using op-amp

Aim

To design Astable, monostable Multivibrators and Schmitt trigger using op-

amp and plot its waveforms.

Apparatus Required:

S.No Component Range Quantity

1. Op amp IC 741 1

2. DTS (0-30) V 1

3. CRO 1

4. Resistor 1

5. Capacitors – –

6. Diode IN4001 2

7. Probes – 1

THEORY:

ASTABLE MULTIVIBRATOR:

Multivibrators are a group of regenerative circuits that are used extensively in

timing applications. It is a wave shaping circuit which gives symmetric or asymmetric

square output. It has two states either stable or quasi- stable depending on the type of

multivibrator.

Astable multivibrator is a free running oscillator having two quasi-stable states.

Thus, there is oscillations between these two states and no external s i g n a l a r e

required to produce the change in state.


35

Astable Multivibrator:

Design:

T = 2RC

R1= 1.16 R2

Given fo = _______KHz

Frequency of Oscillation fo = 1 / 2 RC if R1 = 1.16R2

Let R2 = 10 K

R1 = 10

Let C = 0.05 F

R = 1 / 2 fC = 1/ (2


36

MONOSTABLE MULTIVIBRATOR:

Monostable multivibrator is one, which generates a single pulse of specified

duration in response to each external trigger signal. It has only one stable state.

Application of a trigger causes a change to the quasi-stable state. An external trigger

signal generated due to charging and discharging of the capacitor produces the

transition to the original stable state

Design:

Monostable Multivibrators:

β = R2/R1+R2 [ = 0.5 & R1 = 10 K]

Find R2 = ; R3 = 1K; R4 = 10K;

Let F =_____KHz ; C= 1mfd; C4 = 0.1mfd

Pulse width, T = 0.69RC

Find R =


37

Circuit Diagram

Model graph:

CRO

+

–

+10V

7

4

-10V

2

3

IC741

R

Vββββsat

C4 D2

R4

D1C

VC

6R3

VO

R1

R2

Vin

Vin

VC

VO

Vsat

Vββββsat

VD

t

t

t

T–V sat

TP


38

Observation

Input:




Output:




Procedure:

Astable multivibrator

1. Make the connections as shown in the circuit diagram

2. Keep the CRO channel switch in ground and adjust the horizontal line on the x

axis so that it coincides with the central line.

3. Select the suitable voltage sensitivity and time base on the CRO.

4. Check for the correct polarity of the supply voltage to op-amp and switch on

power supply to the circuit.

5. Observe the waveform at the output and across the capacitor. Measure the

frequency of oscillation and the amplitude. Compare with the designed value.

6. Plot the Waveform on the graph.

Monostable Multivibrator:

1. Make the connections as shown in circuit diagram.

2. A trigger pulse is given through differentiator circuit through pin no.3

3. Observe the pulse waveform at pin no.6 using CRO and note down the time

period.

4. Plot the waveform on the graph.


39

Circuit Diagram

Model Graph

Vin

+12V

R1

-12V

R2

0

+

-

3

26

74

RL = 10K


40

SCHMITT TRIGGER:

If the input to a comparator contains noise, the output may be erractive when

vin is near a trip point. For instance, with a zero crossing, the output is low when vin is

positive and high when vin is negative. If the input contains a noise voltage with a peak

of 1mV or more, then the comparator will detect the zero crossing produced by the

noise.

This can be avoided by using a Schmitt trigger, circuit which is basically a

comparator with positive feedback.

Because of the voltage divider circuit, there is a positive feedback voltage.

When OPAMP is positively saturated, a positive voltage is feedback to the non-

inverting input; this positive voltage holds the output in high stage. (vin< vf). When the

output voltage is negatively saturated, a negative voltage feedback to the inverting

input, holding the output in low state.

Schmitt Trigger:

Design

VCC = 12 V; VSAT = 0.9 VCC; R1= 47KΩ; R2 = 120Ω

VUT = + [VSAT R2] / [R1+R2] & VLT = - [VSAT R2] / [R1+R2] &

HYSTERESIS [H] = VUT - VLT


41

Observation:





For square wave input:




Upper Threshold voltage , VUT =

Lower Threshold voltage , VLT =

Hysteresis voltage, VH =

Procedure

1. Connect the circuit as shown in the circuit

2. Set the input voltage as 5V (p-p) at 1KHz. (Input should be always less than Vcc)

3. Note down the output voltage at CRO

4. To observe the phase difference between the input and the output, set the CRO

in dual Mode and switch the trigger source in CRO to CHI.

5. Plot the input and output waveforms on the graph.


42

RESULT:


Signature

with Date

Simulation (20)


Result (10)


Total (100)


43

Wein Bridge Oscillator:- Circuit Diagram:-

CRO

+

–

+10V

7

6

4

-10V

2

3

ICY41

R1=10 kΩΩΩΩ Rf =20 kΩΩΩΩ

3.2kΩΩΩΩR

C0.05 µµµµf

3.2kΩΩΩΩR = C 0.05µµµµf

VO

Model Graph:

t

+ Vp

V O

–Vp

Observation: Peak to peak amplitude of the output = volts.

Frequency of oscillation = Hz.


44

EXP.NO.6:- DATE: _ _ /_ _ / 2010

Phase shift and Wien bridge oscillators Aim:

To design the following sine wave oscillators

a) Wein Bridge Oscillator with the frequency of 1 KHz.

b) RC Phase shift oscillator with the frequency of 200 Hz.

Components Required:


1. Op-amp IC 741 1



4. Resistors

5. Capacitors

6 CRO (0-30) MHz 1

7 Probes -- --

THEORY:

WEIN BRIDGE OSCILLATOR:

A Wien bridge oscillator is a type of electronic oscillator that generates sine

waves. The bridge comprises four resistors and two capacitors. It can generate a large

range of frequencies. The frequency of oscillation is given by:

F = 1/2 RC


45

Circuit Diagram:-

CRO

+

–

+10V

7

6

4

-10V

2

3

IC741

R1 1 mΩΩΩΩ

3.3kΩΩΩΩ

C

VO 0.01µµµµf

CC

RRR 3.3kΩΩΩΩ3.3kΩΩΩΩ

0.01µµµµf 0.01µµµµf

32kΩΩΩΩ

33kΩΩΩΩ Rf

DRB

Model Graph: VO

t

Observation:

Peak to peak amplitude of the sine wave = Volts

Frequency of Oscillation (obtained) = Hz.


46

RC Phase Shift Oscillators: Design:

Frequency of oscillation fo = 1/(√6*2*Π*RC)

Av = [Rf/R1] = 29

R1 = 10 R

Rf = 29 R1

Given fo = 200 Hz.

Let C = 0.1µF

( )( )6

R 1 / 6 * 2 * fo * C

1 / 6 * 2 * * 200 * 0.1 *10

K

To prevent the loading of amplifier by RC network, R1 10R

R1 10 * K

Since Rf 29R1

Rf 29 *

M

−

= π

= π

= Ω

≥

∴ = − − − − − − = Ω

=

= − − − − − −

= Ω


47

RC PHASE SHIFT OSCILLATOR:

A phase-shift oscillator is a simple sine wave electronic oscillator. It contains

an inverting amplifier, and a feedback filter consisting of an RC network which 'shifts'

the phase by 180 degrees at the oscillation frequency.

The filter must be designed so that at frequencies above and below the

oscillation frequency the signal is shifted by either more or less than 180 degrees. This

results in constructive superposition for signals at the oscillation frequencies, and

destructive superposition for all other frequencies

The most common way of achieving this kind of filter is using three cascaded

resistor-capacitor filters, which produce no phase shift at one end of the frequency

scale, and a phase shift of 270 degrees at the other end. At the oscillation frequency

each filter produces a phase shift of 60 degrees and the whole filter circuit produces a

phase shift of 180 degrees. The mathematics for calculating the oscillation frequency

and oscillation criterion for this circuit are surprisingly complex, due to each R-C stage

loading the previous ones.

Equations Related to the Experiments:

a) Wein Bridge Oscillator Closed loop gain Av = (1+Rf/R1) = 3 Frequency of Oscillation fa = 1/(2πRC)

b) RC Phase shift Oscillator: Gain Av = [Rf/R1] = 29

Frequency of oscillation fa = 1 6 * 2 * * RCπ


48

Wein Bridge Oscillator: Design: Gain required for sustained oscillation is Av = 1/β = 3

(PASS BAND GAIN) (i.e.) 1+Rf/R1 = 3

∴ Rf = 2R1

Frequency of Oscillation fo = 1/2π R C

Given fo = 1 KHz

Let C = 0.05 µF

∴ R = 1/2 π foC

R = 3.2 KΩ

Let R1 = 10 KΩ ∴ Rf = 2 * 10 KΩ


49

Procedure:

Wein Bridge Oscillator

1. Connect the components as shown in the circuit.

2. Switch on the power supply and CRO.

3. Note down the output voltage at CRO.

4. Plot the output waveform on the graph.

5. Redesign the circuit to generate the sine wave of frequency 2 KHz.

6. Compare the output with the theoretical value of oscillation.

RC Phase shift Oscillator

1. Connect the circuits as shown in the circuit

2. Switch on the power supply.

3. Note down the output voltage on the CRO.

4. Plot the output waveforms on the graph.

5. Redesign the circuit to generate the sine wave of 1 KHz.

6. Plot the output waveform on the graph.

7. Compare the practical value of the frequency with the theoretical value.

Result:


Signature

With Date

Simulation (20)


Result (10)


Total (100)


50

EXP.NO: 7 DATE: _ _ /_ _ / 2010

Astable and monostable multivibrators

Aim:

To design and test an astable and monostable multivibrators using ne555 timer.

Apparatus Required:


1. 555 TIMER 1

2. Resistors 3.3K, 6.8k 1

3. Capacitors 0.1 F 0.01 F 2

4. Diode In4001 1

5. CRO 1

6. Power

supply

15 V 1

7. Probe 2

8. Bread Board 1

Astable Multivibrators using 555

Fig shows the 555 timer connected as an Astable Multivibrators. Initially, when

the output is high. Capacitor C starts charging towards Vcc through RA and RB. As soon

as capacitor voltage equals 2/3 Vcc upper comparator (UC) triggers the flip flop and

the output switches low. Now capacitor C starts discharging through RB and transistor

Q1.


51

Circuit Diagram

Model Graph

Vc

t(ms)

VUT

VUT

t high

tlow

t(ms)

VO

VOD

RA

6.8k

Vcc

+5 V

0.01µµµµF

0. 1µµµµF

RB

3.3k

7

2

6

1 5

8 4

3

5555


52

Observation:

For output at pin no.3:Peak to peak amplitude of the input = volts.



For capacitor input: Peak to peak amplitude of the output = volts.

Charging time = sec

Discharging time = sec



DESIGN:

Design an Astable Multivibrators for a frequency of ______KHz with a duty

cycle ratio of D = 50

fo = 1/T = 1.45 / (RA+2RB)C

Choosing C = 1 F; RA = 560

D = RB / RA +2RB= 0.5 [50%]

RB = ______


53

When the voltage across C equals 1/3 Vcc lower comparator (LC), output

triggers the flip-flop and the output goes high. Then the cycle repeats.

The capacitor is periodically charged and discharged between 2/3 Vcc and 1/3

Vcc respectively. The time during which the capacitor charges form 1/3 Vcc to 2/3 Vcc is

equal to the time the output is high and is given by

T c = 0.69(RA+RB)C (1)

Where RA and RB are in Ohms and C is in farads.

Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal

to the time the output is low and is given by

T d = 0.69 RB C (2)

The total period of the output waveform is

T = T c + T d = 0.69 (RA + 2RB) C (3)

The frequency of oscillation

fo = 1 / T =1.45 / (RA+2RB)C (4)

Eqn (4) shows that fo is independent of supply voltage Vcc

The duty cycle is the ratio of the time td during which the output is low to the

total time period T. This definition is applicable to 555 Astable Multivibrators only;

conventionally the duty cycle ratio is defined as the ratio as the time during which the

output is high to the total time period.

Duty cycle = td× T × 100

RB + RA+ 2RB × 100

To obtain 50 % duty cycle a diode should be connected across RB and RA must

be a combination of a fixed resistor and a potentiometer. So that the potentiometer

can be adjusted for the exact square waves


54

Circuit Diagram:

Model Diagram:

VO

RA

10k

Vcc

+5 V

0.01µµµµF

0. 1µµµµF

7

6

1 5

8 4

3

555

2Trigger i/p

0.01µµµµF

Vcc

0 V

(i) Trigger input

(ii) Output

(ii)Capacitor

Voltage

0 V

0 V

Vcc


55

Observation

For trigger input:




For output at pin no.3:




For capacitor voltage:


Charging time = sec

Discharging time = sec


Design:

Given a pulse width of duration of 100 s

Let C = 0.01 mfd; F = _________KHz

Here, T= 1.1 RAC

So, RA =


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Monostable Multivibrators using 555

Monostable Multivibrators has one stable state and other is a quasi stable state.

The circuit is useful for generating single output pulse at adjustable time duration in

response to a triggering signal. The width of the output pulse depends only on

external components, resistor and a capacitor.

The stable state is the output low and quasi stable state is the output high. In the

stable state transistor Q1 is ‘on’ and capacitor C is shorted out to ground. However

upon application of a negative trigger pulse to pin2, Q1 is turned ‘off’ which releases

the short circuit across the external capacitor C and drives the output high. The

capacitor C now starts charging up towards Vcc through RA. However when the

voltage across C equal 2/3 Vcc the upper comparator output switches form low to high

which in turn drives the output to its low state via the output of the flip flop. At the

same time the output of the flip flop turns Q1 ‘on’ and hence C rapidly discharges

through the transistor. The output remains low until a trigger is again applied. Then

the cycle repeats.

The pulse width of the trigger input must be smaller than the expected pulse

width of the output. The trigger pulse must be of negative going signal with amplitude

larger than 1/3 Vcc. The width of the output pulse is given by,

T = 1.1 RAC


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Procedure:

1. Rig-up the circuit of 555 Astable Multivibrators as shown in fig with the

designed value of components.

2. Connect the CRO probes to pin 3 and 2 to display the output signal and the

voltage across the timing capacitor. Set suitable voltage sensitively and time-

base on the CRO.

3. Switch on the power supply to CRO and the circuit.

4. Observe the waveforms on the CRO and draw to scale on a graph sheet.

Measure the voltage levels at which the capacitor starts charging and

discharging, output high and low timings and frequency.

5. Switch off the power supply. Connect a diode across RB as shown in dashed

lines in fig to make the Astable with 50 duty cycle ratio. Switch on the power

supply. Observe the output waveform. Draw to scale on a graph sheet.

Procedure:


1. Rig-up the circuit of 555 monostable Multivibrators as shown in fig with the

designed value of components.

2. Connect the trigger input to pin 2 of 555 timer form the function generator.

3. Connect the CRO probes to pin 3 and 2 to display the output signal and the

voltage across the timing capacitor. Set suitable voltage sensitively and time-

base on the CRO.

4. Switch on the power supply to CRO and the circuit.

5. Observe the waveforms on the CRO and draw to scale on a graph sheet.

Measure the voltage levels at which the capacitor starts charging and

discharging, output high and low timings along with trigger pulse.


58

Result:


Signature

With Date

Simulation (20)


Result (10)


Total (100)


59

BLOCK DIAGRAM

Circuit diagram


60

EXP.NO: 8 DATE: _ _ /_ _ / 2010

PLL characteristics and its use as Frequency Multiplier.

Aim:

To design a PLL characteristics and its use as Frequency Multiplier.

Apparatus Required:


1. IC NE565,74c90 1

2. Resistors

3. Capacitors

5. CRO 1

6. Power

supply

15 V 1

7. Probe 2

8. Bread Board 1

Theory

Phase locked loops are used for frequency control. They can be configured as

frequency multipliers, demodulators, tracking generators or clock recovery circuits.

Each of these applications demands different characteristics but they all use the same

basic circuit concepts. The block diagram consist of a feedback control system that

controls the phase of a voltage controlled oscillator(VCO). The input signal is applied

to one input of phase detector. The other input is connected to the output of a divide

by N counter. Normally the frequencies of both signals will be nearly the same. The

output of the phase detector is a voltage, proportional to the phase difference


61

between the two inputs. This signal is applied to the phase difference between the

two inputs, this signal is applied to the loop filter. The loop filter determines the

dynamic characteristics of the PLL. The filtered signal controls the VCO. Note that the

output of the VCO is at a frequency that is N times the input supplied to the frequency

reference input. This output signal is sent back to the phase detector via a divided by N

counter. Normally the loop filter is designed to match the characteristics required by

the application of the PLL. If the PLL is to acquire and track a signal bandwidth of the

loop filter will be greater than if it expects a fixed input frequency. The frequency

range which the PLL will accept and lock on is called the capture range. Once the PLL

is locked and tracking a signal the range of frequencies that the PLL will follow is

called track range. Generally the tracking range is larger than the capture range. The

loop filter also determines how fast the signal frequency can change and still maintain

lock. This is the maximum slewing rate. The narrower the filters bandwidth the

smaller the achievable capture range.


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Circuit Diagram


63

PLL characteristics:

Free running Mode

Peak to peak amplitude of free running =

Frequency of free running =

Time =

Locked mode

Peak to peak amplitude of locked mode =

Frequency of locked mode =

Time =

Output

Peak to peak amplitude of output =

Frequency of output =

Time =

Frequency Multiplier

Input:

Peak to peak amplitude of input =

Frequency =

Time period =

Output:

Peak to peak amplitude of output =

Frequency =

Time period =


64

Result:


Signature

With Date

Simulation (20)


Result (10)


Total (100)


65

CIRCUIT DIAGRAM:

Low Voltage Regulator

430

1k

0.52N3055Unregulated

DC Power

Supply 12 11

6

5

R1

R2

V+ VcVo

CL

CS

INV

COMPV-

NI

Vref

0.1

UF

TIP122

100pF

Rsc

10

2

3

4

137

Load

A

+ -

V

+

-

DESIGN:

Output voltage → VO

Reference voltage→ Vref

Rprotect → Minimum Resistance to protect the output from short circuit.

Low Voltage Regulator:

Given: Vo=5V, Vref = 7.15 V To calculate R1, R2, R3 and Rsc.

Vo = Vref ( R2 / ( R1 + R2 ) )

5 / 7.15 = ( R2 / ( R1 + R2 ) )

(R1 + R2) 0.699= R2

0.699R1 = 0.301 R2, R1 = 0.4306 R2

Select R2 = 1 KΩΩΩΩ

R1 = 1 KΩ * 0.4306 = 430Ω

R1 = 430ΩΩΩΩ R3 = R1 * R2 / (R1 + R2), R3 = 430.6 *1000 / (430.6+1000)

R3 = 300ΩΩΩΩ

Rsc = Vsense / Ilimit = 0.5 /1A = 0.5Ω , Rsc = 0.5ΩΩΩΩ

LM723


66

EXP.NO.9: DATE: _ _ /_ _ / 2010

DC power supply

AIM:

To design a DC power supply using LM317 and LM723

COMPONENTS REQUIRED:

S.NO COMPONENTS SPECIFICATION QUANTITY

1. Transistors TIP122,2N3055 1 each

2. Integrated Circuit LM723 1

3. Digital Ammeter ( 0 – 10 ) A 1

4. Digital Voltmeter ( 0 – 20 ) V 1

5. Variable Power Supply ( 0 – 30 ) V-2A 1

6.

Resistors 300Ω,430Ω,1KΩ,678KΩ,678Ω

1Ω

1 each

2

7. Capacitors 0.1µF,100pF 1 each

9. Rheostat ( 0 – 350 ) Ω 1

THEORY

GENERAL PURPOSE REGULATOR 723

723 IC is a general purpose regulator, which can be adjusted over a wide range

of both positive and negative regulated voltage. Though the IC is a low current device,

current can be boosted to provide 5 amps or more.


67

CIRCUIT DIAGRAM:

High Voltage Regulator:

High Voltage Regulator:

Given : Vo=12V, Vref = 7.15 V

To calculate R1, R2, R3 and Rsc.

Vo = Vref ( 1 + (R1 / R2) )

12 / 7.15 = 1+ (R1 / R2)

(12 / 7.15) - 1 = (R1 / R2)

(R1 / R2) = 0.678

Select R2 = 1 KΩΩΩΩ

R1 = 1 KΩ * 0.678 = 678Ω

R1= 678ΩΩΩΩ

Rsc = Vsense / Ilimit = 0.5 /1A = 0.5Ω

Rsc = 0.5ΩΩΩΩ


68

It has short circuit protection and no short circuit current limits. It can operate with an

input voltage from 9.5V to 40V and provide output voltage from 2V to 37V.

723 IC has two sections. One section provides a fixed voltage of 7V at the terminal Vref. Other section consists of an error amplifier and two transistors. These two sections are not internally connected.

LOW VOLTAGE REGULATOR

Vref point is connected through a resistance to the non-inverting terminal and

the output if feedback to the inverting terminal of the error amplifier. If the output

voltage becomes low, the voltage at the inverting terminal of error amplifier also goes

down. This makes the output of the error amplifier becomes more positive, thereby

driving transistor more into conduction. This reduces voltage across the transistor and

drives more current into the load causing voltage across load to increase.

HIGH VOLTAGE REGULATOR

If it is desired to produce regulated output voltage greater than 7V, a small

change should be made in the circuit for low voltage regulator. The non-inverting

terminal is connected directly to Vref. So the voltage at the non-inverting terminal is

Vref. The error amplifier operates as a non-inverting amplifier.

PROCEDURE:

LOW VOLTAGE REGULATOR:

Line Regulation:

1. Give the circuit connection as per the circuit diagram.

2. Set the load Resistance to give load current of 0.25A.

3. Vary the input voltage from 7V to 18V and note down the corresponding output

voltages.


69

4. Similarly set the load current (IL) to 0.5A & 0.9A and make two more sets of

measurements.

Tabulation of the Measurements:

LOW VOLTAGE REGULATOR:

Line Regulation:

S.No. Load Resistance RL1 = Load Resistance RL2 = Load Resistance RL3 =

Input

Voltage

Vin(Volts)

Output

Voltage

VL(Volts)

Input

Voltage

Vin(Volts)

Output

Voltage

VL

(Volts)

Input

Voltage

Vin(Volts)

Output

Voltage

VL (Volts)


70

Load Regulation:

S.No. Input Voltage Vin1 = Input Voltage Vin2 = Input Voltage Vin3 =

Output

Current

IL ( A )

Output

Voltage

VL (Volts)

Output

Current

IL ( A )

Output

Voltage

VL (Volts)

Output

Current

IL ( A )

Output

Voltage

VL (Volts)

Load Regulation:

1. Set the input voltage to 10V.

2. Vary the load resistance in equal steps from 350Ω to 5Ω and note down the

corresponding output voltage and load current.

3. Similarly set the input voltage (Vin) to 14V & 18V and make two more sets of

measurements.

Lab Report:

1. Plot the line regulation by taking Input Voltage (Vin) along X-axis and Output

Voltage (VL) along Y-axis for various load currents.

2. Plot the load regulation by taking load current (IL) along X-axis and Output

Voltage (VL) along Y-axis for various input voltages.

3. Calculate its % Voltage Regulation using the formula.


71

HIGH VOLTAGE REGULATOR:

Line Regulation:

1. Give the circuit connection as per the circuit diagram.

2. Set the load Resistance to give load current IL of 0.25A.

3. Vary the input voltage from 7V to 18V and note down the corresponding output

voltages.

4. Similarly set the load current (IL) to 0.5A & 0.9A and make two more sets of

measurements.

Load Regulation:

1. Set the input voltage to 10V.

2. Vary the load resistance in equal steps from 350Ω to 15Ω and note down the

corresponding output voltage and load current.

3. Similarly set the input voltage (Vin) to 14V & 18V and make two more sets of

measurements.


72

HIGH VOLTAGE REGULATOR:

Line Regulation:

S.No. Load Resistance RL1 = Load Resistance RL2 = Load Resistance RL3 =

Input

Voltage

Vin(Volts)

Output

Voltage

VL(Volts)

Input

Voltage

Vin(Volts)

Output

Voltage

VL

(Volts)

Input

Voltage

Vin(Volts)

Output

Voltage

VL(Volts)


73

Load Regulation:

S.No. Input Voltage Vin1 = Input Voltage Vin2 = Input Voltage Vin3 =

Output

Current

IL ( A )

Output

Voltage

VL(Volts)

Output

Current

IL ( A )

Output

Voltage

VL(Volts)

Output

Current

IL ( A )

Output

Voltage

VL(Volts)

Lab Report:

1. Plot the line regulation by taking Input Voltage (Vin) along X-axis and Output

Voltage (VL) along Y-axis for various load currents.

2. Plot the load regulation by taking load current (IL) along X-axis and Output

Voltage (VL) along Y-axis for various input voltages.

3. Calculate its % Voltage Regulation using the formula.

Calculation of % Voltage Regulation:

% Voltage Regulation = ( Vdc ( NL ) - Vdc ( FL ) ) / Vdc ( FL )

Vdc (NL) = D.C. output voltage on no load

Vdc (FL) = D.C. output voltage on full load


74

Model Graph:

Line Regulation: Load Regulation:

Input Voltage Vs Output Voltage: Output Current Vs Output Voltage:

I L

V 0 V 0

V in

Load regulation Line regulation


75

Result:


Signature

With Date

Simulation (20)


Result (10)


Total (100)

Documents

Inverting amplifier: [Closed Loop Configuration]chettinadtech.ac.in/storage/15-01-03/15-01-03-10-08-05-Devilatha.pdf · Inverting amplifier: [Closed Loop Configuration] ... To design