Introduction to SDRAM

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SDRAMSynchronusSynchronusDynamic Random Access MemoryDynamic Random Access Memory

Presented by :

Lakshmi Narayanan.G


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Introduction

DRAM has a single transistor cell structure.

Extremely dense memory arrays fabricated in a single device withrelatively small footprint.

Needs Frequent refreshing.

Conventional DRAM is controlled asynchronously.

The system designer to manually insert wait states to meet the

specifications of the device. Timing depends on the speed of the DRAM and is independent of

the system bus speed.
http://home/LNG/SDRAM%20ppt.odp#Slide%203http://home/LNG/SDRAM%20ppt.odp#Slide%203


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DRAM Structure


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SDRAM :

Synchronous Dynamic Random Access Memory.

It is a type of DRAM which operates in synchronization with anexternal input clock.

SDRAM and DRAM have almost identical basic configurationsinside the memory.

Synchronization helps to achieve higher bandwidth and greatlysimplify interface timing.


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Functional Diagram of SDRAM


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SDRAM Pins

CLK: Clock inut given to the SDRAM Memory chip

CKE: Clock enable signal. The Memory Chip will be FREEZED untill this ismade high.

If SDRAM is idle, when CKE goes low the SDRAM automatically enterspower-down mode, consuming minimal power until CKE is raised again.

If CKE is lowered at the same time as an auto-refresh command is sent to theSDRAM, the SDRAM enters self-refresh mode. This is like power down, butthe SDRAM uses an on-chip timer to generate internal refresh cycles as

necessary


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SDRAM Pins

Chip Select (CS) : When this signal is high, the chip ignores all other inputs(except for CKE), and acts as if a NOP command is received.

Data Mask (DQM) : When high, these signals suppress data I/O. Whenaccompanying write data, the data is not actually written to the DRAM. Whenasserted high two cycles before a read cycle, the read data is not output fromthe chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.


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Row Address Strobe (RAS) : The RAS control input is used to latch the rowaddress and to begin a memory cycle. RAS is required at the beginning ofevery operation and must remain selected for a predetermined minimumamount of time.

Column Address Strobe (CAS) : CAS is used to latch the column addressand to initiate the write or read operation. CAS may also be used to trigger aCAS-before-RAS refresh cycle. This refresh cycle requires CAS to remainselected for a predetermined minimum time period. For most memoryoperations, CAS must remain deselected for a predetermined minimumamount of time.

SDRAM Pins


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Write Enable (WE) : The WE control input is used to select a read or writeoperation. The operation performed is determined by the state of the WE

when CAS is taken active. It is important that setup and hold timingspecifications are met, with respect to CAS, to assure that the correctoperation is selected.

Output Enable (OE) During a read operation, OE is set active to assure datadoes not appear at the I/Os until required. During a write cycle, OE isignored.

Address The address inputs are used to select memory locations in the array.The address inputs are used to select both the desired row and columnaddresses.

SDRAM Pins


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Addressing DRAM


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Synchronous Control LogicAll inputs and outputs are synchronous with the clock. SDRAMs latch eachcontrol signal at the transition of the input clock and all input/output data aresynchronized with the clock signal. Controls are made easier by synchronizingthe memory clock with the system clock.

Controls with CommandsA command is a combination of the logic levels of control signals. Typicalcommands include: Activate Command, Read and Write Command, Pre-chargeCommand, etc. The conventional DRAM is also controlled with control signals,however, it does not have the ability to execute commands.

SDRAM Features


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Multiple Bank Architecture

The SDRAM memory is separated into several banks, so that the controls canbe performed by the bank. For example: since the interleave control can beperformed on each bank separately, the pre-charge time is seemingly hidden.

Refresh ModesThere are two types of refresh operations in the SDRAM: Auto-Refresh and Self-

Refresh. The logic state of the CKE control signal determines which refreshoperation is used. The Auto Refresh mode uses an internal refresh counter andrequires no external addressing. As compared to the Self Refresh mode which isused during periods when the SDRAM is in the low power mode, allowing theSDRAM to refresh its self.

SDRAM Features


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Memory and I/O Power SuppliesSince large amounts of current are sourced and sunk into the SDRAM duringread and write operations, switching noise can be generated which may have anadverse effect on the memory array. Separate power inputs are provided for theI/O signals and the memory array, isolating the memory cells from possible datacorruption.

Selectable CAS LatencyCAS Latency is the number of clock cycles that occur from the input of acommand to the output of data. The number of clocks is set in the ModeRegister.

SDRAM Features


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Selectable Burst LengthThe burst length is the number of words that can be continuously input/output

for a read or write operation.

Mode RegisterThe mode register can be set with the CAS latency and burst length. registerretains data until it is rewritten or the device loses power. This register retainsdata until it is rewritten or the device loses power.

SDRAM Features


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READ operation


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Precharge & Activation


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Basic operations of the SDRAM, such as Read, Write andRefresh, are initiated by loading control commands into thedevice. The most common control commands of the SDRAM are:

Row Address Strobe (RAS)

Column Address Strobe (CAS) Pre Charge CAS-before-RAS (CBR) Refresh Self Refresh


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The Command Set

- Ignore Command (DELS): When this command is set (CS = High), the

SDRAM ignores command input at the clock. However, the internal status is

held.

- No Operation (NOP): This command is not an execution command.

However, the internal operations continue.

- Column Address Strobe (CAS) and Read Command: The CAS command

starts a read operation. In addition, the start address of a burst read is

determined by the column address and the bank select (BS) address. After the

read operation, the output buffer becomes High-Z.


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- Read with Auto-Precharge: The Read command automatically performs a pre-

charge operation after a burst read with a burst length of 1, 2, 4, or 8.

- Column Address Strobe (CAS) and Write Command: This command starts a

write operation. When the burst write mode is selected, the column address and

the bank select address becomes the burst write start address. When the single

write mode is

selected, data is only written to the location specified by the column address andbank select address.

- Write with Auto-Precharge: This command automatically performs a precharge

operation after a burst write with a length of 1, 2, 4, or 8, or after a single write

operation.


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- Row Address Strobe (RAS) and Bank Activate: This command activates the

bank that is selected and determines the row address.

- Precharge Select Bank (PRE): This command starts a precharge operation on

the bank selected.

- Refresh (REF/SELF): This REF/SELF command starts the refresh operation.

There are two types of refresh operations which can be carried out with the

REF/SELF command: auto-refresh, and self-refresh.

- Mode Register Set (MRS): The SDRAM has a mode register which is

programmed by the user to select the read latency, burst length, and burst type

used during read/write operations. After the power-up sequence, the MRS

command must be issued to initialize the device. This command is issued by

setting the RAS, CAS, CS and WE control inputs Low prior to the positive edge ofthe clock. The data to be loaded into the Mode Register is applied to the address

pins. During the MRS cycle, no other command can be issued. If it is necessary to

modify the functionality of the device, it can be altered by re-programming the

Mode Register with a MRS command.


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Documents

Introduction to SDRAM