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Topics to Cover
• The SDRAM Roadmap
• Transitioning from SDR to DDR
• DDR-I 400 Overview
• Market overview
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SDRAM Evolution
Simple,incrementalsteps
“DDR I”
“DDR II”
1100MB/s
PC133
DDR2662100MB/s DDR3332700MB/s DDR400
3200MB/s
1600MB/s
DDR200
“SDR”
DDR5334300MB/s
DDR400?
3200MB/s
MainstreamMemories
DDR6675400MB/s
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Key to System Evolution• Never over-design!• Implement just enough new features to achieve
incremental improvements• Use low cost high volume infrastructure
– Processes– Packages– Printed circuit boards
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From SDR to DDR
Signaling& Power
DifferentialClocks
DataStrobe
Prefetch2
WriteLatency
Prefetch2
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Prefetch• Today’s SDRAM architectures assume an inexpensive DRAM
core timing
• DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits: increase performance without increasing core timing costs
• DDR II (DDR400, DDR533, DDR667) prefetches 4 bits internally, but keeps DDR double pumped I/O
• DDR-I 400 is a prefetch-2 architecture
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Prefetch DepthCK
READ
Core access time
Costs $$$
Essentially free
dataSDR: Prefetch 1
DDR-I: Prefetch 2
DDR-II: Prefetch 4
Costs $$$
Column cycle time
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Prefetch Impact on Cost
SDR
DDR-II
Pre-fetch
2
1
1
2
4
4
100
133
200
266
400
533
10 ns
7.5 ns
10 ns
7.5 ns
10 ns
7.5 ns
SDRAM Family
DataRate
CycleTime
Comparable to DDR266 in cost
DDR-I
2 333 6 ns
2 400 5 ns
Starts to get REAL EXPENSIVE!
High Yield =Affordable
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DDR Data Timing• Data valid on rising & falling
edges… “Double Data Rate”• Source Synchronous; Data
Strobe “DQS” travels with data
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From SDR to DDR
Signaling& Power
DifferentialClocks
DataStrobe
Prefetch2
WriteLatency
DifferentialClocks
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DDR Clocks• Differential clocks on adjacent traces• Timing is relative to crosspoint• Helps ensure 50% duty cycle
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Single Ended Clock
Clock high time
VREF
Clock low time
CK
Clock high time
VREF
Clock low time
CK
Normal balanced signal
Mismatched Rise & Fall signal Error!
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Differential Clock
Significantly reduced symmetry error
Clockhigh time
Clock low time
CK
Clock high time
Clock low time
CK
Normal balanced signal
Mismatched Rise & Fall signal
CK
CK
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From SDR to DDR
Signaling& Power
DifferentialClocks
DataStrobe
Prefetch2
WriteLatency
Signaling& Power
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DDR Signaling• SSTL_2 low voltage swing inputs
– 2.5V I/O with 1.25V reference voltage– Low voltage swing with termination– Rail to rail if unterminated
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Power = CV2f%#Factors:• Capacitance (C)• Voltage (V)• Frequency (f)• Duty cycle (%)• Power states
(# circuits in use)
Keys to lowpower design:
Reduce C and VMatch f to demandMinimize duty cycleUtilize power states
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Power: SDR DDR-I DDR-II
0
2
4
6
8
10
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Throughput per Second per Unit Power
PC-133@ 3.3V
DDR533@ 1.8V
DDR266@ 2.5V
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From SDR to DDR
Signaling& Power
DifferentialClocks
DataStrobe
Prefetch2
WriteLatency
DataStrobe
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Emphasis on “Matched”
• DM/DQS loading identical to DQ• Route as independent 8bit buses
DQ/DQS
DM
VREF
VREF
VREF
VREF
Disable
CONTROLLER DDR SDRAM
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64 = 8 x 8• 64bit bus is 8 sync’ed 8bit buses• Allows external “copper” flexibility• 8 buses resync upon entry to FIFO
8 DQ1 DM1 DQS
8bit Buffer 8bit Buffer
8 DQ1 DM1 DQS
x16 DDRSDRAM
x16 DDRSDRAM
x16 DDRSDRAM
64bit Memory Controller Internal FIFOSync to
Controllerclock
Copperfrom
controllerto SDRAMs
InsideController
x16 DDRSDRAM
8 DQ1 DM1 DQS
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From SDR to DDR
Signaling& Power
DifferentialClocks
DataStrobe
Prefetch2
WriteLatency
WriteLatency
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Write Latency• SDR had to keep inputs powered all the time• Adding Write Latency to DDR allowed inputs to be
powered off between commands• Flexible timing differences on data and address paths
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DDR-I vs DDR-II @ 400
“DDR I”
“DDR II”
DDR333
2700MB/sDDR400
3200MB/s
DDR400?
3200MB/s
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DDR-I 400 Summary• DDR-I is hard to design to 400 MHz data rate
– Lower yields• No JEDEC standard
• Prefetch-2, 2.5V signals, TSOP packages, write latency 1
– DDR-II makes it a lot easier• JEDEC standards & focus
• Prefetch-4, 1.8V signals, differential strobe
• On-die termination, BGA packages, write latency > 1
• Same plane referencing
• Few suppliers supporting DDR-I 400 market
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DDR-I 400 Conclusion• The JEDEC roadmap represents the industry
focus for mainstream products– DDR-I tops out at 333 MHz data rate– DDR-II starts at 400 MHz data rate
• This DOES NOT mean that DDR-I at 400 MHz data rate will not ship in volume
• It DOES mean that there will be price premiums for this speed bin
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Market Outlook
• DDR-I– DDR333 is the mainstream product for 2003– DDR-I 400 will be the premium market
• DDR-II– DDR-II designs under way now– DDR-II 400 & 533 will sample in 2003– DDR-II ramp begins in 2004
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Summary
• DDR has many improvements over SDR– Prefetch, differential clock, low voltage, data
strobe, write latency
• DDR-I 400 likely to stay a profitable niche• DDR-II volume products for 400 & 533 ramp
in 2004
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Thank You
