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Nano Packaging & Interconnect Lab. Introduction - 3D Integration & Through Silicon Via(TSV) ¾ Why TSV for 3D integration? Chip 3 Chip 2 Chip 1 Interposer 2 Interposer 1 Die attach film Substrate Wire bonding < 3 chips + 2 interposers stack with wire bonding> Chip 1 TSV Substrate TSV TSV Chip 2 Chip 3 Bump Underfill < 3 chips stack with TSV > ¾ Through silicon via (TSV) TSV Si chip 9 Vertical electrical interconnection passing through the silicon Source : STATS ChipPAC 9 Smaller package size 9 Short interconnect length 9 Pad area for wire bonding 9 Long looped Au wire

Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

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Page 1: Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

Nano Packaging & Interconnect Lab.

Introduction - 3D Integration & Through Silicon Via(TSV)

¾Why TSV for 3D integration?

Chip 3

Chip 2

Chip 1

Interposer 2

Interposer 1

Die attach film

Substrate

Wire bonding

< 3 chips + 2 interposers stack with wire bonding>

Chip 1 TSV

Substrate

TSV

TSV

Chip 2

Chip 3Bump

Underfill

< 3 chips stack with TSV >

¾ Through silicon via (TSV)

TSV Si chip

9 Vertical electrical interconnection passing through the silicon

Source : STATS ChipPAC

9 Smaller package size

9 Short interconnect length

9 Pad area for wire bonding

9 Long looped Au wire

Page 2: Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

Nano Packaging & Interconnect Lab.

Introduction - Former TSV Interconnection Methods & Limits

TSV

Dielectric polymer

<Cu-Sn Metal bonding> < Cu-Cu Metal/polymer hybrid bonding>Chip

Metal bump

ChipTSV

Metal bump

Substrate chip

TSV Chip

Metal bump

UnderfillSubstrate chip

ChipTSV

Metal bump

Dielectric polymer

ChipTSV

Metal bump

Substrate chip

Voids Cracks

• Long bonding time(< minutes)• Repeat of under-fill• Void trap during under-fill

• Long bonding time(30min)• Additional polymer patterning• Semi-solid state after polymer patterning

Page 3: Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

Nano Packaging & Interconnect Lab.

TCA

Silicon waferSi chip with

TCA

Dicing of TCA-applied wafer

Pressure & temperature

TCASi chip

Si wafer

TSV

*Patent issued : US6518097

TCA coated on releasing film

*Wafer-level lamination of TCA on the wafer

TSV & bumped wafer

Introduction - Why TSV Conducting Adhesives(TCAs)/Solder Joint?

¾ Bonding process with TCA

¾What is TCA?

TSV Conducting Adhesive+ +TSV

Chip

Cu pillar Solder bump

• Substitution of underfill• No need of patterning

Chip to wafer bonding using TCA/solder joint

Page 4: Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

Nano Packaging & Interconnect Lab.

Introduction - Why TCA/solder Hybrid Joint?

¾ Features of TCAs

Substrate chip

TCA

ChipTSV

Solder bump

TSV

TCA Solder bump

Chip

9 Curing temperature

9 Viscosity9 Short bonding time

9 No need of underfill& patterning

9 Gap filling by resin flow

• Joint stability

• Joint formation

Substrate chip

Page 5: Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

Nano Packaging & Interconnect Lab.

Experiments – Test Vehicles (TSV simulated SnAg coated Cu post bump)

¾ Micro-bumped chip

9 Substrate chip design

9 Bonding chip design

Height : 10/10 μm

Diameter : 40 μm

Material : Cu/SnAg2.5

• Dimension : 13 mm X 13 mm

• Pads : 5 daisy resistance & 4 joint resistance circuits

Pitch : 80 μm

• Dimension : 6 mm X 6 mm

• Bump

Single Bump Joint resistanceAt the corner

Daisy resistance

Cu pillar (10 μm)

SnAg bump (10 μm)

Page 6: Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

Nano Packaging & Interconnect Lab.

Experiments – TCAs Formulation

¾ Resin system

Thermosetting epoxy Thermoplastic resin+ +

¾ TCA formulation

Curing agent

TCA1 TCA2 TCA3 TCA4

Curing temperature (oC) 160 185 160 160

Min. viscosity (Pa·s) 450(130oC)

90(160oC)

3000(130oC)

600(120oC)

Curing speed @250oC(sec) 70 70 70 10

Curing accelerator+Thermo-mechanical

propertiesViscosityCuring

temperatureCuring speed

*Tg : 100 ~ 140 oC

Page 7: Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

Nano Packaging & Interconnect Lab.

20

40

60

80

100

50 100 150 200 25010

100

1000

10000

100000

1000000

Visc

osity

(|K|

* )

Temperature (oC)

Dai

sy re

sist

ance

(:)

Results - Effects of Curing of TCAs

9 TCA/solder hybrid joints were interconnected with the viscosity of 600 Pa·s.

Bonding conditionPressure : 16.32 MPaTemperature : 40~250 oC (5 oC/s)

9 Bonding with TCA29 Bonding with TCA1

20

40

60

80

100

50 100 150 200 25010

100

1000

10000

100000

1000000

Visc

osity

(|K|

* )

Temperature (oC)D

aisy

resi

stan

ce (:

)

(160 oC, 450 Pa·s @ 130 oC) (185 oC, 90 Pa·s @ 160 oC)

No bump interconnection

600 Pa·s @ 110 oC

¾ Real time viscosity & resistance change during the bonding

590 Pa·s @ 120 oC

Page 8: Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

Nano Packaging & Interconnect Lab.

20

40

60

80

100

50 100 150 200 25010

100

1000

10000

100000

1000000

Visc

osity

(|K|

* )

Temperature (oC)D

aisy

resi

stan

ce (:

)

Results – Effects of Viscosity of TCAs

9 Bonding with TCA1 9 Bonding with TCA3

9 TCA/solder hybrid joints with high viscosity TCA were interconnected preby the softening of the TCA resin.

50 100 150 200 25010

100

1000

10000

100000

1000000

Vis

cosi

ty (|K|

* )

Temperature (oC)

50

100

150

200

Dai

sy re

sist

ance

(:)

(160 oC, 3000 Pa·s @ 130 oC)(160 oC, 450 Pa·s @ 130 oC)

No bump interconnection

¾ Real time viscosity & resistance change during the bondingBonding conditionPressure : 16.32 MPaTemperature : 40~250 oC (5 oC/s)

Page 9: Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

Nano Packaging & Interconnect Lab.

20

40

60

80

100

50 100 150 200 25010

100

1000

10000

100000

1000000

Visc

osity

(|K|

* )

Temperature (oC)

Dai

sy re

sist

ance

(:)

Results - Joint Interconnection during the BondingBonding conditionPressure : 16.32 MPaTemperature : 40~250 oC (5 oC/s)

<Before bonding>

<Physical contact of the bumps> <Increase of the contact area>

<Metallurgical bonding>No bump

interconnection

¾ Bonding with TCA1(160 oC, 450 Pa·s @ 130 oC)

Page 10: Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

Nano Packaging & Interconnect Lab.

Result – 40 μm Fine Pitch Capability of TCA/solder Joints

¾ TCAs bonding with 40 μm pitch test vehicles

9 Chip specification

Height : 10/10 μmDiameter : 20 μm

Material : Cu/SnAg

Pitch : 40 μm

• Bump

40 μm 80 μm

Contact resistance (mΩ) 1.18 2

9 Joint resistance

Successful bonding of 40 μm pitch TCA/solder hybrid joints in 10 sec!

Page 11: Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

Nano Packaging & Interconnect Lab.

Result – Humidity Test

¾ 85 oC/85 %RH test

< Cross-sectioned image of the bumps after 500 hours of 85 oC/85 %RH test>

9 No failure was found until 300 h of the humidity test for TCA/solder hybrid joints.

TCA 1 (160 oC, 450 Pa·s @ 130 oC)Pressure : 16.32 MPaTemperature : 40~250 oC (5 oC/s)

0 20 40 60 80 100

0

20

40

60

80

100 0 h 300 h 500 h

Cum

ulat

ive

dist

ribut

ion

(%)

Joint resistance (m:)

Page 12: Introduction - 3D Integration & Through Silicon Via(TSV)npil.kaist.ac.kr/research/TSV.pdf · Introduction - 3D Integration & Through Silicon Via(TSV) ¾Why TSV for 3D integration?

Nano Packaging & Interconnect Lab.

Conclusion & Ongoing Works

1. TCA/solder hybrid joint was demonstrated for TSV interconnection using new TCA materials.

TCA/solder as a new solution for the 3D-TSV vertical interconnection

2. TCA material properties was designed for joint interconnection.Curing temperature → joint stability Viscosity → joint interconnection @ 600 Pa·s

3. 40 μm fine pitch capability was demonstrated in 10s bonding time.

¾ Conclusion

¾ Ongoing works

1. Void elimination

2. Optimization of the TCA materials Curing agent, epoxy, & thermo-plastic polymers

3. 3D TSV chip stacking using TCAs

Process & TCA properties optimization