TSV Interposer: The Most Cost-Effective Integrator for 3D ... · PDF fileObjectives To investigate the significant roles of Cu-filled TSV passive interposers for 3D IC integration

TSV Interposer: The Most Cost-Effective Integrator for 3D IC Integration

John H. LauElectronics & Optoelectronics Research Laboratories

Industrial Technology Research Institute (ITRI)Chutung, Hsinchu, Taiwan 310, R.O.C.

886-3591-3390, [email protected]

ASME InterPACK2011-52189 (Lau)

TEL:886-3591-3390�

mailto:[email protected]�

ObjectivesTo investigate the significant roles of Cu-filled TSV passive interposers for 3D IC integration.

Emphasis is placed on the roles they play as: (1) Substrates(2) Reliability buffers (3) Carriers (4) Thermal management tools

It is shown that the Cu-filled TSV passive interposers are the most cost-effective integrator for 3D IC integration system-in-package (SiP).


Contents(1) INTRODUCTION(2) 3D IC INTEGRATION(3) 3D IC MEMORY-CHIPS STACKING(4) 3D IC INTEGRATION: ACTIVE INTERPOSERS(5) 3D IC INTEGRATION: PASSIVE INTERPOSERS

A. Passive Interposers as Substrates/Carriers (2.5D IC Integration)B. Cu-Filled TSV Passive Interposers as Reliability Buffers for Moore’s

Law chipsC. Passive Interposers as the Integrators for Moore’s Law Chips (3D IC

Integration)D. Passive Interposers used as Effective Thermal Management tools and

Low-Cost Integrators for Moore’s Law chips (3D IC Integration)(6) SUMMARY AND RECOMMENDATIONS(7) ACKNOWLEDEGEMENTS


Technology

Mat

urity

Basic/Applied R&D

Applied R&D

Mass Production

Commercia-lization

Die Stacking with wire

bondsPackage

on PackageStacking

(PoP)

C2C, C2W, W2W

StackingW2W

Stacking

Full swing production for memories.

Testing and yield challenges give way for package stacking

Active applied R&D is undertaken by Research Institutes. System level challenges are key. In the

phase of industrialization.

Still in upstream research, technological challenges such as yield & device architecture

are key issues.

3D IC Packaging 3D IC Integration 3D Si Integration

3D Integration Technologies

Lau, Lee, Prem, Yu, 3D MEMS Packaging, McGraw-Hill, 2009Lau4

3D IC Integration with microbumps and thin chips

(has been favored since 2000s)

The origin of 3D Integration (1980)3D integration was trigged by the silicon-on-insulator (SOI) technology 30 years

ago, when people thought Moore’s law could be hitting the wall by the 1990s.

3D Si Integration(was favored in 1980s)

Long way to go!

No sight in Volume Production in the

next 10 years

Stacking up wafers with TSVs for electrical feed through. Bumpless!

Need Ecosystem, EDA, Technology

The right way to go and compete with Moore’s law. Hopefully in production (at

least for memory-chips stacking) by 2020!

Memory-chips

Stacking

Active Interposers (Memory/Logic +

CPU/Logic)

Passive Interposers (2.5D & 3D)

Need Ecosystem, EDA, and Business models

Cost issues and Competing technology

Will be used the most in the next

10 years

Because of the disappointment of 3D Si Integration, and using thin chips and microbumps

3D IC Integration (was rejected in 1980s)

Stacking up the chips with TSVs and solder bumps

The invention of TSV (1958)

Shockley's invention was

not meant for 3D integration

A boost (1985) by Richard Feynman

Go 3D instead of all on a surface of a chip!

TSV

Thin Wafers

W2W (SiO2-SiO2) bonding

TSV/RDL/IPD Passive Interposer

Micro Bump

TSV

8@50μm thick 2Gb Chips (16Gb)

Micro bump

TSV


3D IC Integration with Passive Interposer

2.5D IC Integration with Passive Interposer

560μ

m

Micro Bump

TSV

CPU/Logic

Memory

TSV

Micro bump

BumplessCuCu

Evolution of TSV 3D integration


Xilinx’s 4 FPGAs on a Passive TSV Interposer


Xilinx’s FPGA Wide I/O Interface


` `

Organic (BT) substrate

Ordinary bumps

IPD

PCBPCB

100μm

50μm

TSV/RDL/IPD Interposer

Thermal

Stress sensor

TSV:15μm

TSV:15μm

Electrical

TSV:10μm

80μm

Mechanical100μm TSV:15μm

I/O:400 ball array, pitch:450μm

I/O:400 ball array, pitch:1mm

350μm

Micro bumps

Solder balls

TSV:10μm

RDL

1.2mm

RDL

1mm

TSV is optional

ITRI Phase-I 3D IC Integration SiP8

Not-to-scale


ITRI Phase-I 3D IC Integration Test Vehicle

ITRI’s Phase-I 3D IC integration SiP

4-chip stacked

BT-substrate

Mechanical Chip

Thermal chip TSV interposer

ITRI Phase-I 3D IC Integration Test Vehicle


10

Moore’s Law chips


Semi-Embedded TSV Interposer with Stress Relief Gap

Moore’s law Chip

Moore’s law Chip

Mirco solder joint

Mirco solder joint

Special Underfill

Special UnderfillCu-filled TSV

interposer TSVOrdinary Underfill

BT-Substrate

PCB

PCB

BT-Substrate

Ordinary solder joint(a)

(b)

TCE = 8-10x10-6/oC

TCE = 15x10-6/oC

TCE = 2.5x10-6/oC

Cu-filled TSV can be a Stress Relief (Reliability) Buffer for the Cu-low-k Pads of a Moore’s law Chip

0

50

100

150

200

250

Category 1 Category 2 Category 3

250MPa

Conventional FCBGA

FCBGA with interposer

FCBGA with interposer and underfill

125MPa

42MPa

•Selcanayagam and Lau, et al., IEEE/ECTC08, Also, IEEE Transactions 2009.•Zhang, Lau, et al., IEEE/ECTC 2009, Also, IEEE Transactions 2010•Lau and Zhang, ASME Paper: InterPACK2011-52205

Lau

IME TSV Interposers (Carriers)

3D IC Integration with microbumps and thin chips

(has been favored since 2000s)

The origin of 3D Integration (1980)3D integration was trigged by the silicon-on-insulator (SOI) technology 30 years

ago, when people thought Moore’s law could be hitting the wall by the 1990s.

3D Si Integration(was favored in 1980s)

Long way to go!

No sight in Volume Production in the

next 10 years

Stacking up wafers with TSVs for electrical feed through. Bumpless!

Need Ecosystem, EDA, Technology

The right way to go and compete with Moore’s law. Hopefully in production (at

least for memory-chips stacking) by 2020!

Memory-chips

Stacking

Active Interposers (Memory/Logic +

CPU/Logic)

Passive Interposers (2.5D & 3D)

Need Ecosystem, EDA, and Business models

Cost issues and Competing technology

Will be used the most in the next

10 years

Because of the disappointment of 3D Si Integration, and using thin chips and microbumps

3D IC Integration (was rejected in 1980s)

Stacking up the chips with TSVs and solder bumps

The invention of TSV (1958)

Shockley's invention was

not meant for 3D integration

A boost (1985) by Richard Feynman

Go 3D instead of all on a surface of a chip!

Evolution of TSV 3D integration

TSV

Thin Wafers

W2W (SiO2-SiO2) bonding


Micro Bump

TSV

8@50μm thick 2Gb Chips (16Gb)

Micro bump

TSV


3D IC Integration with Passive Interposer

2.5D IC Integration with Passive Interposer

560μ

m

Micro Bump

TSV

CPU/Logic

Memory

TSV

Micro bump

BumplessCuCu


TSV passive interposer supporting high-power chips (e.g., microprocessor and logic) on its top side and low-power chips (e.g., memory) on its bottom side


Microprocessor/ ASIC

TSV Interposer with RDL & IPD Simple

organic substrate

Stiffener ring

Adhesive

TIM

Heat Spreader + Sink (if needed)Microbumps

Ordinary solder bumps Solder balls

PCBMemory

Special underfills are needed between the Cu -filled interposer and all the chips. Ordinary underfills are needed between the interposer and the organic substrate.

TSV interposer supporting high-power chips on its top side and low-power chips on its

bottom side with a cavity.


Microprocessor/ ASIC

Stiffener ring

Adhesive

TIM

Heat Spreader + Sink (if needed)Microbumps

TSV /RDL/IPD interposer

with a cavity Simple organic

substrate

Ordinary solder bumps Solder balls

PCBSpecial underfills are needed between the Cu-filled interposer and all the chips. Ordinary underfills are needed between the interposer and the organic substrate.

Passive TSV interposer with RDL and IPD supporting high-power chips on its top-side and low-power chips at its

bottom-side. The organic substrate is with a cavity


35mm

35mm

10mm

10mm

TSV Interposer

High power chip

The 4 high power chips are the same and uniformly distributed over the TSV interposer.

150µm………

………

……

…

……

…

There are 66 bumps on each side. Totally 260 bumps.

High Power Chip

Top View

60µm Solder Bump

35mm

35mm

5mmTSV Interposer

Low power chip

The 16 low power chips are the same and uniformly distributed over the TSV interposer.

5mm

400µm

There are 11 bumps on each side. Totally 40 bumps.

Low power chip

Bottom View

60µm Solder bump

200µmTSV Interposer

High Power Chip

Low Power Chip 200µm

200µm

60mm Solder bump

TSV Interposer

20µm200µm

Cu TSV

850µm

There are 1600 TSVs in the interposer. So there are 400 TSVs in the quarter model.

Side View

Dimensions of the passive TSV interposer with 4 high-power flip chips on its top and 16 low-power flip chips at

its bottom (the gist of the 3D IC integration SiP.)

ASME Paper no. IMECE2010-40975Lau

Micro Bumps

PCB

Solder BallsOrdinary Solder Bumps

Organic Substrate

TSV Interposer with RDL & IPD

Heat Sink

High-power Chip High-power Chip

Heat SpreaderThermal Interface Material

Stiffener Adhesive

Special underful between the TSV interposer and the high- and low-power flip chips. Ordinary underful between the TSV interposer and the organic substrate.

Thermal Management System of 3D IC Integration Supported by a TSV Interposer

Heat SlugPCB

Low-power Chip


Low-Cost TSH (Through-Si Holes) Interposer for 3D IC Integration

1. Underfills are optional between the Moore’s law chips and the interpose when they are subjected to thermal loading! However, for shock and vibration loads, and depending on chip size, underfills may be needed!

2. Underfills between the TSH and the organic substrate/PCB are necessary!

Organic Substrate/PCB

Solderbump

RDLRDL RDL

RDLRDL

Cu/Au Stud, wire, or pillow

Solder joints

RDL

Moore’s Law chipThrough-Si Holes (TSH) Interposer

Non-metallization holes on the TSH interposer

Solderbump


Buried via (filled or unfilled) for electrical interconnects

VCSEL = Vertical Cavity Surface Emitted Laser (transparent); PD = Photo Diode Detector (transparent); TIA = Trans-Impedance Amplifier

Optical layer support (film)

Polymer Waveguide

Laminated Substrate/Board

Cu Heat SpreaderTIM

Heat Slug Heat Slug

Special Underfills (e.g., Transparent)

Special Underfills (e.g., Transparent)

Mirror Mirror

VCSEL or PDDriver chip

or TIA

Serializer or deserializer

Heat SlugTIM

TSV

Solder Ball

20ASME InterPACK2011-52189 (Lau)

Embedded 3D IC Integration with Optical Devices

TSV/RDL/IPD Interposer with

embedded fluidic channels to

support multiple Moore’s law

chips without any TSVs

Substrate

PCB

3D IC integration SiP consists of a series of TSV/RDL/IPD interposers with embedded fluidic channels to support multiple Moore’s law chips

without any TSVs


MicrobumpsMicro-channelsTSVs

Solder bumps

IPD RDLMoore’s law chips

TSV/RDL/IPD interposer with embedded fluidic channels to support Moore’s law chips with no TSVs

TSV/RDL/IPD interposer with embedded fluidic channels supporting all kinds of chips

on its top and bottom sides


Fluidic inlet

Fluidic outlet TSV Fluidic

channel

TSV

Fluidic inlet

Fluidic outlet Top-side Bottom-side

Fluidic Channel

Interposer (carrier) with TSVs for electrical feed through and fluidic microchannels for thermal

management


Fabricated TSV and embedded fluidic microchannel carrier (interposer). The TSV, sealing ring for TSVs, sealing ring for micochannels. Au20Sn solder bumps and Ti/Cu/Ni/Au UBMs


Interposer and LEDs temperature distribution LEDs temperature distribution

ASICs temperature distribution Flow path in channel

For channel height = 700μm, 100 LED@2W, 4 ASIC@10W, flow rate = 0.54L/min. Top Left (interposer and LEDs temperature distribution); Top Right (LEDs temperature distribution); Bottom Left (ASICs temperature

distribution); Bottom Right (flow path in channel)


2010

CIS with TSV (2.5D)

CIS with TSV and DSP

2020201420122008 2016 2018

Volu

me

Prod

uctio

n

MEMS on ASIC with TSV

Memory/Logic + CPU/Logic with TSV

2.5D IC integration (TSV interposer with chips on top-side)

3D IC integration (TSV interposer with chips on both sides)

Multi-LEDs on chip with TSV

Mem

ory

stac

king

Mem

ory/

Logi

c +

CPU

/Log

ic

3D Integration Roadmap 3D IC integration (TSV

interposer with embedded fluidic microchannels)

Wide I/Os DRAM


SUMMARY AND RECOMMENDATIONSThe roles played by the Cu-filled TSV passive interposers for 3D IC integration have been investigated in this study. It has been demonstrated that the Cu-filled TSV passive interposers are cost-effective 2.5D IC integration substrates and carriers, as well as 3D IC integrator, thermal management tools, and reliability buffers. Some important results and recommendations are summarized in the following.1. In the next 10 years, the TSVs will be fabricated the most (by the number of

vias) for Cu-filled passive interposers.2. Passive interposer is the most cost-effective 3D IC integrator. It is not only

for substrates, carriers, but also thermal managements. Let the passive interposer be the workhorse of 3D IC integration SiPs!

3. Besides it is the most cost-effective 3D IC integrator, the Cu-filled passive interposer acts like a stress relief (reliability) buffer, which reduces the stress acting on the Cu-low-k pads on Moore’s law chips. This advantage becomes more pronounced when the feature size is getting smaller and so does the allowable stress of the chip pads.

4. A few true cost-effective 3D IC integration SiPs with Cu-filled TSV passive interposers have been proposed.

5. 3D Si integration is the right way to go and compete with Moore’s law. Hopefully, by 2020 at least the memory chips stacking could be manufactured at lower costs and higher throughputs by using the 3D Si integration technology. The industry should stride to make this happens!

Acknowledgements

The author would like to express thanks to the financial support by Ministry of Economic Affairs (MOEA), Taiwan, R.O.C., and the strong support by the VP and Director of Electronics & Optoelectronics Research Lab, Dr. Ian Chan of ITRI.

29

Thank you very much for your attention!

Lau

Documents

TSV Interposer: The Most Cost-Effective Integrator for 3D ... · PDF fileObjectives To investigate the significant roles of Cu-filled TSV passive interposers for 3D IC integration