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Lund University / EITF35/ Joachim Rodrigues 2012
Introduc)on*to*Structured*VLSI*Design*3*VHDL*V*
Joachim(Rodrigues(
Lund University / EITF35/ Joachim Rodrigues 2012
Some Updates
• Tuesday 08:15-10:00 Lab session for Group a with TA support
• Deadline Assignment 2: September 28th
Lund University / EITF35/ Joachim Rodrigues 2012
Overview*
• Recap(• Reset3(asynchronous(vs(synchronous(• Declara9on(of(Arithme9c(Signals((
• Operator(Sharing(• Counters(
Lund University / EITF35/ Joachim Rodrigues 2012
Ram*vs*Register*
RAM(characteris9cs(– RAM(cell(designed(at(transistor(level(
– Cell(use(minimal(area(
– Is(combina9onal(and(behaves(like(a(latch(
– For(mass(storage((
– Requires(a(special(interface(logic((Register(characteris9cs(
– DFF((may)(require(much(larger(area(
– Synchronous(– For(small,(fast(storage(
– e.g.,(register(file,(fast(FIFO(
Lund University / EITF35/ Joachim Rodrigues 2012
Register*File*
Registers(are(arranged(as(an(13d(array(
• Each(register(is(accessible(with(an(address(• Usually(1(write(port((with(write(enable(signal)(• May(have(mul9ple(read(ports(
Lund University / EITF35/ Joachim Rodrigues 2012
Strictly*Structured*VHDL**
• How(is(it(done?(
– Local(signals((r,(rin)(are(stored(in(records(and(contain(all(registered(values.(
– All(outputs(are(stored(in(a(en9ty(specific(record(type(declared(in(a(global(interface(package(–(enables(re3use.(
– Use(a(local(variable((v)(of(the(same(type(as(the(
registered(values.(
– reset(handling(moves(to(combinatonial(part.(
Lund University / EITF35/ Joachim Rodrigues 2012
Strictly(Structured(VHDL3Advantages(
Adding(a(signal(in(tradi9onal(style(• Add(port(in(en9ty(declara9on(• Add(signal(to(sensi9vity(list(• Add(port(in(component(declara9on(
• Add(port(in(component(instan9a9on(
Adding(a(signal(in(Strictly(Structured(VHDL((
methodology(• Add(element(in(record(declara9on((
DUT
DUT
Lund University / EITF35/ Joachim Rodrigues 2012
Structured(VHDL3Stored(signals(
Adding(a(stored(signal(in(tradi9onal(style(
• Add(two(signals((current,(next)(
• Add(signal(to(sensi9vity(list(
• Add(reset(value(
• Update(on(clock(edge(
Adding a signal in Structured VHDL methodology • Add element in declaration record
Comb*
Next*Current*
Comb*
rin*r*
Lund University / EITF35/ Joachim Rodrigues 2012
?
Lund University / EITF35/ Joachim Rodrigues 2012
Reset3(Synchronous(
Advantages • Reset presented to all FFs fully
synchronous to the clock and will always meet the reset recovery time.
• Provides some filtering for the reset signal such that it is not effected by glitches, unless they occur right at the clock edge.
• Recommended for designs where the reset is generated by a set of internal conditions. The clock will filter the logic equation glitches between clock edges.
Disadvantages • Reset signal needs to be long
enough to be captured at active clock edge
• Logic synthesis cannot easily distinguish the reset signal from any other data signal. Thus, reset signal may take the fastest path to the FFs by making timing hard to meet.
Lund University / EITF35/ Joachim Rodrigues 2012
Reset3(Asynchronous(
Advantages • High speeds can be
achieved, as the data path is independent of reset signal.
• The circuit can be reset with or without a clock present.
• As in synchronous reset, no work around is required for logic synthesis.
Disadvantages • If the asynchronous reset is
released (reset release or reset removal) at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable.
• Spurious resets can happen due to reset signal glitches.
Lund University / EITF35/ Joachim Rodrigues 2012
Synchronous(circuit((Chu(8.2)(
• One(of(the(most(difficult(design(aspects(of(a(sequen9al(
circuit:(
– How(to(sa9sfy(the(9ming(constraints((
(
• The(Big(idea:(Synchronous(methodology(((
– Group(all(D3FFs(together(with(a(single(clock:(– Conceptually(you(only(need(to(deal(with((
• 9ming(constraint(of(one(memory(element(
• analyze(cri9cal(path(in(combina9onal(logicß(one3by3one(
– Glitches(have(no(effects(as(long(as(the(signals(are(stable(before(the(sampling(clock3edge(
Lund University / EITF35/ Joachim Rodrigues 2012
RT3Level(Example(
32
48
Y=A*B+C
A
B C
Y
A
B
C D
E
CLK
C CL
Lund University / EITF35/ Joachim Rodrigues 2012
RT3level(ex.((FSM/single3register(view)(
Y=A*B+C
A
B C
Y A
B
C C
CL D
E
This is what we code in the lab: • one sequential process • and a big combinational
cloud
Lund University / EITF35/ Joachim Rodrigues 2012
Any(RT3Level(circuit(and(any(FSM((
can(be(viewed(and(described(this(way:(
CL
Inputs Outputs
Next state State REG
RT3Level*
Lund University / EITF35/ Joachim Rodrigues 2012
Wri)ng*RT3level*VHDL*
• The(technology(offers.(– Storage(elements:(DFF((or(latch),(w/wo(reset(etc.)(
– Combina9onal(circuit(building(blocks((gates,(LUT�s)(
• Write(VHDL(such(that((
– synthesis(tool(can(recognize/infer(flip3flops(((i.e.,(use(the(primi9ves(in(the(technology,(rather(than(synthesizing(these(from(
scratch(using(gates(etc.)(
• Synthesis(is(then(about:(– Recognizing(flip3flops(– Synthesizing(and(op9mizing(combinatonial(logic.(
Lund University / EITF35/ Joachim Rodrigues 2012
Separa)on*of*Comb/Seq**
• The(clear(separa9on(between(sequen9al(and(combina9onal(VHDL(assures(that(only(DFFs(will(be(
connected(to(the(clock(signal(
• Criteria(for(good(code(quality33maintainability(
• A(mixture(of(combina9onal(and(sequen9al(processes(is(
synthesizable(but(degrades(code(quality.(
• Ignored(in(a(lot(of(VHDL(books(• We(will(stress(this(in(the(assignments ((
Lund University / EITF35/ Joachim Rodrigues 2012
Basic Arithmetic SIGNED/UNSIGNED OPERATIONS
Lund University / EITF35/ Joachim Rodrigues 2012
Declaring*Arithme)c*Signals*&*Variables*• NUMERIC_STD(offers(2(data(types( ((
– SIGNED,(UNSIGNED(– These(are(declared(in(a(similar(method(to(�std_logic_vector�(– Can(be(used(to(�declare�(signals,(variables,(even(ports(in(an(en9ty(
• (UNSIGNED(– (Assumes(that(only(posi9ve(values(are(going(to(be(used(
– (Example(declara9on(
signal count: unsigned (3 downto 0)
(Creates(a(signal(used(to(store(values(0(3>(15(
Lund University / EITF35/ Joachim Rodrigues 2012
Declaring*Arithme)c*Signals*&*Variables*• SIGNED(
– 2�s(complement(form,(with(MSB(used(as(a(sign(bit(
(–(Example(declara9on(
*signal count: signed (3 downto 0) Creates(a(signal(used(for(storing(the(values(38(3>(+7(
Lund University / EITF35/ Joachim Rodrigues 2012
NUMERIC_STD Package*Func)ons*
•(For(a(detailed(list(of(func9ons((and(their(opera9ons)(see(
the(program(lis9ng(from(�NUMERIC_STD.VHD�((this(is(the(official(IEEE(package(
(
(
How*to*read*the*package*header*?**function �+� (L: UNSIGNED; R: NATURAL) return UNSIGNED
(
UNSIGNED(+(NATURAL(=(UNSIGNED(
(
Lund University / EITF35/ Joachim Rodrigues 2012
NUMERIC_STD Package*Func)ons*(Signed(Arithme9c(Func9ons:(
(
(
(
(
(
(
(
(
(i.e.(func9ons(to(add/(subtract(signed(numbers(
Lund University / EITF35/ Joachim Rodrigues 2012
NUMERIC_STD Package*Func)ons*(Unsigned(Arithme9c(Func9ons:(
(
(
(
(
(
(
(
(
(
(i.e.(func9ons(to(add/(subtract(unsigned(numbers(
(
Lund University / EITF35/ Joachim Rodrigues 2012
NUMERIC_STD Package*Func)ons*(Comparison(func9ons:(
(
(
(
(
(
(
(
(
(
Lund University / EITF35/ Joachim Rodrigues 2012
NUMERIC_STD Package*Func)ons*• Resize(func9ons((–(Used(for(resizing(a(signed/(unsigned(value((–(Useful(if(we(want(to(extract(carry*bit*etc.(
• Example(
newvalue = resize(oldvalue, 5)
Lund University / EITF35/ Joachim Rodrigues 2012
Operator*sharing*
Circuit(complexity(of(VHDL(operators(varies(
(
•(Arithme9c(operators(
(–(Large(implementa9on(
(–(Limited(op9miza9on(by(synthesis(sohware(
(
•(Manual(op9miza9on(is(forced(by(operator(sharing(in(RTL(
(–(Operator(sharing(
(–(Func9onality(sharing(
Lund University / EITF35/ Joachim Rodrigues 2012
Operator*sharing*cont’d*
Mul9plexing(network(are(mutually(exclusively:(
(–(Only(one(result(is(routed(to(output(
(–(Selected(sig(assignment((case(statement)((
(
(with select_expression select sig_name <= value_expr_1 when choice_1, value_expr_2 when choice_2, value_expr_3 when choice_3, . . . value_expr_n when choice_n;
Lund University / EITF35/ Joachim Rodrigues 2012
Example*I*
Original(code:(r <= a+b when boolean_exp else a+c; (
5(min:(write(VHDL(code(that(reduces(the(number(of(
adders(to(“1!(
Revised*code:*src0 <= b when boolean_exp else c; r <= a + src0;*
Lund University / EITF35/ Joachim Rodrigues 2012
Example*II*Original*code:*process(a,b,c,d,...) begin if boolean_exp_1 then r <= a+b; elsif boolean_exp_2 then r <= a+c; else r <= d+1;
end if end process; *Revised*code:*process(a,b,c,d,...) begin if boolean_exp_1 then src0 <= a; src1 <= b; elsif boolean_exp_2 then src0 <= a; src1 <= c; else src0 <= d; src1 <= "00000001"; end if;
end process; r <= src0 + src1;
a(
b(
c(
d(
1(
Lund University / EITF35/ Joachim Rodrigues 2012
Example*Operator*Sharing*
case when s1 d1 <= a*b; ... when s2 d1 <= b*c; ... when s3 d1 <= a*c; ... end case;
d1←a*b
s1
d1←b*c
s2
d1←a*c
s3
***Synthesis*tool*will*
infere*3*mul)pliers***Expensive*in*hardware!*
Lund University / EITF35/ Joachim Rodrigues 2012
Example*Operator*Sharing*
case when s1 d1 <= a*b; ... when s2 d1 <= b*c; ... when s3 d1 <= a*c; ... end case;
case when s1 in1 <= a; in2 <= b; ...
when s2 in1 <= b; in2 <= c; ...
when s3 in1 <= a; in2 <= c; ...
end case; m_out <= in1*in2;
How*can*the*number*of*mul)pers*be*reduced?*
Lund University / EITF35/ Joachim Rodrigues 2012
Counters*
(
( ( ((
• Binary(• Gray(counter(• Ring(counter(
Lund University / EITF35/ Joachim Rodrigues 2012
Binary*Counter*
Binary(counter:(
– State(follows(binary(coun9ng(sequence(– Use(an(incrementor(for(the(next3state(logic(
Lund University / EITF35/ Joachim Rodrigues 2012
Binary*Counter*
Lund University / EITF35/ Joachim Rodrigues 2012
Gray*Counter*
Gray(counter:(
– State(changes(one(bit(at(a(9me(
– Use(a(Gray(incrementor(
(
VHDL(is(provided(in(the(book(
Lund University / EITF35/ Joachim Rodrigues 2012
Ring*Counter*
Circulate(a(single(1,(e.g.,(43bit(ring(counter:(
(1000,(0100,(0010,(0001(
– n&palerns(for(n3bit(register(– Output(appears(as(an(n3phase(signal(
(Non(self3correc9ng(design(
– Insert(�0001�(at(ini9aliza9on(and(circulate(the(palern(in(normal(
opera9on(
*Fastest*counter*(no*combina)onal*logic)*
Lund University / EITF35/ Joachim Rodrigues 2012
Ring*Counter*cont’d*
Lund University / EITF35/ Joachim Rodrigues 2012
Deadlines*
• Assignment 2 is due no later than Friday 28 th • Source code needs to be provided
• Code must be readable, i.e., use indent etc.
Code
Code
Code
Code
Format: Landscape
Bad*example* Good*example*
• next*week:*Invited*Lecture3ARM*Sweden*
Lund University / EITF35/ Joachim Rodrigues 2012
Synthesis*Summary*
Screen dump of the synthesis summary (ALU+FIR) is needs to be handed in with the code.
Lund University / EITF35/ Joachim Rodrigues 2012
( ( ( ( (?(