Introduction to Structured VLSI Design - LTH · – Record types • Array types ... • With a good testbench it is also easy to verify that the final ... Introduction to Structured

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design [email protected] VHDL II

Introduction to Structured VLSI Design‐ VHDL II

Joachim Rodrigues


Overview

• Recap• Concurrency • Processes• Signals• Delta‐Delay • Variables• Data types• Testbench and Simulation


Setup time:Minimum time input must be stable before clk↑

Register timing

D

Q

Contamination delay (cont_clk_to_Q) : Minimum guaranteed time old outputremains valid after clk↑

time

Register

D Q

clk

en 1

1

2

2

3

en

clk

Hold time:Minimum time input must be stable after clk↑

3

clk↑ = Rising clock edge

Propagation delay (clk_to_Q):Worst case (maximum) delay after clk↑ before new outputdata is valid on Q.


Entity ‐ Adder

The ENTITY is the interface of a component. It contains all IO‐ports (port map) and eventually generics.

library IEEE;use IEEE.std_logic_1164.all;

entity Adder isgeneric (N: integer);port(

A : in std_logic_vector (N-1 downto 0);B : in std_logic_vector (N-1 downto 0);S : out std_logic_vector (N-1 downto 0););

end Adder; B

S

A

+

Adder

N

N

N


B

A

Adder

N

N

N

Architecture ‐ behavioralarchitecture behavioral of ADDER isbegin

add_a_b : process (A,B) begin

s <= A+B;end process add_a_b;

end architecture behavioral; S+

Architecture defines behavior of the circuit

architecture behavioral of ADDER isbegin

s <= A+B;end architecture behavioral;

or

We will see today why both codes result in the same HW


Realization of FSMs

Entity declaration

library IEEE;use IEEE.STD_LOGIC_1164.all;entity state_machine is

port (clk : in STD_LOGIC;reset : in STD_LOGIC;input : in STD_LOGIC_VECTOR(1 downto 0);output : out STD_LOGIC_VECTOR(1 downto 0)

); end state_machine;

St1St0”01” / ”01”

”00” / ”11”

”01” / ”01””00” / ”00”

”00” / ”11”

”00” / ”00”

”01” / ”10”

”01” / ”10”

St3 St2


Realization of FSMs‐ cont’dArchitecture declaration (combinatonial part)architecture implementation of state_machine is

type state_type is (st0, st1,st2, st3); -- defines states;signal state, next_state : state_type;signal next_output STD_LOGIC_VECTOR (1 downto 0);

begincombinatonial : process (input,state,state) begincase (state) is -- Current state and input dependent

when st0 => if (input = ’01’) thennext_state <= st1;output <= ”01”

end if;when ....when others =>

next_state <= next_state; -- Default output <= ”00”;

end case;end process;

St1St0”01” / ”01”

”00” / ”11”

”01” / ”01””00” / ”00”

”00” / ”11”

”00” / ”00”

”01” / ”10””01” / ”10”

St3 St2

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design [email protected]

Questions?


Architecture body‐Concurrency

• Simplified syntax

• An entity declaration can be associated with multiple architecture bodies


Concurrency

• Statements in the architecural body are concurrent– Ordering of these statements NOT important

• Example of statements– Signal assignment

» a <= b and c» d <= not a

• Processes are concurrent– Statements within a process are sequential


Processes• Processes in an architecture body are

concurrent– Ordering of processes NOT important

• Statements within a process are sequential• Process consist of

– Label– Sensitivity list– Optional declarative part (before

keyword begin)– Statement part (between keywords

begin and end)

dff: process (clk)

beginif clk’event and clk=’1’then

if (Reset = '0') thenQ <= '0';

elseQ <= D;

end if;end if;

end process dff;


Signals• Signals are metal wires of arbitrary length.

– Metal has inductive, resistive, and capictive parasitics which introduce delay.

– Real parasitics are known after routing• Signals connect the gates in a design• Value of a signal is determined by evaluating an expression– Result of the evaluation must match the type of the signal

a <= b and c;Q <= '0';Q <= D;


Signals cont’d

• Entities are connected by signals (wires). • Syntax:

signal signal_names : signal_type;

• The value of a signal is given by the voltage level of the wire (technology dependent).


Delta‐delay

architecture behav of encoder issignal abar_s,bbar_s : std_logic;

begin -- behavz(3) <= not (a and b and enable); --(1)z(0) <= not (abar_s and bbar_s and enable); --(2)bbar_s <= not b; --(3)Z(2) <= not (a and bbar_s and enable); --(4)abar_s <= not a; --(5)Z(1) <= not (abar_s and b and enable) --(6)

end behav;

CASE: event on B at time T

Target signals on (1,3,6) updated after T+Δ

Thus, event on bbar_s will trigger (2,4) and target signals are updated after T+2Δ


Delta‐delay cont’d

Signals are updated after 0ns, or after delta delay:

A delta‐delay – represents a infinitesimally small delay.– Models HW where a minimal amount of time is needed for a change to occur.

– Allows for ordering of events that occur at the same time during a simulation.

• Each unit of simulation time consists of an infinite number of delta‐ delays.• An event always occurs at simulation time + multiple of delta‐delays.


Variables

• Behaviour differs from signal: A new value is assigned instantaneously

• Variabales declared and used inside a process are local

• Variables declared outside a process may be shared by several processes (shared variables)

• Retain their value throughout simulation • Used as in traditional PL: a “symbolic

memory location” where a value can be stored and modified

• No direct hardware counterpart Example:

process (...)variable index :integer := 0;beginindex := index +1;


Components

• A component instatiated in a structural descprition must be declared

• Appear in the declaration part of the architecure body. Alternatively, in a package (presented in another lecture)

Declaration: Instantiation

component FF is beginport (D,Q,clk); FF1:FFend component; port map(D=>D, Q=>Q,clk=>clk);begin


Data Types

• Types are categorized in– Scalar Types : values appear in sequential order.– Composite Types : composed of elements of single type(array) or different types (records).

– (Access Types : provide access to objects via pointers.)– File Types : Access to objects that contain a sequence ofvalues.


Data Types‐ subtypes

• A subtype is a type with a constraint• Constraint specifies the subset of values

• Example:subtypemy_integer is Integer range 15 to 64;type digit is(´0´, ´1´, ´2´,´3´,´4´,´5´,´6´,´7´,´8´,´9´);subtypemiddle is digit range ’3’ to ´7´;

Integer range in VHDL: –(232) ‐1 to + (232) ‐1Needs to be limited to avoid 64 bits HW!


Scalar Types

• Enumeration type– A set of user‐defined values consisting of identifiers and character literals

• Exampletype student_state is (active, sleep, party, done);Note: This is synthesizable code! (you’ll use similar in the 1st assignment)


Integer Types

• Defines a type whose set of values fall within a specified integer range.

• Examplestype index is range 0 to 15;type word_length is range 31 downto 0;subtype data_word is word_length range 15 downto 0;

Object declarations may use this typesignal databus:data_word;


Physical Types

• Contains values that represent measurment of some physical quantity, e.g., time, length, current, ...

• Examplestype current is range 0 to 1E9;

unitsnA; ‐‐ base unituA = 1000 nA;mA = 1000uA;A=1000mA;

end units;


Composite Types

• Represents a collection of values– Array types– Record types

• Array types (same type)• Example

type data_word is array (7 downto 0) of std_logic;type ROM is array (0 to 127) of data_word;variable rom_addr:rom;

Can become messy! rom_addr is a one-dimensional array object of 128 elements, each element being another array of 8 std_logic elements

7da

ta_w

ord

0

0 rom_addr 127

<-std_logic


Testbench and Simulation• Testing: Testbench and Circuit

– The testbench models the environment our circuit is situated in.

– Provides stimuli (input to circuit) during simulation.– May verify the output of our circuit against test vectors.

• The testbench (VHDL) consists of:– A top level entity connecting the circuit to the testbench– One or more behavioral architectures (matching the refined

level of our circuit).• Testing is done at every abstraction level.

Testbench

Circuit


Testbench and SimulationTesting larger circuits

• Divide and conquer

testbench

circuit

3 subcomponents ‐> 3 subtests:

testbench A testbench Ctestbench B

Test (simulation) fails !

What then ?

How can I find the bug ?

This will localize the problem or problems! Repeat the procedure if a faulty component consists of subcomponents, etc.


• Test strategy ‐> documentation of design correctness.• Good design = easy to test ‐> a good design is a well‐

structured well‐partitioned hierarchical design.– Tip: Do not overdo it with too many entities!

• Design and test of pipelined circuits

• With a good testbench it is also easy to verify that the final synthesized design works as specified.

Combination of circuits

testbench

One stage

testbench

Testbench and SimulationTesting larger circuits


Testbench Example

Component declaration of the circuit being tested

Clock generator

Reset signal generator

Component instantiation of the circuit being tested

The tester, which generates stimuli (inputs) and verifies the response (outputs)

– The tester could also be a separate component.

entity testbench isend testbench;architecture test of testbench is

component circuit isport(clk,reset,inputs,outputs);end circuit;signal inputs,outputs,clk,reset : type;

beginclk_gen: processbegin

if clk=’1’ then clk<=’0’;else clk<=’1’; end if;

wait for clk_period/2;end process;reset <= ‘1’, ‘0’ after 57 ns;device: circuitport map (clk,reset,inputs,outputs);

tester: process(clk,reset)begin….

end process;end testbench;


Testbench and SimulationCircuit Verification• Input driver and output verification:

– Test vectors

circuit

Input stimuli

Correct circuit output

Testvector:

Testvector file

actual circuit output

clk Equal ?


Simulation and VerificationFunctional simulation

• Your initial specification:– While designing a digital system you will rely on functional simulation to verify that your VHDL specification works.

• Cycle‐accurate RTL:– After refining your VHDL specification to the synthesizable RTL abstraction level, you need to re‐verify, using the same testbench.

• After synthesis:– This testbench is again used to simulate the post‐synthesis VHDL netlist (output of the synthesis tool), to verify that it actually works like your VHDL specification.


Simulation and Timing‐Verification

• After synthesis and place & route:– Just after synthesis, the simulation is still only functional, we need to

simulate the electrical timings of your circuit:• Clock‐to‐output delay, contamination delay, propagation delay, wire delay, setup time, hold time, clock skew, …

• The implementation tools (Synthesis + Place & Route) can generate a detailed timing model of your circuit which includes all the above parameters!

• The tools can also calculate maximum operating frequency– Timing simulations with added test vectors are required to find bugs in

the VHDL code, which were not caught by functional simulation or by the synthesis tool.

• Such bugs usually reflect bad design practices such as: improper use of latches, unintended glitches, metastable flip‐flops, reset/clock skew.


What’s next?

• Continue sequence detector• Lab buddy?

Next Deadline: Preparation of sequencedetector Tuesday 6th

Group A: 13‐15, Group B:15‐17


Documents

Introduction to Structured VLSI Design - LTH · – Record types • Array types ... • With a good testbench it is also easy to verify that the final ... Introduction to Structured