EE365

Intro to Quartus II Software

Learning through Tutorials

Zachary Rauen & Joseph CrandallProject Report 1

Prof. A. Khondker9/12/2014

1. Introduction

In order to work in the Computer Engineering field it is important to understand both the Xilinx and Altera software suites and be able to use them properly. These two brands take up most of the market share. Having learned the Xilinx suite in a previous course, it was imperative that we learned Quartus II from Altera. In order to accomplish this, we have been tasked with going through and completing tutorials for the software. Each of the tutorials objectives and steps are outlined below along with results. This report also includes certain fixes for issues that arise when doing the tutorial.

2. Summaries

2.1. Tutorial 1: Introduction to Quartus II [3]

The main goal of this tutorial is to help orient new users to their software. It accomplishes this task by walking the user through performing common tasks when designing for FPGA boards. Such tasks include making a new project or creating a new VHD file to design in VHDL. This tutorial even shows where the user can find help, should the need arise while using their software. This tutorial also shows users how to do pin assignments for the boards. The process is different than when using Xilinx’s PlanAhead software. Altera now has a configuration file where you can perform similar configuration techniques to the files used in PlanAhead. Also shown is templates that can be used freely by the users. This tutorial also goes over programming the board with your compiled VHDL which is also similar to PlanAhead. However, before the programming of the board occurs, it shows the user how to simulate the design in their software. The tutorial shows to launch a separate program called QSim. In the newer versions of Quartus II (11.1 or above and we are using 13.0) the simulator and waveforms are packaged into Quartus II. Upon launching the simulator, the inputs are varied in a GUI method, by choosing which sections should be ones, and which should be logic zeros. This is different than PlanAhead where the simulation settings are usually typed out. That is what is taught in this tutorial.

2.2. Tutorial 2: Using Library Modules [5]

This tutorial demonstrates what and how to use library modules, as the name of the tutorial would suggest. It explains that library modules are like templates that allow the compiler to understand and recognize certain small circuits. The example that they use in this tutorial is using an add/subtract device. The tutorial walks the user through making a more complex circuit based on a simple one that was made in the library. This is imported with a built in wizard. This is then built upon to make the desired design. The tutorial states that this works the same or better than standard code by having the two designs compared in the compiler. This is shown in the step summary for this tutorial.

2.3. Tutorial 3: Using TimeQuest Time Analyzer [6]

The main objective of this tutorial is to demonstrate the usage of the TimeQuest Time Analyzer. This seems to be something unique to Altera, as this was not taught to us for Xilinx. What the analyzer does is analyze the delays throughout the circuit. For instance it will document the propagation delay between input and output. The TimeQuest is built into the Quartus II software and is very simple to run. When analyzing the circuit, it analyzes the clocks, and then produces graphs which illustrate the delays throughout the circuit. The TimeQuest time analyzer can also help adjust the clock and keep the circuit within specified constraints that are later loaded into the design. That is all the tutorial covers, which while it is rather simple, can prove to be very useful later on while using this software.

2.4. Tutorial 4: Introduction to Quartus II Simulation [2]

This tutorial serves as an introduction to the built in simulation tools that are available through the Quartus II software. Specifically, we are testing Altera's University Program Simulation Tools Qsim and the Simulation Waveform Editor. The first tool, Qsim allows users to create inputs for any designed inputs and monitor the corresponding outputs. The tutorial we used covers VHDL and gives a specific VHDL example, however Verilog can also be used if preferred. The tutorial goes over how to install the software, then shows the implementation of a simple logic circuit. Using the simulator, you can confirm that the circuit is working to the intended design using various inputs. The second tool, the Simulation Waveform Editor there are many functions for editing the waveform including forcing a certain signal or a resistance. The editor can also be used to set binary numbers to counters, or display values of Finite State Machines.

2.5. Tutorial 5: Signal Tap II Logic Analyzer [4]

This tutorial serves as an introduction to the SignalTap II Embedded Logic Analyzer that is used with the Altera FPGAs. This software is used to probe signals on an FPGA and analyze their behaviors. This tutorial shows the user how to set up triggers to specify when data is captured and use the analyzer. Using an example circuit given in the tutorial, the board can be programmed and tested using the analyzer. The analyzer can be set up using multiple trigger conditions and can create a waveform based on the behavior of the FPGA during testing. The tutorial also goes over how to set the sample depth and buffer acquisition setting on the analyzer in order to get more specific results.

2.6. Tutorial 6 Debugging of VHDL Hardware Designs [1]

The purpose of this tutorial is to go over some simple debugging methods that can make coding VHDL designs a little bit easier on Altera's boards. It starts with an example circuit and includes the code. The user is to walkthrough the debugging process using the code provided

inside the Quartus II enironment. The tutorial then explains what three of the tools available for debugging are in the Quartus II software: Netlist Viewers, SignalTap II Logic Analyzer (discussed in tutorial 5), and Simulator. The Netlist Viewers create and RTL view of the designed circuit. Finally, the tutorial goes over methods used to smoothen out the debugging process as well as common errors in VHDL programming that the user should avoid.

3. Tutorial Steps and Results3.1. Tutorial 1: Introduction to Quartus II [3]

This tutorial goes over some key terms that are common for people in the field. Then it shows where a user can use help if they need it. Upon trying their helpdesk, the server was down, meaning there is no workaround. Then the tutorial delves into making a new project by selecting the new project wizard. To go through this wizard it first asks you to make a directory for the project and then name it with a top level entity. Then it gives the option to add preexisting files, which we do not have in this instance, and then walks you through setting the project up for your specific device. Upon checking ours, the menu would not display the whole name at first; we had to click on drag on the names to show them. The next page asks about any toolsets, and we do not change this. A summary of our new project is then displayed.

The tutorial shows us to go to File>New>VHDL File and we call it light. Then we paste in the given code. This code, upon analyzing, activates an LED depending on two switches via an XOR gate. This tutorial also has us look at the built in VHDL templates but not to insert any. At which point it tells us that we can compile the design by using Processing>Start Compilation. This completes with zero errors and 8 warnings. It says that if there are any errors, we can get more information by pressing F1. The tutorial also shows a useful feature where you can detach a window from Quartus II which allows for larger workspace.

The next steps involve setting up the pins. We go to Assignment>Assignment Editor and click the “to” field to get the node finder. It tells us to hit a double arrow button which does not exist. The workaround is that the button has changed to the word “list.” This UI is a little different than the tutorial. The pins get set up for their names then they each have to be allocated to a location. Then for the value, the pins are given in the tutorial for a series of boards. The assignements are then exported.

We then are instructed to simulate the circuit in QSim, which does not actualy exist past version 11.1 of Quartus II. We are using 13.0 so this has long since been gone. There is, however, a simulator that is now built in to Quartus II. In order to use this we must go to File>New>University Debugger this opens a new window. Edit>Insert>Node Finder. We then change the amount of time the simulator runs for via Edit>End Time and view it properly by View>Fit In Window. The inputs are set up by selecting a section and clicking on the one or zero in the menubar. Once this is setup the circuit output can be simulated by clicking Simulation>Run. And Simulation>Run Timing shows the propagation delays. This is shown below.

Figure 1: The waveforms showing the delays.

This just leaves the programming of the board left which is really straightforward. Tools>Programming this brings up another window. Clicking on devices shows our currently connected device. Double clicking on that selects it as our working device. Clicking the “Run” button programs the device via JTAG. The tutorial then says that the device “Run Program” button will need to be pressed but that does not apply to our device. The last part of the tutorial goes over a different way to program the board that is not meant for our board and is meant for boards that do not work with JTAG.

3.2. Tutorial 2: Using Library Modules [5]

This tutorial starts by telling the user to create a new project and to include a specific VHDL file which is included in plaintext by the tutorial. Upon attempting to compile this code, there were several errors that arose. One of the most common errors was the usage of the wrong apostrophe in the pdf tutorial. This is not recognized by the compiler. Another common error was the whitespace left in the pdf seemed to not conform to standard VHDL recognizable whitespace. These lines were re-written and upon doing so, the compiler ran without error.

The next part of the tutorial is where the objective comes into play. In order to use the Library of Parameterized Modules (LPM) the tutorial instructs the user to go to Help>Search and then type Megafunctions/LPM in the search box. Clicking on the corresponding result will list all of the available LPMs from Altera. The tutorial also guides the user over the parameters that can be specified in an LPM but then states it can be overbearing to use them by hand and therefore made a built-in wizard to Quartus II in order to insert these.

Upon creating a new project, in which we can test the LPM, the user is asked to go to Tools>MegaWizard Plug-in Manager which opens a new window for importing and using LPMs. We select to create a megafunction variation then find the LPM_ADD_SUB in the list with the type being VHDL. Upon continuing we are given options to select how many bits we want and if it should perform both possible functions, addition or subtraction, or just one. When continuing another page asks if the inputs should be constant, in this case they should not because we want to have external inputs and we also specify that we want signed arithmetic. The next page gives options for creating overflow input and output. We select to have an overflow bit and continue. We elect to not pipeline the function as that is not useful for our application. The next two pages are summaries; the finish button is clicked to exit the window. One last window appears which asks if you want IP files to be added to the project, the tutorial urges that you click no because this can cause compilation errors in VHDL.

Another piece of code is given and this time it incorporates the megafunction we just created. This is used as the top level entity for the project. This is then compiled.

These results and compilation summary are compared against the first project we did to see if they are nearly the same in performance, the comparison proves this to be true as shown below.

Figure 2: The summary of the original project.

Figure 3: The summary of the project with the megafunction.

3.3. Tutorial 3: Using TimeQuest Time Analyzer [6]

This tutorial starts by explaining what circuit we will be analyzing for timing. The maximum frequency calculation (according to the tutorial) is 200MHz. This then shows that the proposed solution will not work for 250MHz and that Computer Aided Design (CAD) can help in finding a solution. Their CAD shows a viable solution.

The tutorial gives the code that will be used in Verilog, so before proceeding, it is converted to conform to VHDL standards. Next the TimeQuest Analyzer is opened from Tools>TimeQuest Timing Analyzer bringing up the window. On the left hand side of the window is the main section for running the analyzer. The first thing that must be done is creating the timing netlist. This is done by clicking the corresponding button in the left pane. The corresponding SDC is then read in by clicking the next button down. Then this new netlist is updated by clicking Update Timing Netlist in the left pane. Now reports can be generated.

In the same pane on the left under reports, the setup summary is found by clicking on Report Setup Summary. This brings up the summary with the clock. The next step is to report the timing by right clicking on the clock and clicking on report timing. In the new window, the To and From fields are set to the signal named clock. The next part is the Targets field; this is left blank in this tutorial. The next two fields, Analysis and Output, are left nearly the same. The only

change is that the detail level in Output is set to Path Only and checking the Report Panel Name checkbox. Upon clicking Report Timing the next window is a little daunting.

Figure 4: The relatively overwhelming timing analysis screen.

The next step in the tutorial, after explaining what is going on here, is to create a clock. Constraint>Create Clock makes a new window appear. This is pretty straightforward making the period 4ns and the target to be clock. This is then run to apply the constraint. The new constraints are written by going to the bottom of the left pane and double clicking Write SDC File…

Going back to the base Quartus II software, these new constraints are loaded in by going to Assignments>Settings>TimeQuest Timing Analyzer and adding the file that was just saved. This now meets our original requirements.

3.4. Tutorial 4: Introduction to Quartus II Simulation [2]

This tutorial starts by explaining what the Qsim Tool does and introduces the goals of the tutorial. The Qsim Tool is provided with the Quartus II CAD system version 11.1 and later and needs to be run in the command window or a shortcut icon if it was installed using the University Program Installer. The tutorial shows how to use the University Program installer if it is necessary.

A simple VHDL code for an example logic circuit is given which can be copy and pasted into your project. This should be saved as a .qpf file (quartus project file). Using an external

program like notepad and importing it into the project seemed to alleviate the formatting issues we had in the previous examples. It might be easier to use something like that when copying code rather than using the built in text editor on the Quartus II interface. After creating a new project and adding the copied code into the directory, the tutorial instructs the user to open the Qsim tools which we installed at the start and opening the .qpf file we created.

We use the New Simulation Input File button to open the Waveform Editor tool to begin creating test vectors for our project. Using this tool. It is possible to easily test the output of the circuit at all possible valuations for the input signals. The boolean expression for our circuit is

f (x1 , x2 , x3 )=x1 x2+x1 x3+x2 x3.First the time scale of the window should be set to 800 ns for this example. The tutorial

explains that in general FPGA terms, a "node" is a reference to a signal in a circuit. We use the Node Finder feature in the waveform editor to add the inputs of the FPGA chip to the simulator. We do this by using the pins: All filter in the Node Finder. Once this is done, the inputs will be added to the waveform in the window all set to low.

The next step is to draw the sample waveforms on the simulator signals. The tutorial teaches three ways to alter waveforms. We highlight the x1 signal and press the Forcing High (1) icon to make the signal high in that section. We can use the Invert button to change the value from low to high which we did on the x2 signal. And finally we use the Overwrite Clock button on signal x3 to make the entire signal alternate between 0 and 1 at a 100 ns inteval. We do this by setting the clock period to 200 ns with a 50% duty cycle. Waveforms can be saved as .vwf files (vector waveform file). The Waveform editor is able to use Modelsim or Quartus II Simulator to simulate the waveforms. We Used Quartus II Simulator. The output is as follows:

Figure 5. The first run of our simulationUsing the Run Timing Simulation button, we are able to simulate the circuit and observe

propagation delays in order to make it a more useful result. Our example with the propagation delay is as follows:

Figure 6. The second run of our simulationNext, the tutorial tells the user that they can alter waveforms in order to get a different

result. We were able to emulate their example here:

Figure 7. The third run of our simulationThe second half of the document is an appendix of extra features of the Simulation

Waveform Editor. They will be listed here along with a brief description for convenience.

3.5. Tutorial 5: Signal Tap II Logic Analyzer [4]This tutorial starts by going over an example circuit to test the Signal Tap II software on our board. The example they use connects up to 8 switches on the DE-series board to the 8 LEDs on the board when the clock is on its positive edge. The user of the tutorial is to create a project called switches and include a file switches.vhd from the sample code provided. There are several problems with the sample code however that need to be addressed. For our purposes the DE0-Nano board we are using we must make some changes to the code. There are no red LEDs on the board so we must change all of the LEDRs in the code to LEDGs in order for it to compile. This is noted in the Background section of the tutorial, but it is easy to miss. The final step before the user is ready to use the Signal Tap program is to make sure that the Quartus II TalkBalk feature is enabled. This feature is available through the tools section under options.

Once a new SignalTap window is opened in the Quartus II environment, the first step is to save the file switches.stp and add enable it for the project through the pop-up window. Using the Settings option under Assignments in the Quartus II environment we can turn of the Signal Tap window or open a different one. Under the Setup tab in the SignalTap window we can add the nodes to the simulator using the Node Finder. The tutorial to highlight SW[0] to SW[7] but we only can use switches SW[0] to SW[3] for our purposes. We can set the clock to CLOCK_50 just as instructed in the tutorial however.

Now that the signals have been set up in the SignalTap window, we need to set the Trigger Conditions for each signal. These settings tell the program at what state the signals need to be for it to record the data for analysis. For the first example we set the analyzer to trigger when SW[0] is high. for this example the trigger condition will be true when the logical AND of all conditions set is satisfied. In order to test our code, we must configure the hardware. This is done by plugging the board into the computer and activating it in the Hardware section of the SignalTap II window. Once these steps are taken we compile the design and load the project onto the board.

Once the board is set up we can run the analysis in the SignalTap window. The simulator will be waiting for a trigger until SW[0] is giving a high signal. The simulator will record the state of all of the signals at the time when the trigger is true and display them on a waveform. Just like the tutorial shows here:

Figure 8. An example of the waveform in the SignalTap II windowAfter this the tutorial goes over Advanced Trigger options that you can set in order to

make the triggering condition more specific. These include multiple trigger conditions as well as rising and falling edge signals.

The final thing that this tutorial goes over is the Sample Depth and Buffer Acquisition modes. This allows us to collect data over a period triggers as opposed to just capturing the state of the device at one trigger. We are told to set the signal to take 8 32 bit sample segments. This should produce 8 different states of the device as we move the triggering switch up and down (from 0 to 1 and back again). If the hardware was working perfectly it would look something like this:

Figure 9. Segmented WaveformHowever in our experiences with two different boards, there were gaps in the middle of

the waveforms sometimes when the switch was changing from 1 to 0. We were not able to get it to capture a continuous waveform like the tutorial wanted us to. It would capture the states of all of the outputs but never from start to finish. 3.6. Tutorial 6 Debugging of VHDL Hardware Designs [1]

This tutorial begins by explaining the example circuit. The example design is a tester circuit that a user could use to test reaction time. The circuit has three keys that can be pressed. The first key is used as a reset key. When the user presses the second key, one of the LEDs on the board will flash after 4 seconds. The user is then to press the third key and the reaction time will be displayed in hundredths of a second on the seven segment display. The circuit is designed as follows:

Figure 10. The top-level design of the example circuitThe code used for this design is provided inside the tutorial itself. The tutorial gives full

codes for the top-level module, control_ff circuit, delay_counter circuit, hundredth circuit, BCD_counter circuit, BCD_stage circuit, and finally the BCD-to-7-segment decoder circuit. In our experience trying to use this code it compiled easily. The user should be aware that copying the code directly from the .pdf can lead to some formatting errors in the Quartus II text editor. This circuit's function is described in depth in the tutorial.

The next part of the tutorial goes over the tools available for use in Debugging this example and any other Hardware design written in the Quartus II environment. While there are more tools than just these, the ones that this tutorial decides to focus on are the Netlist Viewers, SignalTap II Logic Analyzer (which was described in depth in tutorial 5), and Simulator.

The Netlist Viewers provide a register transfer level version of the example circuit we were given. This is extremely convenient for the user as it can be done before the entire design has been compiled. It can be generated at any time after the initial synthesis and can be seen using the RTL Viewer window. The RTL viewer window allows us to look at a block diagram of the entire circuit based on the initial synthesis step. This part of the tutorial went exactly as intended. This is the complete RTL view of the example:

Figure 11. The RTL view of the top-level circuit

If you double click inside any of the blocks of the circuit you can get a more in-depth look at a specific block. Here is the version of our control_ff circuit. It came out exactly as the tutorial's did:

Figure 12. The RTL view of the control_ff circuitSince the entire circuit design does not have to be complete in order to use the RTL viewer, this tool is invaluable for allow the user to see the top-level effects of his design changes.

The second tool that this tutorial goes over is the Technology Map Viewer. This tool is used once the user has a completely compiled circuit that needs to be analyzed. In this section of the tutorial, the write decided to explain the State Machine Viewer. The state machine viewer can be used to examine any state machines that are included in the design of the circuit. They did not provide one for this tutorial however. This part of the tutorial is a little bit unclear and could be confusing to a beginner user as it shows the picture of the Technology Map Viewer in the section of the State Machine Viewer. Regardless, this section worked as intended in the tutorial. At this point the tutorial begins to talk about the Signaltap Analyzer that was gone over in depth in tutorial 5. It is gone over much more in-depth there and anybody who was just using this tutorial would probably not be able to figure it out without referencing tutorial 5.

The rest of the tutorial goes over general debugging practices that can be used to improve designs and make it easier and more efficient to debug code. It starts with a fairly specific example from the original circuit of this tutorial which is not very general. While it does show you how to identify the problem, this example seems a little bit too specific to be incredibly helpful.

The tutorial then has a section that goes over common source of errors in VHDL designs such as the inadvertent creation of latches and assigning a value to a wire more than once. These

general errors could be useful to the beginner programmer but seem a little bit out of place in this tutorial. We didn't have many problems setting up the example in this tutorial as we imported the code through an external text editor to avoid the formatting issues.

4. Conclusions

Overall these tutorials proved to be a good resource for someone that has never used Altera before, especially the first tutorial where nearly everything an amateur will need to know is covered; things akin to what we learned in EE264 with the PlanAhead software. The tutorials seemed to do well trying to explain where and when the differences occur between differing boards. The tutorials did have some issues however, such as not being up to date with their current GUI. These were easily solvable as the changes to the GUI were improvements, making it easier to navigate. There were also some problems with copying the required code from the tutorial to the Quartus II software. This is because VHDL requires a standard apostrophe whereas the pdf contained the curly apostrophes. There were similar occurrences with hyphens and whitespace. Majority of this was solved by first pasting this into notepad where most things are changed to standard ASCII. Aside from this, the tutorials proved to be a solid knowledgebase for someone to learn the Quartus II software.

5. References

[1]

Altera. (2013). Debugging of VHDL Hardware Designs. Altera. Retrieved from ftp://ftp.altera.com/up/pub/Altera_Material/13.0/Tutorials/VHDL/Debugging_Hardware.pdf

[2] Altera. (2013). Introduction to Quartus II Simulation. Altera. Retrieved from ftp://ftp.altera.com/up/pub/Altera_Material/13.0/Tutorials/VHDL/Quartus_II_Simulation.pdf

[3] Altera. (2013). Quartus II Introduction. Altera. Retrieved from ftp://ftp.altera.com/up/pub/Altera_Material/13.0/Tutorials/VHDL/Quartus_II_Introduction.pdf

[4] Altera. (2013). Signal Tap II Logic Analyzer. Altera. Retrieved from ftp://ftp.altera.com/up/pub/Altera_Material/13.0/Tutorials/VHDL/SignalTap.pdf

[5] Altera. (2013). Using the Library of Parameterized Modules (LPM). Altera. Retrieved from ftp://ftp.altera.com/up/pub/Altera_Material/13.0/Tutorials/VHDL/Using_Library_Modules.pdf

[6] Altera. (2013). Using TimeQuest Timing Analyzer. Altera. Retrieved from ftp://ftp.altera.com/up/pub/Altera_Material/13.0/Tutorials/Timequest.pdf