Intro & BCC-HSIO Status

Carl HaberDec 10, 2010

Stave Mtg

Intro and News

• Some action items for AUW– DC-DC stavelet– Noise measurements on 1st stavelet– Ground bounce – how should serial power be

segmented on a chain-of-24?– Distribution of module assy hardware

• Working meeting: Feb 1-2 RAL• New IT-SC: pixel-strip overlap

Hardware

• HSIO has been distributed• Interface boards have been sent to UK (10),

CERN (6), BNL• 15 End-of-Stave are now in assembly• BCC V3 is in fabrication• Will produce and test new BCC boards for

these

Chain of 24 BCC Tests

Powering

Serial power board

BCC board

Loopback board

Configuration

• BCO out from BCC is LVDS and is locally terminated in 100

• BCO in is driven from the EOS card, line is terminated in 60 and back terminated in 100 Driver is M-LVDS

• Expected line impedance is ~70 ohms (4-4-4-6 mil)• EOS driven from HSIO and new interface card• Firmware drives a 40 MHz BCO clock• BCO input network is 1M-10K-1M• BCC can be powered parallel (2.5 V, 1.08 A for 24)• BCC can be powered in series 24*2.5 V, 50 mA

• With attenuation on the clock bus, the input offset was too high with this nominal network (150 mV)

• Switch to 1M-10K-1M (12 mV offset)• BCO out duty cycle is now solid at 50%

BCO in vs Position

Duty Cycle is 50% @ all Pos’n

BCO input amplitude vs pos’n

This attenuation is due to series resistance down the clock bus, not clearwhy it flattens out around the mid-point (lithography?)

Prediction fromChain-of-8

Amplitude is measured both with scope peak to peakfunction (blue) andmanually withcursor tool (red)

Issues from AUW• It would be nice to know how much amplitude margin

we have before duty cycle can become an effect again• Compare performance with serial powering• Measure 80 MHz DCLK asymmetry on 24 BCC• Measure resistance down clock bus• Vary end and back termination (?)• Check BCO out for BCO off – chatter• Find IDELAY settings for 24 data outs

– EOS Tester code is being extended from 8 to 24

BCC # Short #1 (ns) Short #2 (ns) Short #3 (ns) Long (ns) Total (ns)0 6.0 5.8 4.8 8.4 25.01 6.4 5.5 4.9 8.3 25.12 6.2 5.5 5.1 8.1 24.93 6.0 5.7 5.0 8.3 25.04 6.1 5.5 4.9 8.4 24.95 6.3 5.6 4.9 8.3 25.16 5.8 5.7 5.0 8.4 24.97 6.2 5.6 4.8 8.4 25.08 5.7 5.9 4.7 8.6 24.99 6.1 5.6 4.9 8.3 24.9

10 6.0 5.7 4.9 8.4 25.011 6.1 5.9 4.7 8.4 25.112 5.9 5.8 4.9 8.4 25.013 5.9 5.8 4.5 8.7 24.914 6.1 5.7 4.7 8.4 24.915 6.6 5.4 4.8 8.1 24.916 5.9 5.7 5.0 8.4 25.017 6.9 5.5 4.5 8.1 25.018 6.1 5.6 5.0 8.3 25.019 6.0 5.6 4.7 8.7 25.020 6.1 5.7 4.7 8.5 25.021 6.4 5.4 4.9 8.3 25.022 6.1 5.6 4.8 8.5 25.023 6.4 5.5 4.7 8.3 24.9

Averages: 6.14 5.64 4.83 8.38 24.98stdev 0.26 0.14 0.15 0.16 0.07

DCLK pattern for 24 BCC

DCLK Pattern for 24 BCC

Pattern is very regular for this sample of 24 BCC V2

Serial Power• Serial regulator chain works DC for 1-24 drops

when tested with a simple resistive load• Next step is to power 1,2,3….24 BCC in

sequence: done, works OK• See correct DC response but BCC response is

inconsistent for small number of loads– Due to unpowered load on bus, not an issue