Interrupts UK

7/29/2019 Interrupts UK

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Interrupts & related instructions

Types of data transfer

Simple I/O used when timings of I/O device is known

(Ex. Collect newspaper leisurely any time after 8 a.m.)

Status check I/O Data transfer done anytime after I/O device says it is ready(Ex. Check newspaper box and collect newspaper if it is in the box)

Interrupt driven I/O data transfer done immediately after I/O device interrupts(Ex. Collect newspaper when the door bell rings indicating delivery of newspaper)

In this section only Interrupt driven I/O is discussed.

Interrupt driven I/O

Interrupt types

Hardware interrupts Software interrupts Exceptions or TrapsEx. NMI and INTR pins Ex. INT n, INT 3, INTO

instructions

Ex. Divide by zero error,

Single step interrupt

Interrupt type numbers

Every interrupt type in 8086 has an 8-bit Interrupt type number (ITN) as shown below.

ITN Interrupt type ITN Interrupt type

0 Divide by 0 error 5 Out of bound(80286)

1 Single step interrupt 6 Invalid opcode

2 NMI 7 No Coprocessor

3 Break point interrupt 8 Double fault (during an

4 Overflow error instruction 2 interrupts)

5 -1F Reserved by Intel.

13H for Disk services

20-FF Available for user.

INT 21H for DOS services.

Action when NMI is activated

NMI is positive edge triggered input

1. Complete the instruction in progress

2. Push Flags on the stack

3. Reset IE flag (to ensure no further interrupts)4. Reset T flag (so that interrupt service subroutine, ISS, is not executed in single step)


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5. PUSH CS

6. PUSH IP7. IP loaded from word location 2 x 4 = 8 (2 is ITN)

8. CS loaded from next word location (0000AH)

Processor makes a branch to the subroutine!

Interrupt Vector table (IVT)

RAM locations 0 to 003FFH are used to store IVT. It contains 256Interrupt Vectors (IV) each of 4 bytes.

00000H 1234H

5678:1234H is IV number 000002H 5678H

00004H 3344H

5566:3344H is IV number 100006H 5566H: : :

003FCH 6677H

7788:6677H is IV number FF003FEH 7788H

Execution of INT n (n=0 to FF)


2. Reset IE flag (to ensure no further interrupts)3. Reset T flag (so that ISS is not executed in single step)

4. PUSH CS

5. PUSH IP6. IP loaded from word location n x 4 = say, W7. CS loaded from next word location W+2

In INT n, which is a 2-byte instruction, n is the ITN. INT n has the opcode CDH

Action when INT 3 is executed


2. Reset IE flag (to ensure no further interrupts)

3. Reset T flag (so that ISS is not executed in single step)4. PUSH CS

5. PUSH IP

6. IP loaded from word location 3 x 4 = 0000CH

7. CS loaded from next word location 0000EH

INT 3 is a 1-byte instruction with opcode of CCH


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What is divide by 0 error?

Ex. DIV BL

Before After

AH 40H 00H This is an example for divide by 0 error. It only

means quotient is too large for the register!AL 60H 2030HBL 02H

Action for divide by 0 error

For divide by 0 error the ITN is 0

1. Push Flags on the stack2. Reset IE flag (to ensure no further interrupts)

3. Reset T flag (so that ISS is not executed in single step)

4. PUSH CS

5. PUSH IP6. IP loaded from word location 0 x 4 = 00000H

7. CS loaded from next word location 00002H

Processor makes a branch to the subroutine at location 5678:1234H if the contents of IVT

is as shown in the table above.

Action for Single step interrupt

For divide by 0 error the ITN is 1

1. Push Flags on the stack2. Reset IE flag (to ensure no further interrupts)3. Reset T flag (so that ISS is not executed in single step)

4. PUSH CS

5. PUSH IP6. IP loaded from word location1 x 4 = 00004H


Processor makes a branch to the subroutine at location 5566:3344H as per the IVT

Action for INTO instruction

INTO is a 1-byte instruction. For interrupt on overflow the ITN is 4.

1.Do steps 2 to 7 only if Overflow flag is set2. Push Flags on the stack

3. Reset IE flag and T flag

4. PUSH CS

5. PUSH IP


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6. IP loaded from word location 4 x 4 = 00010H


INTO is equivalent to: JNO Next

INT 4

Next: .

Action when INTR is activatedINTR is level triggered input.

1. Complete the instruction in progress2. Activate INTA o/p twice. In response 8086 receives ITN n instruction from an external

device like 8259 PIC

3. Push Flags on the stack. Reset IE and T flags

4. PUSH CS5. PUSH IP

6. IP loaded from word location n x 4 = say, W7. CS loaded from next word location W+2Processor makes a branch to the subroutine!

IRET (Return from Interrupt) instruction

An ISS ends with the IRET instruction.

IRET is same as POP IP + POP CS + POPF

SP after branch to ISS

IP

CSSP before branch to ISS FLAGS

Make sure ISS does not end with RET!

Priority of 8086 Interrupts

If several interrupts occur during the execution of an instruction, in which order interruptswill be serviced? There will be priorities as indicated below.

Divide by 0 error, INT n

NMIINTR

Single step interrupt

Highest priority

Lowest priority

In reality NMI has highest priority! If NMI occurs during the servicing of INT n,

processor branches to NMI routine as IE flag has no effect on NMI.

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