2 Interrupts

Introduction

The interrupt I/O is a process of data transfer whereby an external device or a peripheral caninform the processor that it is ready for communication and it requests attention.

The process is initiated by an external device and is asynchronous, meaning that it can be initiated at any time without reference to the system clock. However, the response to an interrupt request is directed or controlled by the microprocessor.

The interrupt requests are classified in two categories: maskable interrupt and nonmaskable interrupt. More specifically four maskable interrupts and one nonmaskable interrupt. Among these four maskable interrupts, one is nonvectored. The other three are vectored to specific locations

THE 8085 INTERRUPTThe 8085 interrupt process is controlled by the Interrupt Enable flip-flop, which is internal to the processor and can be set or reset by using software instructions.

If the flip-flop is enabled and the input to the interrupt signal INTR (pin 10) goes high, the microprocessor is interrupted. This is a maskable interrupt and can be disabled.

Steps for the 8085 Interrupt process

Step 1: The interrupt process should be enabled by writing the instruction EI in the main program.The instruction EI sets the Interrupt Enable flip-flop.The instruction DI resets the flip-flop and disables the interrupt process.

Interrupts

4 Maskable

3 Vectored

RST 7.5

RST 6.5

RST 5.5

1 Non-Vectored INTR

1 Non-maskable Vectored TRAP

EI (Enable Interrupt):1 -byte instruction.Sets the Interrupt Enable flip-flop and enables the interrupt process. System reset or an interrupt disables the interrupt process.

DI (Disable Interrupt):1-byte instruction.Resets the Interrupt Enable flip-flop and disables the interrupt.It should be included in a program segment where an interrupt from an outside source cannot be tolerated.

Step 2: When the microprocessor is executing a program, it checks the INTR line during the execution of each instruction.

Step 3: If the line INTR is high and the interrupt is enabled, the microprocessor:• Completes the current instruction• Disables the Interrupt Enable flip-flop• Sends a signal called INTA - Interrupt Acknowledge (active low).• The processor cannot accept any interrupt requests until the interrupt flip-flop is enabled again.

Step 4: The signal INTA is used to insert a restart (RST) instruction through external hardware.• The RST instruction is a 1-byte CALL instruction that transfers the program control to a specific memory location on Page 00H (The first 256 bytes).

Step 5: When the microprocessor receives an RST instruction:• It saves the memory address of the next instruction on the stack.• The program is transferred to the CALL location.

Step 6: Assuming that the task to be performed is written as a subroutine at the specified location, the processor performs the task. This subroutine is known as a service routine

Step 7: The service routine should include the instruction EI to enable the interrupt again.

Step 8: At the end of the subroutine, the RET instruction retrieves the memory address where the program was interrupted and continues the execution.

RST Instruction

The 8085 instruction set includes eight RST (Restart) instructions:• RST 0 , ………., RST 7 • These are 1-byte Call instructions that transfer the program execution to a specific location on page 00H, as listed in the following Table.

Implementing the RST instruction (STEP 4) To implement Step 4 in the interrupt process, insert one of these instructions in the microprocessor by using external hardware and the signal INTA.

In the following circuit, instruction RST 5 is built using a tri-state buffer

RST 5 instruction implementation

Example: An Implementation of the 8085 Interrupt• Write a main program to count continuously in binary with a one-second delay between each count.• Write a service routine at XX70H to flash FFH five times when the program is interrupted, with some appropriate delay between each flash.

Service RoutineXX70 SERV: PUSH BXX71 PUSH PSWXX72 MVI B,0AHXX74 MVI A,00HXX76 FLASH: OUT PORT1XX78 MVI C,01HXX7A CALL DELAYXX7D CMAXX7E DCR BXX7F JNZ FLASHXX82 POP PSWXX83 POP BXX84 EIXX85 RET

Main ProgramXX00 LXI SP,XX99HXX03 EIXX04 MVI A,00HXX06 NXTCNT: OUT PORT1XX08 MVI C,01HXX0A CALL DELAYXX0D INR AXX0E JMP NXTCNT

Issues in Implementing Interrupts

1. Is there a minimum pulse width required for the INTR signal?

The microprocessor checks INTR, one clock period before the last T-state of an instruction cycle. In the 8085, the Call instructions require 18 T-states; therefore, the INTR pulse should be high at least for 17.5 T-states.In a system with 3 MHz clock frequency the input pulse to INTR should be at least 5.8 µs long.(1/3MHz *17.5)

2. How long can the INTR pulse stay high?The INTR pulse can remain high until the interrupt flip-flop is set by the EI instruction in the service routine.If it remains high after the execution of the El instruction, the processor will be interrupted gain, as if it were a new interrupt.

3. Can the microprocessor be interrupted again before the completion of the first interrupt service routine?The answer to this question is determined by the programmer.After the first interrupt, the interrupt process is automatically disabled. If instruction El is written at the beginning of the routine, the microprocessor can be interrupted gain during the service routine.

Multiple Interrupts and Priorities how to use INTR for multiple peripherals and how to determine priorities among these peripherals when two or more of the peripherals request interrupt service simultaneously .One solution is using an 8-to-3 priority encoder that determines the priorities among interrupting devices.

This device has 8 inputs and 3 outputs. The inputs are assigned increasing priorities according to

the increasing index of the input.

Input 7 has highest priority and input 0 has the lowest. The 3 outputs carry the index of the highest priority

active input.

The following Figure shows how this circuit can be used with a Tri-state buffer to implement an interrupt priority scheme.

Function Table for the priority encoder

Using the priority Encoder

When an interrupting device requests service, one of the input lines goes low, which makes line E0 high and interrupts the microprocessor

When the interrupt is acknowledged and the signal INTA enables the tri-state buffer, the code corresponding to the input is placed on lines D5, D4, and D3.

For example, if the interrupting device on line I5 goes low:

The output of the encoder will be 010. This code is inverted by the buffer 74LS366 and combined with other high data lines.

Thus, the instruction 11101111 (EFH) is placed on the data bus. This is instruction RST 5.

If there are simultaneous requests, it responds to the higher-level input, ignoring the lower-level input.

One of the drawbacks of this scheme is that the interrupting device connected to the input I7 always has the highest priority. And this is one of the drawbacks of this schema.

this device is being replaced by a more versatile one called a Programmable Interrupt controller (8259A)

8085 Vectored Interrupt The 8085 has five interrupt inputs; one is called INTR which was discussed so far. Three are called RST 5.5, RST 6.5, and RST 7.5, and the fifth is called TRAP, a non-maskable

interrupt.

These last four (RSTs and TRAP) are automatically vectored (transferred) to specific locations on memory page 00H without any external hardware.

They do not require the INTA signal or an input port; the necessary hardware is already implemented inside the 8085.

TRAP A nonmaskable interrupt that has the highest priority among the interrupt signals. It need not be enabled, and it cannot be disabled.

RST 7.5, 6.5, and 5.5 These maskable interrupts are enabled under program control by two instructions:

El (Enable Interrupt) described earlier SIM (Set Interrupt Mask)

SIM: Set Interrupt Mask. This is a 1-byte instruction and can be used for three different functions

SIM Instruction and Functions Set mask for RST 7.5, 6.5, and 5.5 interrupts. Bit D3 is a control bit and should = 1 for bits D0,

D1 and D2 to be effective.

Reset RST 7.5 flip-flop .Bit D4 is additional control for RST 7.5. If D4 = 1, RST 7.5 is reset. This is used to override (or ignore) RST 7.5 without servicing it.

The third function is to implement serial I/O (discussed in Chapter 16).

Interrupts Priority and Vector Locations

As shown from this schema, all of the interrupts can be masked entirely by EI, or individually by the SIM instruction and its code.

Triggering Mechanism

RST 7.5 Triggering LevelThis is positive-edge sensitive and can be triggered with a short pulse. The request is stored internally by the D flip-flop until the microprocessor responds to the request or until it is cleared by Reset or by bit D4 in the SIM instruction.

RST 6.5 , RST 5.5 Triggering LevelsThese interrupts are level-sensitive, meaning that the triggering level should be on until the microprocessor completes the execution of the current instruction.

TRAP Triggering LevelIt is level- and edge sensitive, meaning that the input should go high and stay high to be acknowledged. It cannot be acknowledged again until it makes a transition from low to high. Examples

Level Sensitive Edge Sensitive Level and Edge Sensitive

Enable all the interrupts in an 8085 system:

Reset the 7.5 interrupt from the last Example:

PENDING INTERRUPTSBecause there are several interrupt lines, when one interrupt request is being served, other interrupt requests may occur and remain pending.The 8085 has an additional instruction called RIM (Read Interrupt Mask) to sense these pending interrupts.

RIM: Read Interrupt MaskThis is a 1-byte instruction that can be used for the following functions: To read interrupt masks: This instruction loads the accumulator with 8 bits indicating the

current status of the interrupt masks. To identify pending interrupts: Bits D4, D5, and D6 identify the pending interrupts. To receive serial data. Bit D7 is used to receive serial data.

Bit Pattern for the RIM Instruction

Example

EI ;enable interruptsMVI A,08H ;bit pattern to enable all interruptsSIM ;enable RST 7.5, 6.5, 5.5

MVI A,18H ;Set D4=1SIM ;Reset 7.5 interrupt flip-flop

Assuming the microprocessor is completing an RST 7.5 interrupt request, check to see if RST 6.5 is pending. If it is pending, enable RST 6.5 without affecting any other interrupts; otherwise, return to the main program.

Summary

Restart as a software instruction

RIM ;read interrupt maskMOV B,A ;save mask info.ANI 20H ;check if RST 6.5 is pending?JNZ NEXT ;RST 6.5 is pendingEI ;RST is not pending ,return to mainRET

NEXT: MOV A,B ;get mask info.ANI 0DH ;enable RST 6.5 (00001101)ORI 08H ;enable SIM (00001x0x)SIMJMP SERV ;jump to RST 6.5 service routine

After the breakpoint routine, the program should return to executing the main program at the breakpoint.The breakpoint procedure allows the user to test programs in segments.For example, if RST 6 is written in a program, the program execution is transferred to location 0030H; it is equivalent to a 1-byte call instruction. This can be used to write a software breakpoint routine.

Illustrative Program:This code illustrates the use of a procedure to display the accumulator content and the PSW into PORT1 and PORT2 when A is entered through a keyboard, and then returns when 0 is entered.

Here when an interrupt with an RST 6 code is initiated, this procedure is called. Arguably, this could also be called from within a program as a normal instruction

BRKPNT is called in the RST 6 code segment.

BRKPNT: PUSH PSW Save RegistersPUSH BPUSH DPUSH H

KYCHK: CALL KBRD Administers a Key in A Function KBRD abstracted hereCPI 0AH Is it key A?JNZ RETKY NO? check Zero keyLXI H,0007H Yes? Load A Location HL= SP+7 = SP’-3

which is ADAD SP Add the content of SP to HLMOV A,MOUT PORT1 Display ADCX H Decrease HL by one HL= SP’-4MOV A,M Which is the PSWOUT PORT2 Display PSWJMP KYCHK Go back to check again

RETKY: CPI 00H Is it Key Zero?JNZ KYCHK No? check for next entryPOP H Yes? Restore registersPOP DPOP BPOP PSWRET Restore PC content

So if at any at any point the programmer desires to view the content of the accumulator within the program for debugging purposes, the user/programmer could inject RST 6 within the code.

Additional I/O Concepts and Processes

Stack Pointer Position

Content Label

SP: SP’-A L SP’-9 H SP’-8 E SP’-7 D SP’-6 C SP’-5 B SP’-4 PSW SP’-3 A SP’-2

PCLow

SP’-1 High

SP’ X

The 8085 interrupt I/O, described earlier, is limited because of its single interrupt pin and hardware requirements to determine interrupt priorities.To circumvent these limitations, a programmable interrupt controller such as the 8259A is used to implement and extend the capability of the 8085 interrupt.Another I/O process, Direct Memory Access (DMA), is commonly used for high-speed data transfer.

Programmable Interrupt Controller:The 8259A• The 8259A is a programmable interrupt managing device.• The primary features of the 8259A are:

– It manages eight interrupt requests.– It can vector an interrupt request anywhere in the memory map through program control without additional hardware for restart instructions.– It can solve eight levels of interrupt priorities in a variety of modes.– With additional 8259A devices, the priority scheme can be expanded to 64 levels.

• One of the major limitations of the 8085 interrupt scheme is that all requests are vectored to memory locations on page 00H, which is reserved for ROM or EPROM,• Access to these locations is difficult after a system has been designed.• In addition, the process of determining priorities is limited, and extra hardware is required to insert Restart instructions.• The 8259A overcomes these limitations and provides many more flexible options.• It can be employed with 16-bit Intel microprocessors as the 8086/8088 as well.