8 Interrupts

7/26/2019 8 Interrupts

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Interrupts


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Interrupts

Interrupt is a process where an external device can getthe attention of the microprocessor. The process startsfrom the I/O device

The process is asynchronous.

Interrupts can be classified into two types: as!able"can be delayed#

$on%as!able"can not be delayed#

Interrupts can also be classified into: &ectored"the address of the service routine is hard%wired#

$on%vectored"the address of the service routine needs to be suppliedexternally#


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,esponding to Interrupts

,esponding to an interrupt may be immediateordelayeddepending on whether the interrupt is mas!ableor non%mas!able and whether interrupts are being

mas!ed or not.

There are two ways of redirecting the execution to theI+, depending on whether the interrupt is vectored or

non%vectored. The vector is already !nownto the icroprocessor

The device will have to supplythe vector to theicroprocessor


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The 0 Interrupts

The 0 has 0 interrupt inputs. The I$T, input.

The I$T, input is the only non%vectoredinterrupt.

I$T, is mas!ableusing the -I/3I instruction pair.

,+T 0.0) ,+T 4.0) ,+T 5.0 are all automaticallyvectored.

,+T 0.0) ,+T 4.0) and ,+T 5.0 are all mas!able.

T,'6 is the only non%mas!ableinterrupt in the 0 T,'6 is also automatically vectored


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The 0 Interrupts

Interrupt name as!able &ectored

I$T, 7es $o

,+T 0.0 7es 7es

,+T 4.0 7es 7es

,+T 5.0 7es 7es

T,'6 $o 7es


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Interrupt &ectors and the &ector

Table 'n interrupt vectoris a pointer to where the I+, is

stored in memory.

'll interrupts "vectored or otherwise# are mapped ontoa memory area called the Interrupt &ector Table"I&T#. The I&T is usually located in memory page "8 %

998#.

The purpose of the I&T is to hold the vectors that redirect

the microprocessor to the right place when an interruptarrives.

The I&T is divided into several bloc!s. -ach bloc! is usedby one of the interrupts to hold its 1vector2


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. The interrupt process should be enabledusing the -Iinstruction.

;. The 0 chec!s for an interrupt during the execution ofeveryinstruction.


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4. (hen the microprocessor executes the ,+T instructionreceived from the device) it saves the address of the nextinstructionon the stac! and *umps to the appropriate

entry in the I&T.5. The I&T entry must redirect the microprocessor to the

actual service routine.

. The service routine must include the instruction -Ito re%

enable the interrupt process.@. 't the end of the service routine) the ,-Tinstruction

returns the execution to where the program wasinterrupted.

The 0 $on%&ectored Interrupt

6rocess


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The 0 $on%&ectored Interrupt 6rocess

The 0 recogniAes ,-+T',T

instructions: ,+T % ,+T5.

each of these would send theexecution to a predetermined

hard%wired memory location:

RestartInstruction

Equivalentto

,+T B'CC8

,+T B'CC8

,+T; B'CC8

,+T< B'CC8

,+T> B'CC;8

,+T0 B'CC;8

,+T4 B'CC


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,estart +e=uence

The restart se=uence is made up of three machinecycles

In the st machine cycle: The microprocessor sends the I$T' signal. (hile I$T' is active the microprocessor reads the data lines

expecting to receive) from the interrupting device) the opcodefor the specific ,+T instruction.

In the ;nd and


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,estart +e=uence

The location in the I&T associated with the

,+T instruction can not hold the complete

service routine.The routine is written somewhere else in

memory.

Only a D?6 instruction to the I+,Es locationis !ept in the I&T bloc!.


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8ardware Feneration of ,+T

Opcode 8ow does the external device produce the

opcode for the appropriate ,+T instructionG

The opcode is simply a collection of bits.

+o) the device needs to set the bits of the data

bus to the appropriate value in response to an

I$T' signal.


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The following is anexample of generating

RST 5:

RST 5s opcode is EF =

D D

765!"#$

###$####


Opcode


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Opcode 3uring the interrupt ac!nowledge machine cycle)

"the st machine cycle of the ,+T operation#:

The icroprocessor activates the I$T' signal. This signal will enable the Tri%state buffers) which willplace the value -98 on the data bus.

Therefore) sending the icroprocessor the ,+T 0instruction.

The ,+T 0 instruction is exactly e=uivalent toB'CC ;8


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Issues in Implementing I$T,

Interrupts 8ow long canthe I$T, remain highG

The I$T, line must be deactivated before the -I is executed.Otherwise) the microprocessor will be interrupted again.

The worst case situation is when -I is the first instruction inthe I+,.

Once the microprocessor starts to respond to an I$T,interrupt) I$T' becomes active "H#.

Therefore)I$T, should be turned off as soon as theI$T' signal is received.


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Issues in Implementing I$T,

Interrupts Banthe microprocessor be interrupted again before the

completion of the I+,G 's soon as the st interrupt arrives) all mas!able interrupts are

disabled. They will only be enabled after the execution of the -I

instruction.

Therefore) the answer is: 1only if you allow it to2.

If the -I instruction is placed early in the I+,) otherinterrupt may occur before the I+, is done.


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ultiple Interrupts 6riorities

8ow do we allow multiple devices tointerrupt using the I$T, lineG

The microprocessor can only respond to onesignal on I$T, at a time.

Therefore) we must allow the signal from onlyone of the devices to reach the microprocessor.

(e must assign some priority to the differentdevices and allow their signals to reach themicroprocessor according to the priority.


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The 6riority -ncoder

The solution is to use a circuit called the priority encoder"5> in the boo! shoes how this circuit can be used witha Tri%state buffer to implement an interrupt priority scheme.

The figure in the textboo! does not show the method for distributing theI$T' signal bac! to the individual devices.


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ultiple Interrupts 6riorities

$ote that the opcodes for the different ,+Tinstructions follow a set pattern.

Jit 30) 3> and 3< of the opcodes change in a binary se=uence

from ,+T 5 down to ,+T . The other bits are always .

This allows the code generated by the 5>


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ultiple Interrupts and 6riority

De%& 7

De%& 6

De%& 5

De%&

De%& !

De%& "

De%& #

De%& $

7

#

!

'

7

!6

6

'

$

'5

()TR *irc+it

()T, *irc+it

()T,

()TR

,D7

,D6

,D5

,D

,D!

,D"

,D#,D$

-7-6-5--!-"-#-$

(7(6(5(

(!("(#($

Tri .

State

/+ffer0riorit1

Encoder

25 3

RST *irc+it


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The 0 as!able/&ectored

Interrupts The 0 has > as!ed/&ectored interrupt inputs.

,+T 0.0) ,+T 4.0) ,+T 5.0 They are all mas!able.

They are automatically vectoredaccording to the following table:

The vectors for these interrupt fall in between the vectors for the,+T instructions. ThatEs why they have names li!e ,+T 0.0 ",+T 0and a half#.

Interrupt Vector

,+T 0.0 ;B8

,+T 4.0 8

,+T 5.0


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as!ing ,+T 0.0) ,+T 4.0 and

,+T 5.0 These three interrupts are mas!ed at two

levels:

Through the Interrupt -nable flip flop and the-I/3I instructions.

The Interrupt -nable flip flop controls the wholemas!able interrupt process.

Through individual mas! flip flops that controlthe availability of the individual interrupts.

These flip flops control the interrupts individually.


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Interrupt 6rocess. The interrupt process should be enabledusing the -I

instruction.

;. The 0 chec!s for an interrupt during the execution of

everyinstruction.

. The microprocessor then executes a call instruction that

sends the execution to the appropriatelocation in theinterrupt vector table.


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Interrupt 6rocess0. (hen the microprocessor executes the call

instruction) it saves the address of the nextinstructionon the stac!.

4. The microprocessor*umps to the specific serviceroutine.

5. The service routine must include the instruction -Ito re%enable the interrupt process.

. 't the end of the service routine) the ,-Tinstruction returns the execution to where the

program was interrupted.


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anipulating the as!s

The Interrupt -nable flip flop is manipulated using

the -I/3I instructions.

The individual mas!sfor ,+T 0.0) ,+T 4.0 and

,+T 5.0 are manipulated using the +I

instruction.

This instruction ta!es the bit pattern in the 'ccumulator

and applies it to the interrupt mas! enabling and

disabling the specific interrupts.

8ow +I Interprets the


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8ow +I Interprets the

'ccumulator

SD-

SDE

R7&5

SE

7&5

6&5

5&5

$#"!567

RST5&5 as

RST6&5 as

RST7&5 as8 $ 9 ,%aila4le# 9 ased

as Set Ena4le

$ 9 (gnore 4its $9"

# 9 Set the mass according

to 4its $9"

Force RST7&5 Flip Flop to reset)ot sed

Ena4le Serial Data

$ 9 (gnore 4it 7

# 9 Send 4it 7 to S-D pin

Serial Data -+t


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+I and the Interrupt as!

Jit is the mas!for ,+T 0.0) bit is the mas!for ,+T 4.0 andbit ; is the mas!for ,+T 5.0. If the mas! bit is ) the interrupt is available.

If the mas! bit is ) the interrupt is mas!ed.

Jit < "as! +et -nable % +-# is an enable for setting themas!. If it is set to the mas! is ignoredand the old settings remain.

If it is set to ) the new setting are applied.

The +I instruction is used for multiple purposes and not only for settinginterrupt mas!s.

It is also used to control functionality such as Serial Data Transmission. Therefore, bit 3 is necessary to tell the microprocessor hether or not theinterrupt mas!s should be modified


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+I and the Interrupt as!

The ,+T 5.0 interrupt is the only0 interrupt that hasmemory. If a signal on ,+T5.0 arrives while it is mas!ed) a flip flop will

remember the signal. (hen ,+T5.0 is unmas!ed) the microprocessor will be interrupted

even if the device has removed the interrupt signal.

This flip flop will be automatically resetwhen the microprocessorresponds to an ,+T 5.0 interrupt.

Jit > of the accumulator in the +I instruction allowsexplicitlyresettingthe ,+T 5.0 memory even if themicroprocessor did not respond to it.


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+I and the Interrupt as! The +I instruction can also be used to perform serial data

transmission out of the 0Es +O3 pin. One bit at a time can be sent out serially over the +O3 pin.

Jit 4 is used to tell the microprocessor whether or not toperform serial data transmission

If ) then do not perform serial data transmission If ) then do.

The value to be sent out on +O3 has to be placed in bit 5 of theaccumulator.

Jit 0 is not used by the +I instruction

? i the +I I t ti t dif the


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?sing the +I Instruction to odify the

Interrupt as!s -xample: +et the interrupt mas!s so that

,+T0.0 is enabled) ,+T4.0 is mas!ed) and

,+T5.0 is enabled.

9irst) determine the contents of the accumulator

SD-

SDE

R7&5

SE

7&5

6&5

5&59 Ena4le 5&5 4it $ = $

9 Disa4le 6&5 4it # = #

9 Ena4le 7&5 4it " = $

9 ,llow setting the mass 4it ! = #

9 Dont reset the flip flop 4it = $

9 /it 5 is not +sed 4it 5 = $

9 Dont +se serial data 4it 6 = $

9 Serial data is ignored 4it 7 = $

$ # $$$$$ #

*ontents of acc+m+lator are: $,;

E( < Ena4le interr+pts incl+ding ()TR

3( , $, < 0repare the mas to ena4le RST 7&5 and 5&5 disa4le 6&5

S( < ,ppl1 the settings RST mass


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Triggering Cevels

,+T 5.0 ispositive edge sensitive. (hen a positive edge appears on the ,+T5.0 line) a logic is

storedin the flip%flop as a 1pending2 interrupt.

+ince the value has been stored in the flip flop) the line does nothave to be highwhen the microprocessor chec!s for the interruptto be recogniAed.

The line must go to Aero and bac! to onebefore a new interruptis recogniAed.

,+T 4.0 and ,+T 0.0 are level sensitive. The interrupting signal must remain present until the

microprocessor chec!s for interrupts.

3etermining the Burrent as!


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3etermining the Burrent as!

+ettings

,I instruction: ,ead Interrupt as!Coad the accumulatorwith an %bit pattern

showing the status of each interrupt pin and

mas!.

(nterr+pt Ena4le

Flip Flop

RST 5&5

RST 6&5

RST 7&5

5&5

6&5

7&5

RST7&5 emor1

SD(

07&5

06&5

05&5(E

7&5

6&5

5&5

$#"!567


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8ow ,I sets the 'ccumulatorEs

different bits

SD(

07&5

06&5

05&5(E

7&5

6&5

5&5

$#"!567

RST5&5 as

RST6&5 asRST7&5 as 8

$ 9 ,%aila4le

# 9 ased

(nterr+pt Ena4le

3al+e of the (nterr+pt Ena4le

Flip Flop

Serial Data (n

RST5&5 (nterr+pt 0ending




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The ,I Instruction and the

as!s Jits %; show the current setting of the mas!for

each of ,+T 5.0) ,+T 4.0 and ,+T 0.0 They return the contents of the three mas! flip flops.

They can be used by a program to read the mas! settings inorder to modify only the right mas!.

Jit < shows whether the mas!able interrupt

process is enabled or not. It returns the contents of the Interrupt -nable 9lip 9lop.

It can be used by a program to determine whether or notinterrupts are enabled.


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The ,I Instruction and the

as!s Jits >%4 show whether or not there arepending

interruptson ,+T 5.0) ,+T 4.0) and ,+T 0.0 Jits > and 0 return the current value of the ,+T0.0 and

,+T4.0pins.

Jit 4 returns the current value of the ,+T5.0 memory flip flop.

Jit 5 is used for +erial 3ata Input. The ,I instruction reads the value of the +I3 pinon the

microprocessor and returns it in this bit.


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6ending Interrupts

+ince the 0 has five interrupt lines) interrupts

may occur during an I+, and remain pending.

?sing the ,Iinstruction) the programmer can readthe status of the interrupt lines and find if there are any

pending interrupts.

The advantage is being able to find about interrupts on,+T 5.0) ,+T 4.0) and ,+T 0.0 without having to

enable low level interrupts li!e I$T,.


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?sing ,I and +I to set

Individualas!s -xample: +et the mas! to enable ,+T4.0 without

modifying the mas!s for ,+T0.0 and ,+T5.0. In order to do this correctly) we need to use the ,I

instruction to find the current settings of the ,+T0.0and ,+T5.0 mas!s.

Then we can use the +I instruction to set the mas!susing this information.

Fiven that both ,I and +I use the 'ccumulator) wecan use some logical operations to mas!s the un%neededvalues returned by ,I and turn them into the valuesneeded by +I.



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SD-

SDE

R7&5

SE

7&5

6&5

5&5

$ $ $$$$$ #


Individualas!s 'ssume the ,+T0.0 and ,+T5.0 are enabled and the interrupt process is

disabled.

,I K ,ead the current settings.

O,I 8 K

K +et bit > for +-.

'$I 38 K

K Turn off +erial 3ata) 3onEt reset

K ,+T5.0 flip flop) and set the mas!

K for ,+T4.0 off. 3onEt cares are

K assumed to be .

+I K 'pply the settings.

,cc+m+lator

SD(

07&5

06&5

05&5

(E7&5

6&5

5&5

$ # $$$$$ $

$ # $$$$$ #

$ $ $$$$$ #


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T,'6

T,'6 is the only non%mas!ableinterrupt. It does not need to be enabled because it cannot be disabled.

It has the highest priorityamongst interrupts.

It is edge and level sensitive. It needs to be high and stay high to be recogniAed.

Once it is recogniAed) it wonEt be recogniAed again until itgoes low) then high again.

T,'6 is usually used for power failure andemergency shutoff.


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Internal Interrupt 6riority

Internally) the 0 implements an interruptpriority scheme. The interrupts are ordered as follows:

T,'6

,+T 5.0

,+T 4.0

,+T 0.0

I$T,

8owever) T,'6 has lower priority than the 8C3 signalused for 3'.


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The 0 Interrupts

Interrupt$ame

as!ableas!ingethod

&ectored emoryTriggering ethod

I$T, 7es 3I / -I $o $oCevel

+ensitive

,+T 0.0 /,+T 4.0

7es3I / -I

+I7es $o

Cevel+ensitive

,+T 5.0 7es3I / -I

+I

7es 7es-dge

+ensitive

T,'6 $o $one 7es $oCevel

-dge+ensitive


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'dditional Boncepts and

6rocesses 6rogrammable Interrupt Bontroller ;0@ '

' programmable interrupt managing device

It manages interrupt re=uests. It can vector an interrupt anywherein memory

without additional 8/(.

It can support levelsof interruptpriorities.

The priority scheme can be extended to 4> levels

using a hierarchy f ;0@ device.


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The $eed for the ;0@'

The 0 I$T, interrupt scheme presented earlier hasa few limitations: The ,+T instructions are all vectored to memorypage 8)

which is usually used for ,O. It re=uires additional hardwareto produce the ,+T

instruction opcodes.

6riorities are set by hardware.

Therefore) we need a device li!e the ;0@' to expandthe priority scheme and allow mapping to pages otherthan 8.


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Interfacing the ;0@' to the 0De%& 7

De%& 6

De%& 5

De%&

De%& !

De%& "

De%& #

De%& $

'

"5

>

,

'$

'

5

()T,

()TR

,D7,D6

,D5

,D

,D!

,D"

,D#,D$

(7

(6

(5

(

(!

("

(#

($


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Operating of the ;0@'

The ;0@' re=uires the microprocessor to provide ;control words to set up its operation. 'fter that) thefollowing se=uence occurs:

. One or more interrupts come in.

;. The ;0@' resolves the interrupt priorities based on itsinternal settings


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Operating of the ;0@'

4. (hen the microprocessor receives the op%code forB'CC instead of ,+T) it recogniAes that the devicewill be sending 4 more bits for the address.

5. The microprocessor sends a second I$T'signal.. The ;0@' sends the high order byteof the I+,Es

address.

@. The microprocessor sends a third I$T'signal.

. The ;0@' sends the low order byteof the I+,Esaddress.

. The microprocessor executes the B'CC instructionand *umps to the I+,.


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3irect emory 'ccess

This is a process where data is transferred betweentwo peripherals directly without the involvementof the microprocessor. This process employs the 8OC3 pin on the

microprocessor The external 3' controller sends a signal on the 8OC3 pin

to the microprocessor.

The microprocessor completes the current operation and sendsa signal on 8C3' and stops using the buses.

Once the 3' controller is done) it turns off the 8OC3 signaland the microprocessor ta!es bac! control of the buses.

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8 Interrupts