Integrated ALD Web

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External Use

CENTURA ® INTEGRATED

GATE STACK SYSTEMControl. Down to the Last Atom.

Steve Ghanayem

Vice President and General ManagerSilicon Systems Group

2011 Semicon West BriefingJuly 12, 2011



External Use

These presentations contain forward-looking statements, including those regardingmarket outlooks; technology roadmaps; the proposed Varian merger; and Applied’s market positions, products, growth opportunities, strategies and business outlooks.These statements are subject to known and unknown risks and uncertainties that couldcause actual results to differ materially from those expressed or implied by suchstatements, including but not limited to: the level of demand for Applied’s products, whichis subject to many factors, such as uncertain global economic and industry conditions,demand for electronic products and semiconductors, government renewable energypolicies and incentives, and customers’ new technology and capacity requirements; the

satisfaction of conditions precedent to the proposed merger with Varian, including theability to secure regulatory approvals in a timely manner or at all; Applied’s ability to (i)develop, deliver and support a broad range of products and expand its markets, (ii) alignits cost structure with business conditions, (iii) successfully execute its acquisitionstrategy and realize synergies, (iv) obtain and protect intellectual property rights, and (v)attract, motivate and retain key employees; and other risks described in Applied’s SEC

filings. All forward-looking statements are based on management’s estimates, projections

and assumptions as of July 12, 2011, and Applied undertakes no obligation to update anyforward-looking statements.

Safe Harbor



External Use

INTERCONNECT-ENABLING PRODUCTS

New Products Released at 2011 Semicon West

3

TRANSISTOR-ENABLING PRODUCTS

Producer ® Black Diamond ® 3

Producer ® Nanocure™ 3

Centura ® DPN HD

-

Centura ® Integrated Gate Stack

Endura ® Versa™ XLR W PVD

Reflexion GT™ for Tungsten

Endura ® HAR Cobalt PVD

Vantage ® Vulcan™ RTP



External Use

Strained Silicon

High- Metal Gate

FinFET

The Transistor Is Undergoing a Revolution

4

90nm 65nm 45nm 32nm 22nm

Unrelenting innovation in materialsand structure to continue scaling



External Use

Engineering the High- Stack Layers

5

Source: Applied Materials Maydan Technology Center

Atomic-scale engineering

Material stabilityInterface layer precision

Source Drain

2 nmSii

Interface Layerr

High-



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Increasing Complexity of Dielectric Gate Stack

6

Today10 Years Ago

4XNUMBEROF STEPS

Nitridation

InterfaceLayer

High-Dielectric

Post-NitridationAnneal

SiO2

TOTAL STACK STEPS



External Use

Applied Leads in Gate Stack Production Experience

7

Nitridation#1

Interface Layer Formation#1

Post-Nitridation Anneal#1Applied’sMarketPosition

Centura DPNGate Stack System

PREVIOUS PROCESS SEQUENCE



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'02 '03 '04 '05 '06 '07 '08 '09 '10 '11E

Applied Leads in the Gate Stack Market

8

Fiscal Year

~$1B cumulativerevenue

GATE STACK SYSTEM SHIPMENTS



External Use

Applied Leads in Gate Stack Production Experience

9

Nitridation#1

Interface Layer Formation#1

Post-Nitridation Anneal#1Applied’sMarketPosition

Centura IntegratedGate Stack System

NEW PROCESS SEQUENCEUnder Continuous Vacuum

Integrated ALD High- new



Applied Materials ConfidentialSILICON SYSTEMS GROUPSILICON SYSTEMS GROUP

Interlayer Formation With Industry-Leading

Thermal Oxidation

10

Critical surfacepreparation for ALD

Scales down to 3Å forcutting-edge scaling



Applied Materials ConfidentialSILICON SYSTEMS GROUPSILICON SYSTEMS GROUP

Atomic Layer Deposition Process

First precursor adsorbed

as monolayer on surface Second precursoradsorbed as monolayer,reacts with first layer

Reaction by-products

purged and steps repeatedto form each atomic layer



Applied Materials ConfidentialSILICON SYSTEMS GROUP12

Nitridation “fixes” thedose and stabilizes thefilm

Anneal completesdielectric stack

processing

Nitridation and Anneal Complete the Stack



External Use

Why Does Integration Under Vacuum Matter?

…Because Interfaces Matter at 22nm

<15% ~50%

45nm

22nm

Interface toBulk Ratio

Si orr SiGee

Interface Layerr

High-k

Si or SiGe

High-k

or e

-Interface Layer

13



External Use

Interfaces Matter Physically…

…Air Exposure Causes Interfacial Contamination

Applied’s Integrated Flow

Non-IntegratedFlow

Si or SiGe

High-k

or e

-Interface Layer

No Air

Exposure

AirExposure Si or SiGe

High--

or eInterface Layer

Uncontrolledoxidation and

contamination

14



External Use

Interfaces Matter Even More Electrically…

…Yielding Chip Performance Benefits

Threshold Voltage

FullyIntegrated

Gate Stack

Air ExposureAfterInterface Layer

FullyIntegratedGate Stack

Air ExposureAfter Interface

Layer

Half-of-a-GenerationPerformance Boost

PeakMobility

For Lower Power Devices

5 to 10%HIGHER PEAKMOBILITY 20 to 40%TIGHTER

THRESHOLDVOLTAGEDISTRIBUTION(1)

15



External Use

The Gate Stack System for Atomic-Scale

Engineering

Centura platform is industry’sbenchmark for complex gatedielectrics

Atomic-level control of interfacelayer, high-and nitridation

Integrated system enables“nearly perfect” gate dielectrics

16



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