Industry Needs for Simulation Technology in Signal ...jsa.ece.illinois.edu/spi/anders.pdf · RBS RBS WCDMA RBS RBS RBS RBS BSC RBS 14.4 Kbps . 384 Kbps . 3.6 Mbps . 14 Mbps . 42 Mbps

In d u s t r y Need s f o r Sim u l a t io n Tec h n o l o g y in Sig n a l In t eg r it y & Po w er In t eg r it y

Bringing the networked society to life

SPI 2013, PARIS

Anders Ekholm | © Ericsson AB 2013 | 2013-05-09 | Page 2 (30)

›Background, High speed wireless ›PCB development challenges ›Goals & objectives ›Methods/Modeling ›Conclusions

Ag e n d a


› LTE (4G) <150Mbits/sec › WCDMA (3G) <30Mbits/sec › GSM (edge) <256Kbit/sec

› Tomorrow › 5G ? Mbits/s

W h e r e a r e w e w it h H ig h -s pe e d W IR E LE S S d a t a t o d a y ?

Today

M o b il e b r o a d b a n d s u b s c r ipt io n s

This slide contains forward-looking statements. Actual result may be materially different.


Have you ever left your mobile device behind? What was that feeling, emptiness, isolation, nakedness.

By now most people take high speed wireless communication for granted, anywhere and anytime.

M o bil c o m m u n ic a t io n To d a y

N E TW OR K E D S o c ie t y


› Even while you are sitting here you expect to be able to use your personal communication devices, and in a few years you have rapidly become used to have high speed data at all times, all locations.

Th e s e f a n t a s t ic w ir e l e s s po s s ib il it ie s h a s be e n d e v e l o pe d in <30 y e a r s .

› US wireless networks handled 1.1 Trillion Mbytes of data last year* (10e18 bytes, 1.1 Tera Mbytes, 1.1 Exabytes).

* Between July2011-July2012


› How much computing power will you need to send that traffic to a mobile device?

› How much high speed communication will we need to drive traffic to a mobile device?

M o bil e d a t a t r a f f ic

M S C

B S C

B S C


› Since we are communicating with mobile devices we need to feed a maximum speed data channel from a point in the network to a mobile device which moves, walks, rides a bike, drives a car or even travels by high speed train at 300Km/h or faster. The data will have to move from access point to access point (RBS) not for one user but for all users.

M o bil e Da t a t r a f f ic

RNC

RBS

RBS

RBS

RBS

RBS

RBS

RBS

RBS

RBS

BSC

RBS

14.4 Kbps

384 Kbps

3.6 Mbps

14 Mbps

42 Mbps

80-160 Mbps

HSPA

LTE

GSM

EDGE

HSPA Evolution

WCDMA

Core Network


› Robust design – No customer claims.

› Low manufacturing cost – High yield. – Low cost materials.

› High performance

– High bandwidth. – Low power.

In d u s t r y De s ig n g o a l s

S im u l a t io n t o o l s


› Analysis are important to verify and secure robustness. – Fault coverage. – Signoff analysis.

› Analysis are important to achieve low Manufacturing Cost.

– Do not primarily optimize SI/PI, optimize/balance cost with robust SI/PI. – Methods, models and tools need to be able to analyze this angle of the

problem, not just “simple” SI/PI.

De s ig n g o a l s im pa c t s o n S i & P I a n a l y s is


In digital design we can divide analysis in 4 major areas based on analysis methods.

S I/P I a n a l y s is To d a y

S ig n a l Qu a l it y

P o w e r In t e g r it y


All 4 areas are analyzed in three phases. › Constraints analysis

– To define constraints used in PCB Schematic/Layout design. – Mostly done early pre-layout stages.

› Signoff analysis – Done on the final PCB database to verify design before it is sent to

manufacturing.

› Parameter optimization – Often done after PCB is manufactured, optimize parameter settings

for memory controllers, SERDES buffers, parallel with lab verifications.

S I/P I a n a l y s is To d a y


S ig n a l Qu a l it y › Signal Quality analysis – Signoff analysis, large simulations 1K-10K nets, 4-24 layer PCB’s. – Automated signal verification to given criteria's. – Parameter variations, PVT variations, increases the number of

simulations needed to run. – Results needed in less than 24 hours.

› Analysis methods – Spice and IBIS circuit simulations, emphasis on IBIS for

performance. – Careful tradeoff between performance and accuracy for PCB trace

modeling. – Some sample correlation with lab measurements to verify model

quality.

S ig n a l Qu a l it y a n a l y s is


› Timing analysis – Analysis all timing critical interfaces, emphasis on DDR2, DDR3 and DDR4 interfaces – Full analysis of all signals in every interface over all PVT variations. – Large simulation databases.

Tim in g a n a l y s is

› Analysis methods – Spice and IBIS circuit simulations, emphasis on IBIS for performance. – Careful tradeoff between performance and accuracy for PCB trace modeling. – Worst case, Best Case and/or statistical timing analysis (DOE, Design Of

Experiments).


› SERDES analysis – Analysis of all multi-gigabit channels. – BER and eye mask compliance. – Specification S-parameter compliance. – Optimizing parameter setting of TX & RX. – Full analysis of all signals in every interface over all PVT variations.

› Analysis Methods

– IBIS AMI, LTI assumption, statistical & Time domain analysis. – Frequency domain & time domain analysis used for PCB/System

modeling. – Correlation with measured data is mandatory.

S E R DE S a n a l y s is


› Power Integrity – DC & AC analysis. – All voltage domains need analysis (10-50 voltage domains/PCB). – Signoff analysis.

› Analysis Methods – 2.5D analysis of PCB voltage distributions. – DC analysis for IR drops, High DC currents up to 60A/chip. – AC analysis for decoupling based on target impedance methods.

(Hard to estimate target impedance requirements, estimates of target impedance in time domain, which is used in analysis in frequency domain gives overdesign.)

– No SI/PI co-simulation is done so far.

P o w e r In t e g r it y a n a l y s is

P o w e r In t e g r it y


› RF analog and digital electronics are becoming similar, both are up to Microwave.

– RF design are high frequency, narrow band, noise sensitive. – Digital design are high frequency, wide band, some noise margin.

› Lab verification and simulation verification environments are coming

together, one is not enough both are working together. – Correlation of simulation work with lab measurements are critical. – Simulation over parameter variations and PVT variations is needed, can not be

practically done in lab measurements.

H ig h f r e q u e n c y e l e c t r o n ic s


› The digital components used today will use around 60A of current at lower than 1V.

› Digital units (PCB’s) will contain 6-7 of these

› Power Integrity is becoming critical, both DC and AC. – Methods needed for reasonable estimates of power consumption, peak currents. – Fast performance simulators needed to fit design project time plans. – High performance compute nodes needed which work with analysis tools to

increase simulation throughput.

P CB P o w e r De s ig n


› Power Integrity – Analyzing a full PCB will use between 64G-128Gbytes of memory. – With a few probe points (<10) will run for 24-48 hours. – All this is one voltage domain and we have 10-50 voltage domains.

› Design Project view – Post layout signoff analysis results needed within 24 hours. – Otherwise we will be forced to use less fault coverage. – Known lower fault coverage enforces overdesign & higher MC.

S o m e pe r f o r m a n c e r e q u ir e m e n t s e x a m pl e s


› From worst case analysis with expectation of 100% correct signal transmission to Statistical methods, Design of Experiments and BER, the transmission will have errors. Calculate/Estimate confidence intervals.

› Earlier we could accept to simulate/analyze the most sensitive part of our design, Now we have to analyze full designs, nothing is simple anymore.

E l e c t r o n ic d e s ig n is c o m in g t o a pa r a d ig m s h if t


Important modeling aspect are: › No model with cover all analysis. › Choose the right modeling standard for the needed analysis. › Tradeoff accuracy and performance.

Model quality › Easy availability of models. › Accurate out of the box? › How much correlation efforts are needed by the system user. › Performance of models? Can we get analysis results in time?

M o d e l in g


The major modeling standards used today are: › IBIS › IBIS-AMI › Spice › Touchstone

Timing models lack a standard today › Propriety modeling.

M o d e l in g


IBIS: SI & Timing analysis › Reasonably trustworthy models out of the box. › IC vendors are experienced with IBIS. › High performance models. › Some correlation work needed with lab measurements. › Availability is usually good.

IC vendor (model creator) & System user › Good working relationship needed, generally works well.

M o d e l in g


IBIS-AMI: SERDES analysis › Still not mature enough as a standard. › IC vendors are too inexperienced with IBIS-AMI. › Some high performance models exists. › Every model needs correlation work with lab measurements. › Availability is improving but not enough yet. IC vendor (model creator) & System user › A very good working relationship is needed, generally several redesign

reruns will have to be done by IC vendors before the models is usable.

M o d e l in g


Spice: › Standard language? (Many standards). › No standardized method of interfacing the models. › Reasonable accurate. › Slow performance. › Availability is limited. › Issues with parameter “scoping”. › Often encrypted models.

M o d e l in g


Touchstone: › Touchstone 2. › Touchstone (1). › Validate passive, causal. › DC point ? › Enough frequency points?

Timing models › Always extra works to get and define the timing parameters correctly

into the propriety model format your tools use. › Nomenclature issues with IC vendor & System user.

M o d e l in g


The presented material sets new requirements on analysis methods and tools and the algorithms they use. › We need more accurate results faster.

– Multi-processing algorithms?

› We need to analyze SI/PI non optimal solutions to reach MC goals. › We are pushing designs very close to their limits and even beyond the

limits with given BER and as a high volume manufacturer we need to make sure we are within that boundary.

M e t h o d s a n d A l g o r it h m s


Analysis needs more automation.

› Engineers are a limited resource.

› Simulation methods & algorithms needs to increase analysis throughput and minimize engineering time.

M e t h o d s a n d A l g o r it h m s


› Signal Quality and timing analysis are working design flows that still can benefit from performance tuning.

› SERDES & Power Integrity analysis need more accuracy & performance development. The analysis flows used by design projects needs more automation.

› A good working relationship between system user, models creators and EDA tool vendors are needed to get efficient workflows.

Co n c l u s io n s

Questions please.

Q & A


Documents

Industry Needs for Simulation Technology in Signal ...jsa.ece.illinois.edu/spi/anders.pdf · RBS RBS WCDMA RBS RBS RBS RBS BSC RBS 14.4 Kbps . 384 Kbps . 3.6 Mbps . 14 Mbps . 42 Mbps