Incremental Physical Design - VAST labcadlab.cs.ucla.edu/~cong/slides/ispd2k.pdfIncremental Physical Design Jason Cong UCLA Majid Sarrafzadeh Northwestern 2 Jason Cong ISPD 2000: April

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Jason CongMajid SarrafzadehISPD 2000: April 10-12 C

Incremental Physical Design

Jason Cong UCLA

Majid Sarrafzadeh Northwestern

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Outline

l PART I: Introduction & Motivation

l PART II: Partitioning, Floorplanning, and Placemenet

l PART III: Routing

l PART IV: Conclusion

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PART I:Introduction & Motivation

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Introduction & Motivation

l Concurrent optimization:l problems are getting complex

l need quick evaluation of a number of alternatives

l Existing algorithms are “incremental”l what can we say about the quality of the final solution?

l when to do, and how much, incremental “moves”?

l A more fundamental concept: Given a solution, assessits quality

l Design for change

l The right data structures

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Current Methods

l Ad-hoc (low-temp annealing or rip-up and reroute)

l No or very little understanding of the solution quality

l Painful and slow updates

l May have undesired global impact

l There has been very little done on the topic

l (We provide a reasonable list of references as a startingpoints: data structures, layout algorithms, synthesisalgorithms, etc)

l Today’s presentation is meant to serve as a motivator

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PART II:Partitioning, Floorplanning, and

Placement

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Partitioning

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Incremental Partitioning

l An original (hyper)graph and its near-optimal partitioningresults are given.

l An incrementally changed (hyper)graph is obtained byadding/deleting vertices/edges from the original graph.

l Incremental partitioning problem is to find the near-optimal partitioning for the changed (hyper)graphwithout doing from the scratch.

l Incremental partitioning should be much faster than theoriginal partitioning.

l It is preferable to use the existing partitioning results forthe original (hyper)graph.

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Original Graph

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One Vertex Changed (e.g., resized)

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One Edge Added (logic restructuring)

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3rd Vertex Changed

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0-proximity Vertices

0-proximity

0-proximity

0-proximity

0-proximity

0-proximity

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0-proximity

0-proximity

0-proximity

1-proximity

1-proximity

0-proximity

0-proximity1-proximity

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0-proximity

0-proximity

0-proximity

1-proximity

1-proximity

0-proximity

2-proximity

1-proximity 0-proximity

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Partitioning Problem on the OriginalGraph

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Partitioning Problem on theChanged Graph (inf-threshold)

0-proximity

0-proximity

0-proximity

1-proximity

Changed Vertices

0-proximity

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0-Threshold IncrementalPartitioning

0-proximity

0-proximity

0-proximity

0-proximity

0-proximity

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1-Threshold IncrementalPartitioning

0-proximity

0-proximity

0-proximity

1-proximity

1-proximity

0-proximity

0-proximity

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Incremental Partitioning with 1%Change In the Original Graph

0

0.2

0.4

0.6

0.8

1

1.2

ibm01 ibm02 ibm03 ibm04 ibm05

0-threshold 1-threshold

2-threshold inf-threshold

Net-cut results normalized to infinity-threshold results.

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0

0.2

0.4

0.6

0.8

1




Runtime normalized to infinity-threshold results.

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Some more ideas

l Localized proximity

l Net-list dependent proximity

l New/ targeted algorithms (not “locked full partitioner ”)for incremental partitioning

l Create an initial solution that is suitable for change

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Floorplanning

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Incremental Floorplanning

l Do not resize the floorplan if not needed or if not needed“badly” (based on an enhanced sizing tree) [Crenshaw-Sarrafzadeh]

Time Ratio Plot

1

10

100

1000

10000

Vec1x Vec5x Vec10x Vec50x Vec100x

Vector File

Ex10

Ex20

Ex50

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A slack based sizing tree(for quick decision making)

w+ - slack in widthh+ - slack in height

Horizontal critical pathVertical critical path

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1

2 3

4

5

7

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105

4

5

5

5

87

8

1011

14

7

7

8-7

2

1 6

53w+=0h+= 2w+=0

h+= 0

w+=0h+= 0

w+=3h+= 0

w+=0h+= 2

w+=0h+= 0

w+=0h+= 0

4

w+=0h+= 0

w+=0h+= 0

w+= 1h+= 0

w+=2h+= 0

10-8

TSSmodule width height

1 3 22 0 23 0 44 3 05 2 06 0 0

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Speed-up after a series of moves(adding buffers, sizing, gate duplication

User Times for Finding Area Improving Moves

0.00

100.00

200.00

300.00

400.00

500.00

600.00

700.00

800.00

900.00

fract

-40

fract

-50

fract

-60

fract

-70

fract

-90

stru

ct-9

0

stru

ct-1

00

stru

ct-1

20

stru

ct-1

30

stru

ct-1

50

primary

1-70

primary

1-80

primary

1-90

primary

1-100

primary

1-130

primary

2-70

primary

2-80

primary

2-90

primary

2-120

primary

2-150

benchmarks

CP

U r

un

tim

e (s

)

slack-aware

greedy-local

greedy-global

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(Floorplan) Design for Change

l Accurate data is not available in early phases:l Missing cells: Some cells have not been designed yet. Use

estimates from previous design.l Formulate designer’s experience in estimation of the cell area.

l Evolving (cell / IP) library: Final area of modules can be estimatedfrom current area.

l Geometric synthesis, timing improvement, ….

l Nostradamus: A Floorplanner of Uncertain Designs [Bazargan-Kim-Sarrafzadeh]

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Problem Formulation

l Distribution lists for width/height:

l Wi = { (wi1,p(wi1)),…,(wi,mi,p(wi,mi)) } Σj p(wij) = 1

l Hi = { (hi1,p(hi1)), … , (hi,ni,p(hi,ni)) } Σj p(hij) = 1

l Example:l W1 = { (5,0.3) , (7,0.5), (8,0.2) }l W2 = { (2,0.9), (3,0.1) }

l H1 = { (1,.1),(2,.2),(7,.7) }l H2 = { (4,.4),(6,.6) }

l We could also use:l Li = { (wi1, h i1, pi1), … , (wim, him, pim) }

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Output Distributions

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Input/Output CorrelationWidth: Input and output std dev of diff data sets

020406080

100120140

a1 a3

b1

b3 c1 c3 c5 d1 d3

e1 e3 f1 f3 g1

h1 h3

c6f1

data sets

std

de

v

Ouput deviation Scaled input deviation

Height: Input and output std dev of diff data sets

01020304050607080

a1

a3 b1

b3 c1 c3 c5 d1 d3

e1

e3 f1 f3 g1 h1

h3

c6f1

data sets

std

de

v

Output deviation Scaled input deviation

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Experimental Results

Ratio of actual area of traditional methods to area of Nostradamus : 30% uncertainty

0%

20%

40%

60%

80%

100%

120%

140%

a1 a2 a3 a4 b1 b2 b3 b4 f1 f2 f3 f4 g1 g2

Conservative Optimistic Exp. Val.

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Ratio of actual area of traditional methods to area of Nostradamus : 10% uncertainty

0%

20%

40%

60%

80%

100%

120%

140%

a1 a2 a3 a4 b1 b2 b3 b4 f1 f2 f3 f4 g1 g2

Conservative Optimistic Exp. Val.

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Placement

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Placement Problem

Input:• A set of cells and their complete information (a cell library).• Connectivity information between cells (netlist information).

Output:• A set of locations on the chip: one location for each cell.

Goal:• Total chip area and wirelength, under timing constraints.

Challenge:• Rapid growing circuit size (> 1 million).• Multi objectives (timing constraint, routability)

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Placement Problem

Input:Cells and Interconnections

Output:Locations on a 2-D plane

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Predictors based on the given algorithm or based onabsolute truth

A bad placementA good placement

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Placement Algorithms (both incremental, so do

we understand incremental?)

l Constructive Placemente.g. Analytical optimizationBuild up placement from scratch.Fast, but most of them lack of solution quality.

l Iterative Improvemente.g. Simulated annealingGradually improve existing solutions.Slow, but with good solution quality, easy toconsider multi-objectives.

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Incremental Placement

Caused by:

l Adding cells/nets

l Meeting timing constraintswhile minimizing total chip area.

l Reducing congestionA post processing algorithm is more effective

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Proximity In Placement

Topological Proximity Geometrical Proximity

A

B

C

BA

Cell A and B are topological proximate Cell A and B are geometrical proximateIn a good placement, topological proximity and geometrical proximity generally correlate well

C D

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Preliminary studies

Reducing length of long net

Helps meeting timing constraints

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Shrinking long nets

Pick up cells which are located on the edge of theBounding box, switch them with other cells.

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Experimental setup

Given a placement produced by a fresh placement run,

find the longest nets,Let its length be L, then find all the nets which arelonger than (1-x%)*L, reduce all these long nets to (1-x%)*L or less.Data reported are number of long nets and x%

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Experiment results

It is not difficult to reduce the longest net by up to 20% without considerably increasing the total wirelength

N/A131.85%100.14%20.06%125114avql

1.67%60.78%50.16%30.03%121854avqs

N/A50.06%10.04%10.01%115059industry3

N/A39N/A170.48%60.06%212142industry2

N/A132.48%70.37%30.06%12907Primary2

�WL# nets�WL# nets�WL# nets�WL# nets

30%20%10%5 %

Length of long nets are reduced to (1-x)% of longest net

#cellsCircuit

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Experiment results

Experiments of Shrinking Long Nets

0.00%

0.50%

1.00%

1.50%

2.00%

2.50%

3.00%

3.50%

0% 5% 10% 15% 20%

Long nets length reduction

To

tal

WL

in

cre

as

e

primary2 industry2 industry3 avqs avql

It’s a greedy, simple approach.More effective algorithms are to be studied.

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PART III:Incremental Routing

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Incremental Routing Problem

l Basic operations:l Net removal (easy)

l Net addition (focus of this talk)

l Objectivel Preserve as much previous results as possible

l Applicationsl Changes of the netlist due to functionality modification

l Modification of placement due to performance consideration

l Change of a route (width, spacing, possible buffer insertion)after post-layout extraction and simulation

l ...

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Sub-problems in IncrementalRouting

l Single Net Routing

l No change of existing routes

l Rip-up and Reroute

l Change some existing routes but no change of

placement/floorplan

l Incremental Floorplan and Placement Update

l Invoke when Rip-up & re-route fails

Increasing flexibility

Increasing runtime

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Single Net Routing Problem

l Problem FormulationGiven

- a set of existing routes/obstacles

- the width and spacing of a given net

Find a valid route for this net

l Need for gridless (GLS) routingl Variable wire width for delay optimization

l Variable wire spacing for noise constraints

l Challengesl Construction of GLS routing graph

l Representation of GLS routing graph

l Search on GLS routing graph

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Existing Approaches to GLS SNR

l Obstacle expansionl Reduced to zero-width routing

l Construction of routing graphl Tile-based approach

l Point-based approachl Uniform grid graph

l Non-uniform grid graph

l Search on the routing graph

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Obstacle Expansion for Gridless Routing

l Expansion of Obstacles According to Width Rule andSpacing Rule to Reduce the Routing Problem intoZero Width Routing

Ww=4 Sw=2Ew=Ww/2+Sw

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Tile-based Approach[Margarino CAD’87; Sechen ISPD’98]

1. Tile Partition

2. Corner-Stitching Data Structure [Ousterhout, TCAD84]

3. A Tile-to-Tile Searching

s

t

T1

T2 T4

T3

T7

T5

T6

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Uniform Grid Approach [Lee’61]

Representing the region using uniform grids

Graph can be very large!

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Minimal Routing Graph Approach[Wu T-Comp’87; Zheng TCAD’96]

Extend the boundries of expanded rectangles

Sparser than uniform- grid but irregular

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Limitations of Existing Approachesfor Incremental Routing

l Pre-expansion of obstacles - very costlyl Need to re-expand if routing a net of different width and/or spacing

l Pre-construction of routing graph - very costlyl Incremental route may use only a small portion of the graph (but

cannot be determined a priori)

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S

T

Non-Uniform Grid Graph Approach[Cong-Fang-Khoo, ICCAD’99]

l Given a set of obstacles and a source s and sink tl GS is an orthogonal grid graph

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S

T

Implicit Representation of GS

y1

y2

y3

y4

y5

y6

y7

y8

x1 x3 x4x2 x5 x6 x7 x8 x9 x10

l Store x, y locations in arraysl Space Pre-construction

l Can be maintained incrementally (O(logN) time)

)(NO )log( NNO

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S

T

Searching on GS

y1

y2

y3

y4

y5

y6

y7

y8

x1 x3 x4x2 x5 x6 x7 x8 x9 x10

l Determine the Location of Neighboring Node: Easy

Free?

l Determine If the Location Is Valid: Difficult

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No Pre-Expansion of Obstacles

l Point enclosure query -> rectangle intersection query

a

b

dc

q

a

b

dc

q

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Our 2-D Query Data Structure

a

b

dc

q

Data Structure

Is q in free space

Query

c b,d

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70117225668232741.5 x 3192.8Eco-7

37224013959232926.1 x 1676.8Eco-6

1969477542231556.6 x 1676.8Eco-5

2326336417231372.5 x 1608.6Eco-4

2320046417531372.5 x 1593.3Eco-3

2324536417231372.5 x 1593.3Eco-2

2323096417331372.5 x 1593.3Eco-1

RectsCellsPinsLayersDimensionEx.

l Examples

l Comparisonl Explicit Uniform Grid Graph

l Iroute from Magic Layout Editor [Arnold 88]

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Comparison of Memory UsageUnit: MB

3.01.0014.3Ratio

84.743.6641.1Eco-7

52.615.9359.4Eco-6

35.212.7191.0Eco-5

32.610.9161.7Eco-4

32.67.2160.2Eco-3

32.710.9160.2Eco-2

32.710.9160.2Eco-1

IrouteNon-Uni. GridUni. GridsEx.

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Comparison ofRuntime and ECO Routing Quality

47591 / 2079.7935690 / 7438.2Eco-7

56423 / 2074.2937858 / 7024.7Eco-6

34543 / 1243.1427061 / 5412.3Eco-5

24385 / 15357.3921760 / 12224.0Eco-4

36593 / 10368.7034736 / 11034.5Eco-3

13162 / 6226.5811332 / 446.3Eco-2

22629 / 8942.1517374 / 6619.1Eco-1

Iroute

Result(wl/vc)Time(s)

Non-Uniform

Result(wl/vc)Time(s)

Ex.

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placement/floorplan




Increasing runtime

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Rip-up and Reroute

l Invoke when net-by-net routing fails

l Objectivesl Complete all the nets

l Minimize number of rip-ups

l Challengesl Gridless nature of routing problem makes routing resource

difficult to model and manage

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Overview of Existing R&R Approaches

l Maintain Design-Rule Correctnessl Pros: always has a valid partial solution

l Cons: too restrictive; net order dependent

l Allow Temporary Design-Rule Violationl Pros: allow cross and touch [Kawamura ICCAD’90], more flexibility

l Cons:l Difficult to model routing resources in gridless routing

l Lack of global picture

l Planning Based Ripup and Re-routel Preferred approach

l Can model routing resources with flexible resolution

l Allow a more global view

l Can be applied iteratively

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Planning Graph Construction

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Planning Based Rip-up & Re-route

l Advantagesl More Global Picture

l Reasonably Accurate Routing Region Information

l Very efficient on the planning graph

l Similar to global routing, but only serve as a guide

l Re-planning Approachesl Local Refinement

l Ripup and Re-plan

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Local Refinement

S1

S2

S3

T1

T2T3

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Local Refinement

S1

S2

S3

T1

T2T3

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Local Refinement

S1

S2

S3

T1

T2T3

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Ripup & Re-planning

S1

S2

S3

T1

T2T3

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placement/floorplan




Increasing runtime

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Incremental Floorplan andPlacement Updatel Problem Formulation

l When rip-up and re-route fails, determine how to complete thedesign with minimum changes of the floorplan and/or placement

l Need efficient heuristics to decide what routing regionsto enlarge

l May apply compaction/de-compaction techniques

l Earlier discussions on incremental floorplan andplacement also apply

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Conclusions

l Design iteration is unavoidable

l Incremental PD is an important enabling technology to

allow design convergence

l Trade-off of efficiency, preservability, and design quality

is the key issue in incremental designs

l Much work is needed in this area

l Need to start thinking about “Design for Incremental

Changes” (DFI)

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Acknowledgements

l NSF, DARPA, and Fujitsu Laboratories

l Jie Fang and Kei-Yong Khoo from UCLA

l Kiarash Barzagan, Maogang Wang, and Xiaojian Yang

from Northwestern Univ.

Documents

Incremental Physical Design - VAST labcadlab.cs.ucla.edu/~cong/slides/ispd2k.pdfIncremental Physical Design Jason Cong UCLA Majid Sarrafzadeh Northwestern 2 Jason Cong ISPD 2000: April