IMPLEMENTATION OF CARRIER FREQUENCY OFFSET …web.ee.nchu.edu.tw/~ljh/pdf/J2_Implementation of carrier frequency... · Robert C. H. Chang, C. H. Lin, K. H. Lin and C. L. Huang: Implementation

Robert C. H. Chang, C. H. Lin, K. H. Lin and C. L. Huang: Implementation of Carrier Frequency Offset and IQ Imbalance 251 Compensation in OFDM Systems

Short paper

IMPLEMENTATION OF CARRIER FREQUENCY

OFFSET AND IQ IMBALANCE COMPENSATION IN

OFDM SYSTEMS *

Robert Chen-Hao Chang and Chih-Hung Lin

Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan

Kuang-Hao Lin

Department of Electronic Engineering, National Chin-Yi University of Technology, Taichung, Taiwan

Chien-Lin Huang

Department of Design Service, National Chip Implementation Center, Hsinchu, Taiwan

ABSTRACT

This work presents a low-complexity architecture compensating for carrier fre-quency offset (CFO) and IQ imbalance circuits in OFDM receiver systems. A coordinate rotation digital computer (CORDIC) based sinusoid iteration generator (CSIG) is also developed for CFO estimation and correction in wireless local area network (WLAN) communications. Besides the main effect from the multi-path, some non-ideal effects from imperfect hardware design should also be considered such as the IQ imbalance from direct conversion in RF front-end. The improved low-complexity time-domain compensation algorithm is adopted to replace the traditional high-order equalizer. The integrated CFO and IQ compensation circuits reduce 15.7% of area by using hardware sharing. The proposed architecture with high precision is simulated and implemented by TSMC 0.18um CMOS technology. The design occupies about 133k equivalent gate count and 1.339mm2 core area.

Key words: IQ imbalance, carrier frequency offset (CFO), Synchronization, OFDM, ar-

chitecture.

Manuscript received Feb. 27, 2010; revised Apr. 13, 2010; and accepted June 17, 2010. This work was supported in part by the National Science Council (NSC), Taiwan, R.O.C. under Grant NSC 98-2221-E-005- 086-MY2 and NSC 98-2218-E-167-004.

I. INTRODUCTION

Wireless local area networks (WLANs) have been rapidly deployed and extended worldwide in recent years. The development of wireless consumer electron-ics for high data-rate transmission has become an im-portant research field. Orthogonal frequency division multiplexing (OFDM) has been widely applied in WLAN communications due to its high data rate. OFDM is a spectrally efficient signaling technique for commu-nication over frequency selective fading channel. Un-fortunately, OFDM is also sensitive to non-ideal front- end effect and imperfect synchronization, which result in

IQ imbalance and carrier frequency offset (CFO) errors. Thus, the errors would significantly degrade the per-formance of the communication receiver. Various stud-ies have considered IQ imbalances and CFO respectively [1]-[4].

The OFDM procedure raises the transmission data rate, but it is sensitive to frequency. To solve this prob-lem, the proposed architecture manages the timing and carrier synchronization efficiently with a precise digital oscillator and a re-modified Booth multiplier. The coor-dinate rotation digital computer (CORDIC) based sinu-soidal iterative generator (CSIG), divisor, and the timing controller are presented for synchronization. The CORDIC processor is widely used for synchronization in the OFDM receiver [5].

INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING, VOL.17, NO.4 PP.251-259 (2010)

252 INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING, VOL.17, NO.4 (2010)

Zero-intermediate-frequency (zero-IF) receivers are particularly interesting, because they save the cost of IF components. However, zero-IF front-ends also introduce additional severe front-end distortion, such as IQ imbal-ance [6]. The increase in required transmission speed of the WLANs means that a higher-order modulation of quadrature amplitude modulation (QAM) is required to improve the data rate. Thus, the IQ imbalance causes a severe degradation of demodulation performance. Za-reian and Vakili [7] developed an easy theoretical analy-sis and derived the exact BER performance of M-QAM-OFDM over an additive white gaussian noise (AWGN) channel in the presence of IQ imbalance. The IQ imbalance results from a nonideal front-end compo-nent due to the power imbalance or the non-orthogonal-ity between inphase (I) and quadrature (Q) branches. Especially in the increasingly popular zero-IF or direct conversion receiver architectures, analog IQ separation is performed and IQ imbalance is almost unavoidable [8]. An equalizer is generally adopted to implement the IQ imbalance compensation circuit. However, the complex-ity of the equalizer makes it difficult to implement in hardware. Therfore, low-complexity digital algorithms of the IQ imbalance compensation can be developed to design and implement wireless transceivers.

Several methods for compensating IQ imbalance in OFDM transmission were presented [9]-[11]. Held et al. [9] presented a non-adaptive time-domain method for estimating and correcting IQ imbalance in OFDM WLAN receivers. Tubbax et al. [10] presented a com-pensation method that eliminated the IQ imbalance based on one OFDM symbol. Their method performed well in the presence of phase noise. Xing et al. [11] ap-plied a pilot-based (frequency-domain) scheme for both frequency offset and IQ imbalance compensation at the baseband. The proposed hardware architectures with low-complexity digital IQ imbalance and CFO compen-sation are practically implemented in OFDM receivers to eliminate distortions and carrier offset in the time do-main.

II. SYSTEM BLOCK DIAGRAM

Synchronization is an essential task to receive transmitted data reliably in a digital communication sys-tem [12]. The PLCP preamble in the IEEE 802.11a standard is designed for synchronization. The first seven short preamble symbols are used for automatic gain con-trol (AGC) and frame detection. The last three short preamble symbols are used for timing estimation and coarse CFO estimation. In addition, the channel estima-tion and the fine CFO estimation are then performed by the two long preamble symbols. In the proposed system, AGC and the clock synchronization are performed be-fore the step of frame detection, and the received signal r(t) is assumed to be affected by AWGN, Rayleigh fad-ing, frequency offset, and IQ imbalance effect.

Figure 1 shows the overview of IEEE 802.11a

Fig. 1 System block diagram of OFDM-based baseband re-ceiver.

baseband transmission, including the transmitter and the receiver. The transmitter comprises of the following components: a scrambler scrambling the transmit data, a convolutional encoder reducing the number of transmit-ted bits and increasing the coding rate, an interleaver preventing consecutive errors, a mapper modulating the subcarriers, and a windowing system. The receiver works in the opposite direction to the transmitter. More-over, some synchronization circuits resist the channel effect in the receiver. This study focuses on designing and implementing the synchronization circuits with IQ compensation in the receiver. In Fig. 1, the architecture is adopted to simulate and implement CFO and IQ im-balance compensation. The blocks with dotted lines de-note the channel effects. The CFO and IQ imbalance compensation blocks are implemented in time-domain to increase demodulation performance.

III. CARRIER FREQUENCY SYNCHRONIZATION

A. Timing Estimation

Timing estimation based on the short preamble in the burst mode OFDM is the process of identifying the beginning of the core of the first symbol [13]. The core is the ISI-free part of the symbol. The starting points of all symbol cores in a burst can be derived from the be-ginning of the core of the first symbol. The timing syn-chronization comprises of the frame detection and the symbol boundary detection. The symbol boundary and the end point of the short preamble can also determined, such that the start of coarse CFO estimation, fine CFO estimation, and FFT can be identified.

The received signal correlates with itself at the re-ceiver with a delay of one short symbol. A(n) denotes the autocorrelation, given by

16

1( ) ( ) *( 16)

kA n r k n r k n

== + + +∑ (1)

where r(n) denotes the received sequence, and the su-perscript * denotes Hermitian. This work adopts a fixed threshold written by

32

1( ) *( ) / 2.5auto

mTHR d n m d n m

=

⎡ ⎤= − ⋅ −⎢ ⎥⎣ ⎦∑ (2)


where d(n) denotes the known short preamble signal. After detecting the start of the frame, the receiver

can also utilize a sliding correlator to correlate the re-ceived signal with the waveform of the known OFDM symbol in the preamble to find the symbol boundary and to detect the short preamble end time. It means that the so-called cross-correlation correlator operates as a match filter, shown in Fig. 2. The 16-tap correlator is generated by the first known frame resulting in ten peaks given by

16

1( ) ( ) *( )

mC n r n m ref m

== + ⋅∑ (3)

where C(n) denotes the match filter output of the cross correlation at the time period n, and ref(m) denotes the complex value of the mth known sequence. However, a straightforward implementation of this correlator by the complex floating coefficients listed in Table I requires a highly costly and complex multiplier. Clearly, if the real and imaginary parts of the correlator coefficients can be expressed as sums of powers of two, the shifting and addition operations are required for the implementation, and the multiplication can be removed. The coefficients ref(m) is quantized into [0 −1 −j 1 1 1 −j −1 0 −j −1 j j j −1 −j] [14]. According to (2), the threshold of cross-correlation can be derived as THRcross=THRauto×10. Figure 3 shows the timing synchronization with the es-timated position, using auto-correlation and cross-cor-relation operations.

B. Carrier Frequency Offset

CFO causes two deleterious effects, namely the re-duction of signal amplitude in the output of filters matched to each of the carriers, and the introduction of ICI from other carriers. Therefore, the accurate carrier frequency synchronization scheme is very important in OFDM systems [15], [16]. The following derivation of the algorithm is based on perfect timing estimation and clock synchronization.

Assume that the transmission is under a slow fading channel such that the short symbol is similar. The corre-lator that takes Maximum Likelihood Estimation (MLE) for CFO is adopted. The IEEE 802.11a uses the last three short symbols for coarse CFO estimation. The fol-lowing algorithm can use any successive three short symbols to perform the coarse CFO after AGC is ob-tained.

To reduce the cost of the estimated coarse CFO ξ̂ hardware implementation, an adopted equation given by Peng and Wen [15] can be modified into

15* *

0( , ) ( 1, ) ( 1, ) ( 2, )

1ˆ arg2 2

s s s sn

s

Y k n Y k n Y k n Y k n

N=

⎛ ⎞⎡ ⎤+ + + +⎜ ⎟⎣ ⎦⎜ ⎟=⎜ ⎟⎜ ⎟⎝ ⎠

∑ξ

π(4)

where arg(.) denotes the argument and Ys(k,n) denote the received noisy output through the channel at nth sample of kth symbol. Equation (4) clearly reveals that the delay

Fig. 2 Architecture of the match filter.

Fig. 3 Timing synchronization with the estimated position.

Table 1 Correlator coefficients selected as the short OFDM waveform.

m ref (m) quantized

1 0.045999 + 0.045999j 0

2 – 0.13244 + 0.0023396j –1

3 – 0.013473 – 0.078525j –j

4 0.14276 – 0.012651j 1

5 0.091998 0 1

6 0.14276 – 0.012651j 1

7 – 0.013473 – 0.078525j –j

8 – 0.13244 + 0.0023396j –1

9 0.045999 + 0.045999j 0

10 0.0023396 – 0.13244j –j

11 – 0.078525 – 0.013473j –1

12 – 0.012651 + 0.14276j j

13 0 + 0.091998j j

14 – 0.012651 + 0.14276j j

15 – 0.078525 – 0.013473j –1

16 0.0023396 – 0.13244j –j


and correlated architecture of autocorrelation can be reused here besides frame detection. Thus, it is suitable for hardware design. The fine CFO estimation is similar to the derivation process of the coarse CFO with NL =64 indicating long preamble signals, yielding

1*

0

1ˆ ˆ ˆarg (0, ) (1, )2

LN

fine L LnL

Y n Y nN

−

=

⎡ ⎤= ⋅⎢ ⎥

⎣ ⎦∑ξ

π (5)

Where

( )ˆˆ ( , ) ( , ) exp 2 ( )L L LY m n Y m n j n N= ⋅ − +π ξ

with m=0,1. The phase shift increases in size, since the OFDM

symbols are received continuously. The small-phase rotation caused by CFO still occurs after OFDM sym-bols passing through FFT. According to each OFDM symbol, four pilot subcarriers exist with the value in-serted into the 48 data subcarriers. The rotated phase can be obtained

( )*, ,

21, 7,7,21

ˆ ˆarg l k l kk

Y P=− −

⎛ ⎞= ⎜ ⎟

⎝ ⎠∑φ (6)

where ,l̂ kY denotes signal k of symbol l, and Pl,k de-notes the pilot value at frequency subcarrier k. The re-ceived data are retrieved by the frequency and phase synchronization, given by

ˆ ˆ ˆˆ exp( 2 ( ) )k k finer r j k= ⋅ − + +π ξ ξ φ (7)

where k=0, 1, 2, …, and rk denotes the complex signals beginning from long symbols.

IV. IQ IMBALANCE COMPENSATION

A low-cost implementation of OFDM physical lay-ers is a challenge because of the impairments associated with the analog components. When the received radio- frequency (RF) signal is down-converted to baseband, two different receiver architectures are employed, which are the super-heterodyne receiver and the direct-conversion RF receiver with its potential for low-cost and low-power implementation on silicon. The direct con-version structure is introduced by popular zero-IF. Al-though the structure dispenses with expensive external IF filter and the image-rejection filter, it has disadvan-tages such as DC offset and IQ imbalance.

IQ imbalance can be characterized by two parame-ters: the amplitude imbalance K as a power mismatch between the I and Q branches, and the phase imbalance

εϕ yielding an orthogonality mismatch between the I and Q branches. A popular model for an IQ imbalance

impaired signal s = sI + jsQ is given by

'

'

[ ][ ] 0

[ ] sin cos [ ]

II I

Q Q Q Q

s ks k K

s k K K s k

⎡ ⎤⎡ ⎤ ⎡ ⎤⎢ ⎥= ⋅⎢ ⎥ ⎢ ⎥− ⋅ ⋅ ⎢ ⎥⎣ ⎦ ⎣ ⎦ ⎣ ⎦ε εϕ ϕ (8)

where s'I and s'Q denote the components of the unim-paired signal. The amplitude imbalance K is represented by the two symmetrical factors KI and KQ, while the phase imbalance is given by εϕ .

The IQ imbalance compensation circuit is tradition-ally designed by an equalizer, which corrects degrada-tion of demodulation performance. The advantage of using an equalizer is that increasing the tap order of the equalizer can improve the accuracy. However, the dis-advantage is that the equalizer may not be converged when the number of training symbols is too small, or the front-end channel variability rises. Therefore, a high- complexity digital equalizer circuit is required to per-form degradation correction to improve the demodula-tion performance. Since the implementation of the high- complexity equalizer hardware is very difficult, this study improves the time-domain compensation algo-rithm [9] to minimize hardware complexity and maintain stable performance because the IQ imbalance compensa-tion circuits can be shared with CFO circuits. A long preamble of L=64 estimated IQ imbalance compensation parameters is adopted herein. Equations (9) and (10) are employed to estimate the amplitude (Kest) and phase (Pest) of the IQ imbalance parameters respectively.

1

1

[ ] [ ]

[ ] [ ]

L

Q Qk

est L

I Ik

s k s k LK

s k s k L

=

=

⋅ +=

⋅ +

∑

∑

(9)

( )1

1

[ ] [ ]

[ ] [ ]

L

I Qk

est L

I Ik

s k s k LP

s k s k L

=

=

⋅ +=

⋅ +

∑

∑

(10)

Equations (11) and (12) are employed to compensate the amplitude and phase imbalances, respectively.

I I

Q Q

[ ] [ ]

1[ ] [ ]

est

w k s k

w k s kK

=⎧⎪⎨ =⎪⎩

(11)

I I

Q Q I2

[ ] [ ]

1[ ] [ ] [ ]

1est

est

w k s k

w k s k P s kP

=⎧⎪⎨ = ⋅ − ⋅⎪ −⎩

(12)

where WI and WQ denote IQ compensation accom-plished.


As shown in Fig. 4, we obtain the 64-QAM con-stellation after CFO compensation and FFT. However, there still exists phase shift and IQ imbalance with an amplitude imbalance of 3dB, SNR=25, and a phase im-balance εϕ =10°. Figure 5 shows the 64-QAM constel-lation is obtained after CFO and IQ imbalance compen-sation. Figure 6 shows the comparison of the bit error rate (BER) of demodulating signals with and without IQ imbalance correction in the AWGN channel. IQ imbal-ance is not apparent in lower-order QAM modulation. However, in higher-order QAM modulation, it will cause serious interference.

V. IMPLEMENTATION RESULTS

A. Timing Estimation and CFO Compensation

The timing estimation comprises autocorrelation

Fig. 4 64-QAM constellation impaired by amplitude and phase imbalance in AWGN.

Fig. 5 64-QAM constellation compensation by CFO and IQ imbalance compensation in AWGN.

with depth 16 and cross-correlation, called a 16-tap match filter. To detect the peak, the absolute value of autocorrelation and cross-correlation must be compared with some thresholds shown in Fig. 7. Autocorrelation plays an important role in synchronization circuits, since it is not only utilized in timing estimation, but also re-used in coarse CFO estimation, when a similar architec-ture is adopted in fine CFO estimation with depth 64. As shown in Fig. 8, the architecture of autocorrelation with depth 16 consists of delay registers, a complex multiplier, and a moving adder.

The absolute values of the outputs of autocorrela-tion and match filter must be taken before the signals go into the peak detector, as revealed in Fig. 7. To improve the precision, the absolute value should be obtained by taking the square value as

2 2 2abs I Q= + (13)

However, (13) requires multiplication, and also needs truncation. The value has been truncated once already before taking the absolute value. Hence, the following method is adopted

( ) ( )1max , min ,

2abs I Q I Q= + (14)

Equation (14) is more efficient than (13), and can reduce the area of the implementations.

CFO estimation comprises of coarse and fine CFO estimations. Coarse CFO estimation employs the real and imaginary parts of output values of the autocorrela-tion during the short preamble. To improve the precision, the operation of fine CFO estimation is similar to that of coarse CFO estimation, but fine CFO estimation is only adopted during the long preamble. The architecture of coarse and fine CFO estimation can be combined as de-picted in Fig. 9. To reduce the hardware area, the coarse and fine CFO estimation can adopt the same divisor, because they work at different times. The received

Fig. 6 Performance comparison for IQ imbalance with and without compensation.


Fig. 7 Block diagram of the timing estimation.

Fig. 8 Architecture of autocorrelation.

signals perform the first rotation by coarse CFO estima-tion and the second rotation by fine CFO estimation.

The upper part of Fig. 9 is an architecture of coarse CFO estimation. Once the real and imaginary parts of output values of the autocorrelation are obtained, the real part is given by I, and the image part is given by Q. Thus, the tangent value is computed by dividing Q/I. The ro-tated angle of CFO is calculated as θ=tan-1(Q/I). An arctangent table is needed to find the angle. If the angle (θ) is smaller than radian 0.5, then the quotient is ob-tained as (Q/I)=tanθ≒θ.

The CORDIC architecture is adopted to rotate the frequency offset vector to be the front-end of the CSIG, as shown in Fig. 10. If the initial vector is on the real axis, then the real axis signal X0 = 1, and the imaginary axis signal Y0 = 0. The auxiliary computing angle Z0 is a phase rotation that can be estimated by the autocorrela-tion. The stage controller is influenced by the signal Zout, and controls the shifters and the tan−1 table. The values of sinθ and cosθ are given as constants. The modified equations are given as

1 0 0

1 0 0

i i i

i i i

S S C C S

C C C S S+

+

= += +

(15)

where S0=sinθ and C0=cosθ. The sinusoid iteration ar-chitecture in Fig. 10 receives the real and imaginary signals from the CORDIC architecture. The stage con-troller starts the modified oscillation, and controls the iteration feedback computation. The last frequency ro-tated vectors (Si+1, Ci+1) are calculated from the current rotated vectors (Si, Ci) and the initial phase offset (S0, C0).

The architecture of fine CFO estimation is similar to coarse CFO estimation, except for the depth of autocor-relation, sixty-four. Additionally, since the angle de-tected by fine CFO estimation is very small, the value of sinθ can be viewed as θ, and the value of cosθ equals 1. That is, the architecture of fine CFO estimation does not

Fig. 9 Combinational circuit of the coarse and fine CFO esti-mation.

mux

mux

mux

mux

mux

Fig. 10 The CSIG architecture.

need CORDIC to calculate the first rotated vector. The initial values in (15) thus become S0=θ and C0=1.

B. IQ Imbalance Compensation

A received OFDM signal impaired by both ampli-tude and phase imbalance is compensated in two phases. One is amplitude imbalance estimation and compensa-tion performing according to (9) and (11); the other one is phase imbalance estimation and compensation per-forming according to (10) and (12). Figure 11 illustrates the foregoing correction method of hardware structure for IQ imbalance compensation.

The first step is to wait for the start trigger from the front-end signal when the long preamble symbol is de-tected. Then, the parameter Kest is calculated according to the amplitude estimation equation, and the amplitude compensation (I_A_ok and Q_A_ok) is obtained by the Amplitude Corrector (A.C.). The parameter Pest can be calculated based on the phase estimation equation and the phase compensation, and the unimpaired signal (I_ok and Q_ok) can be attained through the Phase Corrector (P.C.). The shaded calculation circuit block in Fig. 11 can be reused by 64-Auto hardware in Fig. 9 for reduc-ing hardware cost.

Figure 12 shows the flowchart of the control block that must be introduced for the hardware combination. There are four states (S0…S3) for the control block flowchart. The initial state is in S0 waiting for the long preamble to start the trigger. In S1, the length of the long preamble is counted to apply to Kest calculation after S0 is triggered. Amplitude estimation finish signal, which waits for the A.C. process to accomplish correction, is


Fig. 11 The block diagram of IQ imbalance compensation circuit.

Fig. 12 The flowchart of IQ compensation control block.

introduced in S2. Finally, in S3 the length of the long preamble is counted again to calculation Pest.

C. Simulation and Implementation Results

Figure 13 shows post-simulation results of IQ com-pensation with amplitude imbalance of 3dB equality KI =1 and KQ=1.4, phase imbalance of εϕ =10°, SNR=25dB, and 600 kHz frequency offset. The IQ compensation circuit operates when the CFO compensa-tion finishes frequency offset correction and the start_long signal becomes active. The estimation com-plete signal (IQ_ok) pulls high, and then the compensa-tion sequential data (I_ok and Q_ok) are obtained. The amplitude estimative value (K_est) is 01.011012, which equals 1.41. The P_est value is 111.11010010102, which equals −0.1777, and the phase imbalance estimation

εϕ = −arcsin(P_est) = 10.24°. Figure 14 shows the lay-out diagram of the CFO and the IQ imbalance compen-sation circuits, which contain the three functional blocks of the proposed circuit. Table II lists the implementation results including gate count, area and power. A Com-parison of the results is added in Table II, which shows that the proposed IQ compensation uses fewer gate count compared with Palipana et al. [17]. The integrated CFO and IQ compensation circuits reduce 15.7% of area by using hardware sharing, when the gate count from IQ compensation is reduced about 50%.

Fig. 13 Post-simulation of IQ compensation.

Fig. 14 The physical layout of the CFO and the IQ compensa-tion.

Table 2 Performance comparison of the proposed architecture.

CFO IQ CFO & IQ Combina-

tion

Palipana et al. [17]

Operation Fre-quency 20MHz 20MHz 20MHz -

Area 1.093 mm2

0.51 mm2 1.339 mm2 -

Gate Count 109k 51k 133k 56K

Power 9.858 mW

7.537 mW 16.572mW -

VI. CONCLUSION

This work presents the synchronization circuit for timing estimation, CFO estimation, and the IQ imbal-ance compensation in a wireless baseband receiver. The CSIG architecture for CFO estimation proposed for wireless systems reduces memory use and increases pre-cision. Also, the CSIG architecture can efficiently re-duce the hardware cost. Moreover, the low-complexity time-domain IQ compensation algorithm is adopted to implement the hardware architecture. This study uses system simulation to produce the test signals and verify the effectiveness of the compensation circuit via the cell- based design process. The proposed architecture is im-


plemented and verified by TSMC 0.18 µm CMOS tech-nology for the 600 kHz frequency offset and IQ imbal-ance in the AWGN wireless system. Consequently, it achieves three goals which are high precision, a small area of 1.339 mm2, and low power consumption of 16.572 mW.

ACKNOWLEDGMENTS

This work was supported in part by the National Science Council (NSC), Taiwan, R.O.C. under Grant (NSC 98-2221-E-005-086-MY2 and NSC 98-2218-E- 167-004) and in part by the Ministry of Education, Tai-wan, R.O.C. under the ATU plan. The authors would like to thank the National Chip Implementation Center (CIC) of Taiwan for technical support.

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Robert Chen-Hao Chang re-ceived both B.S. and M.S. degrees in Electrical Engineering from Na-tional Taiwan University, Taipei, Taiwan, in 1987 and 1989, respec-tively, and his Ph.D. degree in Electrical Engineering from the University of Southern California

(USC), Los Angeles, in 1995. In 1996, he joined the faculty of the Department of Electrical Engineering, National Chung Hsing


University, Taichung, Taiwan, where he is cur-rently a Professor. He has served as the Director of Meng Yao Chip Center from 2000 to 2004, the Director of the Center for Research and Devel-opment of Engineering Technology with in the College of Engineering from 2005 to 2006, and Chairman of the Electrical Engineering Depart-ment from 2006 to 2008. He has published more than 80 technical journal and conference papers. His research interests include power manage-ment IC design, low-power circuits design, and baseband circuits design. Dr. Chang was a recipient of the Distinguished Teaching Award and the Outstanding Research Project Award from National Chung Hsing Uni-versity in 2004 and 2006, respectively. He is a member of Tau Beta Pi. He has been an Associ-ate Editor for the IEEE TRANS. ON VLSI SYSTEMS since 2010. He has been a Member of VLSI Systems and Applications Technical Com-mittee, and Nanoelectronics and Gigascale Sys-tems Technical Committee, IEEE Circuits and Systems Society since 2004 and 2009, respec-tively. He also served as Technical Program Committee Member for many conferences.

Chih-Hung Lin received both B.S. and M.S. degrees in Electrical En-gineering from National Chung H s i n g U n i v e r s i t y ( N C H U ) , Taichung, Taiwan, R.O.C., in 1996 and 2002, respectively. He is cur-rently working towards his Ph.D. degree in the ICs and Systems re-

search group of the same department. His re-search interest is VLSI architecture design for communication.

Kuang-Hao Lin received both B.S. and M.S. degrees in Electronics En-gineering from Southern Taiwan University of Technology (STUT), Tainan, Taiwan, R.O.C., in 2001 and 2003, respectively, and his Ph.D. degree in Electrical Engi-

neering from National Chung Hsing University (NCHU), Taichung, Taiwan, R.O.C., in 2009. After graduate studies, he worked at Soc Tech-nology Center (STC) of Industrial Technology Research Institute (ITRI) in Hsinchu, Taiwan, R.O.C. In 2009, he became an Assistant Professor in the Department of Electronic Engineering, Na-tional Chin-Yi University of Technology, Taichung, Taiwan, R.O.C. His research interests include MIMO wireless communication systems, synchronization in digital communications, Channel Coding, and VLSI architectures design for communication.

Chien-Lin Huang was born in Taiwan, R.O.C., in 1985. He re-ceived both B.S. and M.S. degrees in Electrical Engineering from Na-tional Chung Hsing University (NCHU), Taichung, Taiwan, R.O.C., in 2006 and 2009, respectively. He is working in the National Chip

Implementation Center, Hsinchu, Taiwan, R.O.C.


Documents

IMPLEMENTATION OF CARRIER FREQUENCY OFFSET …web.ee.nchu.edu.tw/~ljh/pdf/J2_Implementation of carrier frequency... · Robert C. H. Chang, C. H. Lin, K. H. Lin and C. L. Huang: Implementation