Tutorials Tutorial 1 Foundations and Practical Design of CMOS Image Sensors Morning Session 9:00-12:30 Angel Rodríguez-Vázquez, PhD, Professor IEEE Fellow, IMSE-CNM, Universidad de Sevilla/CSIC AnaFocus Ltd, Sevilla, Spain

Abstract CMOS imagers are complex systems whose design requires quite different pieces of expertise, namely: pixels, analog signal processing, pixel readout and analog-to-digital conversion, digital signal processing, output drivers, etc. Confront-ing the design of new imagers require hence the concourse of multidisciplinary teams. However, because correct opera-tion calls for the close interconnection among the different parts, global knowledge is mandatory for successful design. This is particularly pertinent for the newer generations of smart imagers required for high-end applications and/or re-quiring ultra-high image capture, on-chip image correction, scene interpretation, high dynamic range capture, etc. All these features demand architectural and circuital innovations and pose significant challenges to designers. Also, the increased interest on sensors capable of capturing 3-D scenes raise new challenges at circuit level related to the neces-sity to interface pixels different from those employed for 2-D capture, on the one hand, and to extract and convert to digital domain time information, on the other hand.

This tutorial addresses the design of smart CMOS imagers by following a comprehensive and complete top-down ap-proach where each subsystem is contemplated and described as a part of a whole. Starting the formulation of the per-formance metrics used to specify and characterize imagers, the tutorial explains how the subsystem behavior and non-idealities impact on the global imager metrics, thereby setting the basis to specify the subsystems for given global image sensor specs. Such methodology is illustrated in the tutorial via a dedicated, MATLAB-based modeling tool which will be employed to allow the attendees gaining insight on the impact of non-ideal sub-systems behaviors. The tutorial over-views the state-of-the-art regarding: pixels; analog signal processing and read-out circuitry; data conversion circuitry, covering both amplitude data converters (required for 2-D images) and time-to-digital converters (required for 3-D imagers); driving circuits. Practical design recipes are given for all these circuits. Architectures and circuit solutions em-ployed for high dynamic range acquisition and embedded image processing are also reviewed. A case study is included where attendees are exposed to practical considerations to be taken during the design process, including the influence of packaging, optics and camera embedding.

Tutorial 2 Energy Harvesting Wireless Sensor Networks Morning Session 9:00-12:30 Hamada Alshaer, Senior researcher in the Etisalat BT Innovation Center (EBTIC), Khalifa University, Abu Dhabi, UAE. Bayan Sharif, Professor of Electrical and Computer Engineering, Dean of the College of Engineering at Khalifa, Abu Dhabi, UAE.

Abstract With universal and multi-disciplinary applications of wireless sensors, energy harvesting technologies emerge as vital to sustain wireless sensor networks lifetime and ensure network reliability through maintaining persistent data communi-cations. Energy harvesting wireless sensor networks (EH-WSNs) use energy harvesting sensor devices to harvest energy from the environment for immediate use or storage for future use. Several techniques exist for converting mechanical or electrical energy, light, or temperature differences into energy for powering sensors including piezoelectric, radio fre-quency, thermoelectric, inductive coupling, wind and solar power. However, the use of rechargeable sensor nodes faces several challenges, such as technical problems in practical implementation, the extremely low recharging speed due to typical ultra-low-power ambient energy, and the relay sensor node placement in wide sensor networks.

Numerous energy-aware routing protocols have been conceived for wireless sensor networks without energy harvesting capabilities, but only a small number of energy harvesting-aware routing protocols have been introduced to take advan-tage of the sustainable energy harvesting sources to increase wireless sensor networks lifetime. The applications of energy harvesting sensors are diverse, ranging from industrial and environmental monitoring, to smart buildings and grid asset monitoring. Energy harvesting provides new opportunities for sensor manufacturers in applications that would otherwise have difficulty obtaining a reliable power source or require batteries and the associated replacement effort and costs.

This tutorial is divided into three parts. The first part explains the concept of energy harvesting wireless sensor net-works. It reviews the characteristics and energy requirements of typical sensor network nodes, assesses a range of po-tential ambient energy sources, and outlines the characteristics of a wide range of energy conversion devices. The sec-ond part develops analytical models for the harvesting and consuming entities that characterize their achievable performance. It also discusses the main energy harvesting technologies and compares these diverse sources and conver-sion mechanisms in terms of their normalized power density. The third part analyzes and compares some state-of-the-art energy harvesting-aware routing algorithms for wireless sensor networks. It also explains other distributed protocols that schedule tasks in accordance with the environmental harvesting opportunity available at different network nodes.

Tutorial 3 Radio Frequency Integrated Circuit Design for Cognitive Radio Systems Morning Session 9:00-12:30 Amr Fahim, Semtech Corporation, Irvine, CA

Abstract Cognitive radios systems are defined as wireless communication systems that allows for intelligent sharing of spectrum with other users by dynamically allocating resources. As frequency spectrum becomes less available the need for sharing frequency spectrum led to increased interest in cognitive radios. One obstacle in designing cognitive radio is the inte-grated circuit implementation of such systems in an energy efficient manner, as to allow for longer battery lifetimes, as well as compact form to allow for ubiquitous use for multiple applications.

This tutorial considers an in-depth look at circuit design requirements and challenges for cognitive radios. Key issues in cognitive radio systems, such as spectrum management techniques and spectrum sensing are detailed. High-linearity, low-noise wideband receiver architectures are explored. This includes highly linear amplifiers, 'smart' RF filter and gain control design. The implementation of efficient wideband spectrum sensing techniques is also given. The performance requirements of highly linear wideband transmitter circuits and architectures suitable for cognitive radios are also ex-plored. Finally, challenges in frequency synthesizer design are detailed.

Tutorial 4 New trends in the Application of Formal Verification Technology in Digital Design Morning Session 9:00-12:30 Eman El Mandouh and Ashraf Salem, Mentor Graphics, Cairo, Egypt

Abstract Functional verification is a critical element in the development of today’s complex digital designs. Up to 70 percent of the design development time and resources are spent on functional verification. Functional bugs are still the number one cause of silicon re-spins. They are hard-to-verify structures for which traditional simulation based verification is inefficient. Accordingly Formal based verification becomes an emerging predominant methodology for performing hardware verification. Formal verification mathematically proves that a design property holds for all points of the search space. It comes in complement to simulation such that it needs no test bench or stimulus to operate, only the design intent (or specifications) described as properties (assertions, assumptions and cover statements) along with the design written in hardware description language are passed to the formal verification tool and assertions are examined whether they are proven to hold or found to falsify during the formal analysis session such that the given assumptions

are satisfied. In general, a design property is a codified statement about a specific intended behavior of the design that must hold true under normal operating conditions. An asserted property is a property that’s expected to be always true. In practice, formulating formal design properties is usually extracted from high-level specifications that are written in natural languages. Formal verification is performed by tools such as automatic theorem provers and model checkers. Model checkers analyze a model of the design along with its properties are able to formally/mathematically prove whether or not these properties are true. Formal methods indicate a pass/fail result for the properties, and in the event of failure, counterexamples can also be generated. The advantages of formal methods are that stimuli do not need to be provided, and once a decision is reached, the result is proven correct. The disadvantage is that proving properties on complex designs can often be computationally expensive in time and processing requirements or even impractical for large designs.

Applying formal technology with block level verification in ad hoc manner can result in potential undesirable and painful results, accordingly a structured application of formal technology should started with identifying a good candidates of the design blocks for formal verification. Formal technology is excellent with design blocks that are concurrency in na-ture or containing multiple data streams while they may not be that effective with sequential design blocks or design elements with a lot of data transformation. The second step should be describing the behavior of the candidate design block, its timing and its interfaces, in natural language from which the formal design properties and assumptions will be extracted. Finally the formal strategy should be picked up according to the main goal of applying formal technology which may be focus on finding proves for critical logic and design blocks, bug hunting for complex logic of the design, interface and connectivity check testing and finally coverage improvement and coverage closure.

Tutorial 5 SAT 101: Solving Challenging Optimization Problems using Advanced Boolean Satisfiability & ILP Techniques Morning Session 9:00-12:30 Fadi A. Aloul, Department of Computer Science & Engineering, American University in Sharjah, U.A.E.

Abstract Recent years have seen a tremendous growth in the number of research and development groups at universities, re-search labs, and companies that have started using Boolean Satisfiability (SAT) algorithms for solving different decision and optimization problems in Computer Science and Engineering. This has lead to the development of highly-efficient SAT solvers that have been successfully applied to solve a wide-range of problems in Electronic Design Automation (EDA), Artificial Intelligence (AI), Networking, Fault Tolerance, Security, and Scheduling. Examples of such problems include automatic test pattern generation for stuck-at faults (ATPG), formal verification of hardware and software, cir-cuit delay computation, FPGA routing, power leakage minimization, power estimation, circuit placement, graph coloring, wireless communications, wavelength assignment, university classroom scheduling, and failure diagnosis in wireless sensor networks.

SAT solvers have recently been extended to handle Pseudo-Boolean (PB) constraints which are linear inequalities with integer coefficients. This feature allowed SAT solvers to handle optimization problems, as opposed to only decision problems, and to be applied to a variety of new applications. Recent work has also showed that free open source SAT-based PB solvers can compete with the best generic Integer Linear Programming (ILP) commercial solvers such as CPLEX.

This tutorial is aimed at introducing the latest advances in SAT technology. Specifically, we describe the simple new input format of SAT solvers and the common SAT algorithms used to solve decision/optimization problems. In addition, we highlight the use of SAT algorithms in solving a variety of EDA decision and optimization problems and compare its per-formance to generic ILP solvers. This should guide researchers in solving their existing optimization problems using the new SAT technology. We discuss how to detect and break symmetries in SAT instances and the effect of that in signifi-cantly speeding up the search process. Finally, we provide a prospective on future work on SAT.

Tutorial 7 BIO-Inspired Chips for High Fidelity Classifications Afternoon Session 13:30-17:00 Hoda S. Abdel-Aty and John F. Dodge, Chair Professor of Engineering at Oakland University, Founder and Director of the Microelectronics & Bio-Inspired Systems Design Lab, and a Professor in the Department of Electrical and Computer Engineering at Oakland University, Rochester, MI, USA.

Abstract This tutorial is composed of three main parts that review sensor data collection, preprocessing, and developing and implementing high-fidelity classification algorithms.

First, background and motivations for using bio-inspired intelligent hardware and software systems will be discussed. They are required now more than ever, because of the fast paste progress in sensors, actuators, and more sophisticated applications.

The second part will cover modern alternative systems to develop efficient classifiers, based on sensory data, data pre-processing, algorithms, and mapping them into hardware to achieve portability, speed, and low cost. An exposition of Sampling Spiking Neural Network (SSNN) classifiers will be given as a promising technique.

In the third part the significance of preprocessing sensors data for classification is emphasized. A preprocessing ap-proach ought to take into account the nature of the application and the classification method. Those include: classical filters, evolutionary techniques, wavelet transform, fuzzy and hyper-fuzzy logic with their advantages and limitations explained. Furthermore, classification experiments of target tracking from radar signals, and of chemicals from mixtures with different concentrations, will be presented as good examples in achieving high fidelity classifiers.

Tutorial 8 Embedded Memory Design in Nanometer Technologies Afternoon Session 13:30-17:00 Baker Mohammad, Khalifa University of Science, Technology & Research (KUSTAR), UAE

Abstract With technology scaling, the requirements for higher density and lower power embedded memory are increasing expo-nentially. Nowadays, a large percentage of microprocessors and System-On-Chip SoC die areas are occupied by memo-ries, and this percentage is expected to increase substantially in the future. This increase is driven by the high demand for performance and low-power especially for mobile systems, which integrate a wide range of functionality such as digital cameras, 3-D graphics, MP3 players, email, communication protocols and other applications. However, technol-ogy scaling which enables packing > 100’s of millions of transistors on the same die also brings many new design chal-lenges due to the increase in leakage and variability combined with requirements for lower supply voltage operation. The SRAM-based memory using the traditional six transistors (6T cell SRAM) is still the dominant approach to build em-bedded memory, due to SRAM sensitivity to process variation its usage adds to the traditional challenges (power, area, yield, timing) that are also present for logic gates. In addition to these topics new emerging memory technologies (Mem-ristor, PCRAM, STT-RAM) will be described and the role they may play in future processors or SOC will be discussed.

Tutorial 9 BioMEMS Afternoon Session 13:30-17:00 Hisham Mohamed, Visiting Professor, Rensselaer Polytechnic Institute, Troy, NY, USA. Sr. Research Scientist, Egypt Nanotechnology Center, Smart Village, Egypt.

Abstract Recent progress in microfabrication technology, developed and used by the integrated circuits (ICs) industry, is being ap-plied to biomedical applications. It became a relatively new field of research known as BioMEMS. Microfabricated devices have been used in a broad range of biomedical and biological applications. In the last decade, microchips have been used in many biological applications such as in microscale sensors for surgical instruments, monitoring physiological activities, in microfluidics applications such as drug discovery and delivery, cell sorting, DNA amplification, and electrophoresis.

BioMEMS is a multi-disciplinary research field that requires the integration of knowledge and techniques from many disciplines such as engineering, biology, physics, and/or chemistry to develop a device with biological utility. Microfabri-cated devices are used to study and generate new insights into how biological systems work. On the other hand, re-searchers learn from biology to create new micro-nanoscale devices to better understand life processes at the nano-scale. BioMEMS is a challenging field due to the vastly diverse array of materials and chemical systems important to biological applications. Thus new fabrication processes must be developed for use with biologically relevant material systems while keeping the ability to effectively address dimensions at the molecular scale.

The first objective of this tutorial is to present an overview of the available technology, its strengths and current limita-tions, and current and potential applications with examples from the literature and the instructors’ laboratories. The second objective is to introduce engineers and life scientists to basic terminologies and concepts to facilitate the initia-tion of joint, multidisciplinary projects.