ICECS 2002 IEEE 9th International Conference on Electronics, Circuits and Systems Trends in Reconfigurable Logic and Reconfigurable Computing (invited

ICECS 2002IEEE 9th International Conference

on Electronics, Circuits and Systems

Trends in Reconfigurable Logic and Reconfigurable Computing

(invited paper)

Reiner Hartenstein

University ofKaiserslautern

viewgraph downloading, see:

http://kressarray.de

Dubrovnik, Croatia September 15-18, 2002

© 2002, [email protected] http://KressArray.de2

University of Kaiserslautern

Xputer Lab>> Outline

•The Computer Architecture Crisis

•The Impact of Reconfigurable Platforms

•The Dichotomy of Models

•Parallelism

•Conclusions

http://www.uni-kl.de



Xputer Lab

Flag ship example: annual IEEE ISCA conference series

Resignation?

taken over by the opposition:

Interconnect Fabrics:

vN Parallelism:

the Datenflow Machine is dead

98.5 % vN

Statistics [David Padua, John Hennessy, et al.]

Reconfigurable Computing



Xputer Lab

Dead Supercomputer Society

•ACRI •Alliant •American Supercomputer

•Ametek •Applied Dynamics •Astronautics •BBN •CDC•Convex•Cray Computer •Cray Research •Culler-Harris •Culler Scientific •Cydrome •Dana/Ardent/ Stellar/Stardent

•DAPP •Denelcor •Elexsi •ETA Systems •Evans and Sutherland•Computer•Floating Point Systems •Galaxy YH-1 •Goodyear Aerospace MPP •Gould NPL •Guiltech •ICL •Intel Scientific Computers •International Parallel Machines

•Kendall Square Research •Key Computer Laboratories

[Gordon Bell, keynote at ISCA 2000].

•MasPar•Meiko •Multiflow •Myrias •Numerix •Prisma •Tera •Thinking Machines •Saxpy •Scientific Computer•Systems (SCS) •Soviet Supercomputers •Supertek •Supercomputer Systems •Suprenum •Vitesse Electronics



Xputer LabCS: young ? dynamic?

.. but the von Neumann Paradigm is still the dominant doctrine ...

Microelectronics is ignored (except falling cost of computational effort)

... still pushing he basic models from the times of mainframe dinosaurs

after >10 technology generations ...

• 1th 4004• 2nd 8008• 3rd 8086• 4th 80286• 5th 80386• 6th 80486• 7th P5 (Pentium)• 8th P6 (Pentium Pro / Pentium II)• 9th Pentium III• 10th ....• 11th

• .......

... the vN Microprocessor is a methusela, the steam engine of the silicon age.

It is time to

go silicon-

oriented

It is time to

go silicon-

oriented

computing sciences

are ultra conservative …

… to avoid saying: senileA Re-

orientation is

over-due

A Re-

orientation is

over-due



Xputer Lab>> Paradigm Shifts

•The Computer Architecture Crisis

•The Impact of Reconfigurable Platforms

•The Dichotomy of Models

•Parallelism

•Conclusions

http://www.uni-kl.de



Xputer Labbetter to go for reconfigurable

platforms

•[Dataquest] PLD market > $7 billion by 2003.

•fastest growing segment of semiconductor market

•IP reuse and silicon reuse

•FPGAs are going into every type of application



Xputer Lab

Why coarse grain ?



Xputer LabThroughput vs. Efficiency

1000

100

10

1

0.1

0.01

0.0012 1 0.5 0.25 0.13 0.1 0,07

MOPS / mW

µ feature size

FPGAs (reconfigurable logic)hardwired

instruction set processors

standard microprocessor

DSP

S S

S S

resources needed for

reconfigurability

L

L L

LL

L

L LL

area used by application

1 Bit CLB

T. Claasen et al.: ISSCC 1999

Wiring by abutment:32 Bit example

*) R. Hartenstein: ISIS 1997

rDPAs (reconfigurable computing)*



Xputer LabThroughput vs. Flexibility

flexibility

throughput1000

100

10

1

0.1

0.01

0.0012 1 0.5 0.25 0.13 0.1 0,07

MOPS / mW

µ feature size

T. Claasen et al.: ISSCC 1999

hard-wired

hardwired

vonNeumann

instruction set processors

standard microprocessor

DSP FPGAs

Reconfigurable logic

the anti machine goes far beyond bridging the gap

antimachine

*) R. Hartenstein: ISIS 1997

rDPAs (reconfigurable computing)*



Xputer LabTerminology

DPU data path unitrDPU reconfigurable DPUDPA data path array (DPU array)rDPA reconfigurable DPARA reconfigurable arrayISP instruction set processorAM anti machineAMP data stream processor*rAMP reconfigurable AMP

*) no “dataflow machine”

platform category

programming source

machine paradigm

hardware (not programmable) noneISP software von Neumann• morphwar

econfigware FPGA: none

data stream processor (AMP)

streamware

anti machinereconfigurable AMP (rAMP)

streamware & configware

digital system platforms:

morphware use granularity (path width) (re)configurable blocksreconfigurable logic • fine grain (~1 bit) CLBs

reconfigurable computingcoarse grain (e.g. 32 bits) rDPUs (e.g. ALU-like)multi granular: by slice bundling rDPU slices (e.g. 4 bits)

categories of morphware:

consensus is near

FPGA field-programmable gate arrayFPL field-programmable logicPLD programmable logic deviceCPLD complex PLD

instruction set processor



Xputer LabParadigm Shifts:

Nick Tredennick‘s view

algorithms variable

resources fixed

instruction-stream-based computing:

algorithms variable

resources variable

reconfigurable computing:

programmable



Xputer LabCompilation for (r)DPA of anti

machine

mapper

scheduler

expressionmorphware

configware

streamware

tree

high level source program

wrapperparameters

codegenerators

DPU library

(software notation)

DataPath

Array

DPA

streamware

streamware



Xputer LabWhy fine grain ?

•no specific silicon: low production volume (aerospace, automotive, military, industrial controllers, et al.)

•the spare part problem

•design flow

© 2002, [email protected] http://KressArray.de


Xputer Lab

15

Evolution of FPGA and its design flow

UserCode Compiler Executable

Netlister NetlistPlaceand

Route..

Bitstream

Schematics/HDL

HLL Compiler

CompilerHLL

[à la S. Guccione]

CPUcore

FPGA core

MemorycoreCompilerHLL

softCPU


interfaces

CPUcore

FPGAcore

Memorycore

rDPAcore

interfaces

softrDPA

as soon as Giga FPGA is available



Xputer LabSome soft CPU core examples

Spartan-II16 bit DSPDSPuva16

FLEX10K30 or EPF6016

i8080AMy80

32-bit gr1050

16-bitgr1040

Altera – Mercury

8 bitNios

Altera 22 D-MIPS

32-bit instr. set

Nios 50 MHz

Altera Mercury

16-bit instr. set

Nios

Xilinx up to 100 on one FPGA

32 bit standard RISC32 reg. by 32 LUT RAM-based reg.

MicroBlaze 125 MHz 70 D-MIPS

platformarchitecturecore

SpartanXLRISC integer Cxr16

old Xilinx FPGA Board

16-bit RISC, 2 opd. Instr.

YARD-1A

1 Flex 10K20Acorn-1

Altera, Lattice, Xilinx

8 bit CISC1Popcorn-1

Lattice 4 isp30256, 4 isp1016

12 bit DSPReliance-1

2 XILINX 3020 LCA

8 bits Instr. + ext. ROM

REGIS

200 XC4000E CLBs

CISC, 32 reg.uP1232 8-bit

ARMARM7 clone

SPARCLeon25 Mhz

platformarchitecturecore



Xputer Lab soft CPUs in academic teaching

• UCSC: 1990! • Märaldalen

University • Chalmers University • Cornell University• Gray Research• Georgia Tech • Hiroshima City Univ.

• Michigan State • Univ. de Valladolid• Virginia Tech• Washington U. St. Louis • New Mexico Tech• UC Riverside • Tokai University



Xputer LabASIC emulation

•ASIC emulation / Rapid Prototyping: to replace simulation

•Quickturn (Cadence), IKOS (Synopsys), Celaro (Mentor)

•hours of compilation run: inefficient since netlist-based: ...

•... ASIC emulators will become obsolete soon

•by RTR: in-circuit execution debugging instead of emulation

•new business model: upgradable morphware is the product

•emulation for solving the spare part problem in many areas



Xputer LabThe microelectronics spare part

problem

•Original fab line is no more existing

•ICs do not survive storage time

•Demand: several decades of availability

IC physical life

expectance /years

2 1 0.5 0.25 0.13 0.1 0,07µ feature size

[Hartenstein 2002]

•e. g. car price: ~25% electronics

demand

/years of

availability

IC m

arke

t vo

lum

e



Xputer LabThe microelectronics spare part

problem

IC physical life

expectance /years

2 1 0.5 0.25 0.13 0.1 0,07µ feature size

[Hartenstein 2002]

demand

/years of

availability

IC m

arke

t vo

lum

e

key problem in many application areas: medical, aerospace, automotive, other transportation, military, industrial equipment controllers, et al.



Xputer Lab>> The Dichotomy of Models

• The Computer Architecture Crisis

• The Impact of Reconfigurable

Platforms

• The Dichotomy of Models

• Parallelism

• Conclusionshttp://www.uni-kl.de



Xputer LabMatter & Antimatter

The World of Mattermachine paradigm: the Atom

++Electron spinning-

The World of Anti Mattermachine paradigm: Anti Atom

--Positron spinning

+



Xputer LabMatter & Antimatter of Informatics :

instruction stream

spinning(von Neumann)

data stream spinning-DPU

+

Anti Machine paradigm

+

CPU

-

nothing central !



Xputer Labcomputing paradigms and methodologies: instruction-stream-based vs. data-stream-

based1946: machine paradigm (von Neumann)1980: data streams (Kung, Leiserson)1989: anti machine paradigm introduced1990: anti machine implementation methodology1990: rDPU (Rabaey)1994: anti machine high level programming language 1995: super systolic rDPA (Kress)1996+: SCCC (LANL), SCORE, ASPRC, Bee (UCB), ...1997: configware / software partitioning compiler

(Becker) 2000: generator for rDPA with high memory bandwidth

(tutorials and courses available on all this)



Xputer LabNasty Matter

+CPU

DataPath

instructionsequencer

RAM

Address Computation Overhead

Instruction Fetch Overhead

central von

Neumannbottleneck

extremely power hungry and area inefficient

performance problems

reconfigurable?

the wrong machine paradigm



Xputer Lab

-DPU

DataPathUnit

DPUDataPath


Matter vs. Antimatter: CPU vs. DPU

+

data

str

eam

data

str

eam

s+

+

+

+

DataPathUnit

DPU



Xputer Labheavy anti atoms: DPA = DPU

array

-DPA-

DPU

-DPU

-DPU

-DPU

-DPU

-DPU

-DPU

-DPU

-DPU-

DPA

+

+

+

+

+

+

++

+

str

eam

ware

: data

str

eam

ssp

innin

g a

round



Xputer Lab

+CPU

DataPath


+ simple machine paradigm+ scalability

+ relocatability+ compatibility

= secret of success of software industry

RAM

RAM-based

CPU:



Xputer LabSuccess Factors

propertyinstruction

stream based

data stream based

reconfigurable

hardwiredfine grain (FPGA)

coarse grain

RAM-based yes yes yes (hardwired)

machine paradigm yes no available available

compatibility yes limited feasible feasible

scalability yes no good* (hardwired)

code relocatability

yes no good* (hardwired)*) if KressArray

used**) mapping coarse grain

onto FPGA

good**

good**

feasible**

available**

success of software industry

•for configware industry is missing:– FPGA compatibility, – fully scalable FPGA, – relocatable configuration code • rDPUs and rDPAs do much

better than FPGAs



Xputer Lab>>> Problems with

Concurrency


• The Impact of Reconfigurable Platforms


• Parallelism




Xputer LabParallelism by Concurrency

independent instruction streams

....

Bus(es) or switch box

DataPath


DataPath


DataPath


DataPath


+-

+-

-+

+

+-

+

-+

-

-

difficult coordination

massive run time overhead



Xputer LabData-stream-based Parallelism

See my other talkICECS 2002

IEEE 9th International Conferenceon Electronics, Circuits and Systems

Memory Organisation for Datastream-based Reconfigurable Computing

(invited paper)

Michael Herz, Agilent Technologies

Reiner Hartenstein,University ofKaiserslautern

Miguel Miranda, Erik Brockmeyer, Francky Catthoor, IMEC, Leuven

Dubrovnik, Croatia September 15-18, 2002



Xputer Lab>> The Dominance of Embedded

Systems


• The Impact of Reconfigurable

Platforms


• Parallelism




Xputer LabSummary of the Anti Machine

Paradigm

• anti language primitives are almost the same (slightly extended)

• anti machine execution potential is dramatically more powerful

• provides drastically more flexibility

• not always replacing von Neumann



Xputer LabConclusions

•the anti machine is the way to go for massive parallelism, also data-intensive applications

•reconfigurable anti machine for high performance with short product life cycles, unstable standards

•reconfigurable for low cost low volume production

•Giga FPGAs highly promising - only by a new design flow: configware could repeat the success of software industry

•sparepart problem: needs new infrastructures



Xputer Lab



Xputer Lab>>> thank you

thank you for your patience



Xputer Lab



Xputer Lab>>> END

END



Xputer Lab



Xputer Lab>>> Appendix

Appendixfor discussion



Xputer Lab>> Problems to be solved

• Configware Market

• FPGA Market

• Embedded Systems (Co-Design)

• Hardwired IP Cores on Board

• Run-Time Reconfiguration (RTR)

• Rapid Prototyping & ASIC Emulation

• Evolvable Hardware (EH)

• Academic Expertise

• ASICs dead

• Soft CPU

• HLLs

• Problems to be solved



Xputer LabEDA industry shift into CS mentality

[Wojciech Maly]

•patches instead of engineering•innovation stalled many years ago•85% users hate their tools•netlist-based: do not care about efficiency, ...•... do not care about transistor density



Xputer Lab[Jonathan Rose] FPGAs Give You

• Instant Fabrication– Get to Market Fast– Fix ‘em quick

• Zero NRE Charges– Low Risk– Low Cost at good volume



Xputer LabMachine Paradigms

machine category Computer (the Machine:

“v. Neumann”) The Anti Machine

driven by: Instruction streams data streams (no “dataflow”)

engine principles instruction sequencing sequencing data streams

state register single program counter (multiple) data counter(s)

Communication path set-up .

at run time at load time

resource DPU (e.g. single ALU) DPU or DPA (DPU array) etc. data path

operation sequential parallel pipe network etc.

( “instruction fetch” )

also hardwired implementations**) e g. Bee project Prof. Broderson



Xputer LabThe Crisis of Computing Sciences

• Computing Sciences are in a severe crisis

• Computing curricula are obsolete because of strictly enforced „procedural-only“ blinders

• Computer Architecture and related areas have lost leadership in digital system implementation

• CS ignores > 90% µprocessors in embedded systems: 10 times more programmers will write embedded applications than computer software by 2010

• A disruptive promising therapy introduced by new approaches coming with Reconfigurable Computing



Xputer LabProgramming Language

Paradigms

language category Computer Languages Languages f. Anti Machine

both deterministic procedural sequencing: traceable, checkpointable

operation sequence driven by:

read next instruction, goto (instr. addr.),

jump (to instr. addr.), instr. loop, loop nesting

no parallel loops, escapes, instruction stream branching

read next data item, goto (data addr.),

jump (to data addr.), data loop, loop nesting, parallel loops, escapes, data stream branching

state register program counter data counter(s) address computation

massive memory cycle overhead overhead avoided

Instruction fetch memory cycle overhead overhead avoided parallel memory bank access interleaving only no restrictions

very easy to learn

multipleGAGs



Xputer LabConclusion: all knowledge needed is

available

• languages

• machine paradigm

• compilation techniques

• anti architectural resources

• sequencing methodology: hw & sw

• hw / sw partitioning methodology

• parallel memory IP core and module generator vendors

courses / embedded tutorials:• DATE. Munich, 2001

• ASP-DAC, Yokohama, 2001• SBCCI, Brasilia, 2001

full day:

Univ. Montpellier 1998Nokia / Univ. Tampere, Finland, 2002

CNRS Paris France, 2002

• keynotes 2001 / 2002• invited talks 2001 / 2002

• anything else needed



Xputer LabUbiquitous embedded systems

20 billion µprocessors (2001)

> 90% in embedded systems

10 times more programmers will write embedded applications than computer software by 2010

That’s where our graduates will go

Embedded systems means:

• hardware / software co-design

• configware / software co-design

• hardware / configware / software co-design



Xputer LabThe Situation in Computing

Sciences

• Computing Sciences are in a severe crisis

• New fundamentals and R&D directions are inevitable

• my mission: getting you involved

• All knowledge needed is readily available ...

• ... even from Computing Sciences

• Silicon application and EDA provide useful concepts

• Reconfigurable Computing has the remedy



Xputer Labthe edu gap has dramatic consequences

•Key R&D scenes are drying out or dying

•because of a lack of qualified researchers

•the embedded system design crisis gets worse

•because of a lack of qualified designers

•many innovative products cannot be sold

•because of a lack of qualified customers

•the edu gap is widening dramatically

•because of a lack of qualified educators



Xputer LabSuper Pipe Networks

pipeline properties array applications

shape resources

mapping scheduling

(data stream formation)

systolic array

regular data dependencies

only

linear only

uniform only

linear projection or algebraic synthesis

super-systolic DPA

no restrictions simulated

annealing or P&R algorithm

(e.g. force-directed) scheduling algorithm

The key is mapping, rather than architecture

*) KressArray [ASP-DAC-1995]



Xputer Lab.... it‘s an alternative culture

....

•now the area is going mainstream: a rapidly widening audience of non-specialists gets interested ...

•severe communication gaps due to educational deficits

•not only to users: still many hardware and EDA experts ask: isn’t it just logic design on a strange platform ?

• it is time to clarify and popularize fundamental aspects and to explain, that it is a fundamentally different culture



Xputer Lab

© 2001, [email protected] http://www.fpl.uni-kl.de


Xputer LabJürgen Becker’s Co-DE-X Co-Compiler

Analyzer/ Profiler

HostSoftware

GNU Ccompiler

paradigmComputer machine

DPSSKressArrayConfigware

X-Ccompiler

Xputer machineparadigm

Partitioner

Loop

Transfor-

mationsX-C is C languageextended by MoPLX-C

Resource Parameters

supportingdifferentplatforms

supporting platform-based design



Xputer LabImpact of Makimoto’s

wave

TTL µproc.,memory

custom

standard

ASICs,accel’s

LSI,MSI

reconfigurable

1957

1967

1977

1987

1997

2007

Proceduralpersonalization via RAM-based

Machine Paradigm

Personalization(CAD) beforefabrication

structuralpersonalization:

RAM-basedbefore run time

Software Industry’sSecret of Success

Repeat Success Story bynew Machine Paradigm !

ConfigwareIndustry



Xputer Lab

© 2001, [email protected]


Xputer Lab

instructions

programcounter:

state register

CompilerRAM

Datapath

hardwired

Sequencer

Computer Computer tightly coupledby compact

instruction code

“von Neumann”

“von Neumann”does not supportsoft data pathsdoes not supportsoft data paths

Datapath

reconfigurable

Xputer Xputer

Scheduler

CompilerRAM

(multiple)sequencer

DatapathArray

“instructions”


Xputer Lab

loosely coupledby decision data bits only

Xputer:Xputer:The Soft Machine Paradigm

The Soft Machine Paradigm reconfigurablereconfigurable

also for hardwiredalso for hardwired

Computer:the wrong Machine Paradigm

“von Neumann”

data stream specthere are some differences

sdatacounter

(anti machine)



Xputer LabReconfigurable semiconductor market

Xilinx42%

Altera37%

Lattice15%

Actel6%

Top 4 PLD Manufacturers 2000total: $3.7 Bio

•[Dataquest] > $7 billion by

2003.

•PLD vendors’ and their alliances provide libraries of “soft IPs”

Configware Market

•fastest growing semiconductor market segment

coarse-grained:

rDPUs: configurable functional blocks

fine-grained:

cLBs, rLBs: configurable logic blocks

PACT AG, Munich, Germanyhttp://pactcorp.comQuicksilver, San Josehttp://quicksilver-tech.com



Xputer LabSemiconductor Revolutions

“Mainstream Silicon Applicationis switching every 10 Years”

TTL µproc.,memory

custom

standard

1957

1967

1977

1987

1997

2007

Makimoto’s Wave

ASICs,accel’s

LSI,MSI

“The Programmable System-on-a-Chipis the next wave“

reconfigurable

Published

in 1989

Tredennick’sParadigm Shifts

hardwired

algorithm: fixed

resources: fixed

procedural programming

algorithm: variable

resources: fixed

structural programming

algorithm: variable

resources: variable

vN machineparadigm

anti machine paradigmanti machineparadigm




wave

TTL µproc.,memory

custom

standard

ASICs,accel’s

LSI,MSI

reconfigurable

1957

1967

1977

1987

1997

2007

Proceduralpersonalization via RAM-based

Machine Paradigm

Software Industry’sSecret of Success




wave

TTL µproc.,memory

custom

standard

ASICs,accel’s

LSI,MSI

reconfigurable

1957

1967

1977

1987

1997

2007


RAM-basedbefore run time


ConfigwareIndustry

qualified people are not available



Xputer LabImpact of Data-stream-

based ...

TTL µproc.,memory

custom

standard

ASICs,accel’s

LSI,MSI

reconfigurable

1957

1967

1977

1987

1997

2007


hardwiredbefore fabrication


EmbeddedHardware/Configware

Industry

qualified people are not available



Xputer LabRapidly growing CS education gap

•Our computing curricula are obsolete

•introduction is strictly „procedural-only“

•vN-only use of terms like „computer organisation“, „ computer structures“, „ computer architecture

•graduates are not prepared to the real world– most applications for embedded systems (>90% by 2010)

•our graduates are unable to compete with EE graduates

•only a few % curricula need to be changed

•my mission: getting you involved



Xputer Lab Binding Time vs. Computing Domain

time domain(procedural)

Binding time: (Set-up ofCommunication Channels)

at run time microprocessorparallel computer

time & space(hybrid)

later fabrication step ASICs

space domain(structural)

before fabrication full customICs

at loading time

at compile time

ReconfigurableComputing

array processor

programming domain:

supersystolicarrayssystolic

arrays



Xputer Lab

Sources: Proc ISSCC, ICSPAT, DAC, DSPWorld

Why Coarse Grain instead of FPGA ?

physicallogical

supersystolic

FPGAlogical

1980 1990 2000 2010

FPGAphysical

100 000 000 000

10 000 000 000

1000 000 000

100 000 000

10 000 000

1000 000

100 000

10 000

1000

Tra

nsi

sto

rs /

chip

~ 10

~ 10 000

drastically smaller configuration memorya lot of more benefits

much faster loading

FPGArouted

memory

microprocessor

reduced reconfigurability overhead by up to ~ 1000



Xputer LabWhat are the differences ?

vN* computing:

•computing in time

•instruction fetch at run time

•procedural

programming

• instruction scheduling

Reconfigurable Computing:

•computing in space and time

•“instruction” fetch at compile time

•structural programming

•data scheduling

•i. e. Data-stream-based

•also hardwired implementations**

•“instruction” fetch before fabrication**) e g. Bee project Prof. Broderson*) vN stands for “von Neumann”



Xputer LabBasics of Binding Time

run time

loading time

compile time

time of “Instruction Fetch”

microprocessorparallel computer

ReconfigurableComputing

“Instruction” generalized: including complex expressions and other datapaths

strong impact on the machine paradigm !

Documents

ICECS 2002 IEEE 9th International Conference on Electronics, Circuits and Systems Trends in Reconfigurable Logic and Reconfigurable Computing (invited