On the Characterization of Limit Cycle Modes in Oversampled Data Converters

Sotir Ouzounov Electronic Systems & Silicon Integration

Philips Research Europe Eindhoven, The Netherlands sotir.ouzounov@philips.com

Abstract— This paper studies the appearance of periodic and quazi-periodic modes, denoted as limit cycles, in the operation of closed-loop oversampled data converters. It demonstrates that the properties of these limit cycles are largely determined by the parameterization of the system loop filter, the amplitudes and the frequencies of the applied input signals, and the applied sampling frequency. For the analysis, quantization in amplitude and quantization in time are seen as separate functions. The quantizer is represented with sampled describing functions and a quazi-linear time-variant model for the loop operation is introduced and illustrated with simulation examples.

I. INTRODUCTION The paper introduces a new approach in the analysis of

oversampled data converters with an accent on sigma-delta modulators (SDMs). The SDMs are treated as nonlinear, closed-loop, clock-synchronized systems. Such identification is inspired by previous work on asynchronous sigma-delta modulators (ASDMs) [1] and puts an accent on the existence of limit cycles (LCs) in the SDM operation [2]. The LCs are defined as periodic modes that exist or appear in the system for some combinations of the system parameters and/or the input signal. The modes that appear for zero input are denoted as idle LCs. Historically, in the context of SDM, the LC phenomena are perceived as performance degrading effects. Though some recent studies [4] undertake a deep look in the LC behavior of SDM, the phenomenon is mainly studied heuristically. Extensive simulations have been required to study e.g. the appearance of tones in the signal band or the deterioration of the noise shaping. Here, we demonstrate that these and many other effects originate from a specific LC behavior and can be treated with the theory that is developed. In Section II a limit cycle model (LCM) of the SDM operation is introduced. The potential idle LCs are identified and the mechanism through which the clock determines their behavior is illustrated. The quantizer and the sampling operation are represented with a sampled describing function (DF). The graphical evaluation of the SDM LC behavior is explained with an example and several parameters of the LCM are defined. In section III the input-driven time-variant SDM LC behavior is studied for DC and harmonic inputs.

II. LIMIT CYCLE MODEL OF SDM IN IDLE MODE A LCM of the SDM operation can be established with the

help of the system shown in Fig. 1.

Figure 1. Basic SDM block diagram.

In Fig. 1, the SDM loop is built with a continuous-time (CT) filter L(jω), a binary quantizer, a sampling switch and a zero-order hold (ZOH). An important aspect of the model is the separation of amplitude quantization from sampling. In this way, the sampling operation can be superimposed to the asynchronous oscillatory mechanism that is characteristic for non-linear closed-loop systems [1]. In addition this allows the representation of the quantizer, the sampling switch and the ZOH by sampled DFs. With this background, a quazi-linear model of the SDM is constructed in the following steps.

A. Clock introduced phase shift From the ASDMs we know that the appearance of a limit

cycle is determined by the phase/magnitude relation in the closed loop. To apply the same reasoning here, firstly, we need to establish and model the impact of sampling on the phase/magnitude relation in the SDM loop. Using notations from Fig. 1, the impact of sampling on the loop behavior is illustrated conceptually in Fig. 2. In Fig. 2, time waveforms of the quantizer input and output signals: i(t) and y(t), and of the ZOH output: y*[nTs], are shown. The quantizer changes state at the zero crossings of i(t). The sampling switch propagates this state to the output at the sampling moments thus after some time delay and holds it till the next clock period. From Fig. 2, it can be concluded that the sampling switch and the ZOH introduce in the SDM loop a phase shift φs that can take any value between zero and a clock period. In idle mode the SDM is in steady state, the φs is fixed and depends on the total phase rotation in the closed-loop.

( )L jω ZOH-

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( )L jω ZOH-

( )r tsf

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Figure 2. Introduction of phase shift φs in the SDM loop by the sampling.

For busy operation, φs depends on the frequency and the amplitude of i(t) at the particular sampling instance. As this amplitude is continuously varying, φs is not fixed. That is why for busy operation the term phase uncertainty is used for the clock added phase shifts. The subject is treated further in Section III for input driven operation.

B. Potential idle sub-harmonic modes For the construction of the LCM of SDM, firstly, the

properties of the output bitstream in idle operation (zero input) are considered. For zero input, the average value of the output should also be zero. Thus, for idle mode, and fully structurally symmetrical loop, the output digital bitstream consists of N ones followed by N zeros [5]. This requirement presupposes that the only idle oscillations that can exist in the SDM loop have periods that are even integer multiples 2N of the sampling period Ts (N = 1, 2, 3...). Note that in practical systems the condition for N ones followed by N zeros is rarely observed as it requires ideal loop symmetry. Even small DC offsets in the implementation can disturb this ideal periodicity and have to be treated as input signals. For clear notations, the potential idle modes are denoted as first (with LC frequency fs/2), second (fs/4), third (fs/6) and so on, sub-harmonic LC modes. This definition shows the coupling of the idle LCs to the applied clock frequency, and the deceasing speed of the signals in the loop for low frequency LCs.

Figure 3. Evaluation of the φs for different sub-harmonic idle LC modes, i(t) is quantizer input and y*[nTs] is the SDM output.

From Fig. 3, it can be seen that φs depends on the frequency of the particular idle LC, such that for an idle LC with frequency fs/2, the clock can introduce in the SDM loop a maximum phase delay of 180deg. This comes from the fact that for the first sub-harmonic LC the sampling period corresponds to half the period of the LC. As the frequency of the LC scales down, the maximum φs that can be introduced also scales down with the same even integer factor because of the relative decrease of the clock added phase for the lower sub-harmonic LCs. From Fig. 3, for sub-harmonic LCs with

frequencies fs/4 and fs/6, the maximum φs that can be introduced is 90deg. and 60deg., respectively.

C. Sampled Describing Function A SDM loop filter with low-pass characteristics allows the

representation of the quantizer input signal i(t) in idle operation by a sinusoid with frequency equal to the active LC frequency. In this case the quantizer can be represented with its DF in the form N(A), where A is the amplitude of the quantizers’ sinusoidal input signal. The separation of the quantization in amplitude from the quantization in time allows the introduction of a modified DF that can be denoted as a sampled describing function [6], N(A, φs) with magnitude given by N(A) and phase component e-φs that accounts for the clock introduced phase shift. The block diagram that is used for the construction of the LCM is summarized in Fig. 4, where the quantizer, the sampling switch and the ZOH are represented by a sampled DF.

Figure 4. Block diagram of the LCM representation of SDM, The binary quantizer, the sampling swtich the ZOH are represented with a sampled DF.

D. Graphical evaluation of idle LC modes in SDMs As defined, an idle LC is a stable periodic mode that

appears in the SDM loop for zero input. For an SDM that can sustain i limit cycles, in analogy to the linear case, the prediction of oscillation is given by the Barkhausen criterion. The relation between the linear part of the loop and the DF representation of the non-linear element is given by:

( ) ( ), , ,1 ,LC i LC i s iL j N Aω ϕ= − (1)

where ALC,i and ωLC,i are the ith sub-harmonic LC amplitude and frequency and φs,i is the clock added loop phase shift for LCi. This equation states that the SDM can sustain LC oscillations for frequencies for which the total phase rotation in the loop is an integer multiple of 360deg. and the loop gain is one. The solutions of (1) give the frequency and the amplitude of the possible idle LCs and reveal the phase/magnitude relation in the loop at each sampling instance. For example, let us implement the system of Fig. 1 with a binary quantizer and a 2nd order loop filter defined as L(jω)= G(jω+ωz)/(jω+ωp)2, where G is a frequency independent gain and ωz and ωp are the frequencies of the loop filter zero and double pole. The identification of the existing idle LCs with (1) can easily be performed graphically as illustrated in Fig. 5. The φs,i for each potential LC with frequency fs/2N is shown as a dashed line originating from the discrete frequency points of the locus L(jωs/2N) and with length equal to π/N that, corresponds to the maximum phase shift that the clock can add for a particular LC. The LC modes correspond to those even integer fractions of fs for which the sampling operation adds enough phase in the loop such that the lines starting from L(jωs/2N) can cross –1/N(A), as indicated with dots in Fig. 5.

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Figure 5. Graphical description of the LCM of the SDM operation.

The phase that the loop filter contributes at the particular LC frequency is also indicated in Fig. 5 as ςi. For the example in Fig. 5, two LC modes are possible with frequencies fs/2 and fs/4. LCs with lower frequencies are not possible as the total phase rotation in the loop does not provide 360deg. phase shift required for oscillation (1).

The 1st sub-harmonic LC mode with frequency fs/2 is the only mode traditionally considered. However, the LCM reveals the possible existence of at least a second sub-harmonic mode of operation with frequency fs/4. The second sub-harmonic mode exists if φs,2 for frequency of fs/4 is such that the -180deg. line is crossed (see Fig. 5). Such a condition is easily fulfilled even for a 1st order system built with an integrator. Several parameters of the LCM can be defined:

• The phase boundary ρi gives a measure for the amount of phase with which the maximum φs,i exceeds the -180deg. phase line on both sides of the LC points.

• The phase margin λi that is required for the prevention of ith sub-harmonic mode (see Fig. 5). The λi is the distance between the maximum phase delay that can be introduced and the -180deg. line.

From Fig. 5 several important implications for the SDM operation can be stated:

1) In practice, at least two LCs are introduced in every SDM. They define stable points of operation that, as explained in Section III, determine also the SDM input driven behavior.

2) Multiple low frequency LCs can be avoided if sufficient λi is introduced via proper filter parameterization.

As pointed out, both the 1st and the 2nd idle sub-harmonic limit cycles LC1 and LC2 are possible modes. However, in practice the SDM loop oscillates at only one. Intuitively, the LC2 with the lower frequency is active due to the fact that in steady state operation the loop gain is highest for the LC mode with lowest frequency [3].

III. INPUT-DRIVEN TIME-VARIANT LC BEHAVIOR The study so far showed that several oscillation modes can

be possible in the SDM loop. Next, the LC behavior for DC and harmonic inputs is treated. For a low pass SDM loop filter, a DC input signal x(t)=Vin results in a ramp in i(t) with an instantaneous value at each sampling moment n given as VQin,n that depends on the applied DC input and the properties

of the loop filter. The quantizer input signal is then described as the summation of a sinusoidal component due to the active limit cycle LCi and the instantaneous DC value VQin,n:

( ) ( )', , ,LC i LC i Qin ni t A sin t Vω= + (2)

Let us take as an example a 1st order SDM built with an ideal integrator and driven with a DC input, and assume that both LC1 and LC2 are possible modes of operation (similar to Fig. 5). In idle mode the loop oscillates at LC2 and the oscillations are characterized by a phase boundary ρ2, as defined in Fig. 5. In Fig. 6 the time waveforms of i(t), y(t) (`indicates a busy signal) and y*[nTs], are shown. Due to the presence of an ideal 1st order integrator as a loop filter, the quantizer input signal i(t) has a triangular waveform.

Figure 6. Comparison: idle i(t), y(t) and small (-20dBFS) DC signal i`(t), y`(t) waveforms for a 1st order SDM, 1GHz fs, where y*[nTs] is the output.

When a DC signal Vin is applied at the SDM input, a ramp appears in i`(t) due to the integration of Vin by the loop filter. In Fig. 6 the waveforms in the studied SDM loop are shown for a small DC input corresponding to -20dB full scale (FS). Several observations for the system behavior can be made:

1) For higher inputs the slope of the ramp increases. 2) The frequency and amplitude of the LC component

in i(t) are unaltered by the small DC input such that (2) holds. 3) The signal y`(t) is shifted in phase with respect to idle

mode signal y(t). The phase shift depends on the slope of the ramp and thus on the applied Vin. This phase shift is due to VQin,n and alters the total phase rotation in the loop and as a result alters the oscillation conditions that have to be reevaluated at each sampling moment.

4) For the observed time interval, the SDM output signal y*[nTs] remains the same for idle mode and for operation with a small DC input and the instantaneous input-added phase rotation is undetected at the output.

For a positive DC input and zero initial conditions (LC2 is active), the ramp causes an increase of the positive part of y`(t). If the LC waveform is approximated1 with a sinusoid, the zero crossings of y`(t) (see Fig. 6) with respect to y(t) occur when VQin,n-ALCisin(χi,n)=0. For each second sampling moment n this leads to the introduction in the loop of a signal dependent phase shift that is given by the expression:

1 The actual LC waveform in the 1st order SDM with an ideal integrator is

triangular, however, around the zero crossings where the impact of the input signal is seen, it can also be approximated with a sinusoid.

( )L jω( )1−

N A

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( )1, ,sini n Qin n LCiV Aχ −= (3)

where VQin,n is the DC value in i`(t) at sampling moment n. As LC2 has frequency fs/4, only half of the sampling moments lead to a transition in the output bitstream. For the other half a value that is established at the previous clock moment is propagated. As the value of VQin,n varies in time, the signal dependent phase shift χ2,n is different at each sampling moment. For the time interval observed in Fig. 6, the phase χ2,n increases with each consecutive sampling moment. However, when χ2,n exceeds the phase boundary ρ2, the phase condition for exactly 360deg. phase rotation in the loop is not fulfilled for the active LC, it becomes instable and the SDM loop enters another stable point of operation: LC1.

Figure 7. LC transitions in 1st order SDM, a) from LC2 to LC1 with +180deg. phase jump; b) from LC1 to LC2 and negative -90deg. phase jump.

As the frequency of LC1 is fs/2, the first sampling after the instable moment is changing the bitstream a clock period earlier. From Fig. 7a, this is accompanied by a phase jump of +180deg. and the SDM loop enters LC1. At the transition from LC2 to LC1, the DC in i`(t) becomes negative and close to the amplitude of LC1, VQin,n≈-ALC1.For LC1 the phase boundary ρ1 approaches 90deg. and the amplitude ALC,1 is twice smaller. Then the phase delay (3) is twice larger than the delay that is introduced by operation at LC2 with the same input signal. As ρ1 is larger than ρ2, a much longer phase accumulation is taking place before LC1 becomes instable. For LC1, the accumulated phase reaches the phase boundary such that χ1,n≈ρ1 when VQin,n≈|ALC1|. As illustrated in Fig. 7b, when χ1,n>ρ1, LC1 is rendered instable, the output y*[nTs] does not change state for an extra clock period and a phase jump of -90deg. is introduced in the loop. That makes LC2 operational and introduces a small negative DC component in i`(t). The following LC2 cycle starts from a different initial value and a slightly different bitstream is produced.

Fig.8a illustrates the impact of the input DC value on the LC behavior. For higher DC inputs, the rate of the transitions between LC1 and LC2 also increases. That is due to the faster cross over the phase boundary for each limit cycle, due to the faster accumulation of phase shift for larger input signals. It is clear that the transitions between the LCs are deterministic and from given initial conditions the output bitstream can be established. For large DC inputs, ρ2 for LC2 can be surpassed for a single clock period (last waveform in Fig. 8a).

The SDM LC behavior with sinusoidal inputs is governed by the same mechanisms as discussed for DC input:

1) It is determined by the possible LCs in idle mode.

2) The stability region for each LC is dependent on the phase boundary of the particular SDM parameterization.

Figure 8. Quantizer’s inputs in 1st order SDM a) idle, small and large DC input signals; b)1MHz and 5MHz input signals with -20dBFS amplitude.

3) Due to the AC properties of i`(t), the phase variation in the loop due to the input signal is sinusoidal, such that equal phase accumulation and subtraction occurs for one period of the input signal. For sufficiently high input amplitudes the SDM loop can jump between several limit cycles within one period of the input signal.

4) The transitions between the LCs are also dependent on the frequency of the input signal as it influences the instantaneous amplitude of the signal component.

Both for DC and AC inputs, fully periodic modes can appear in the SDM output only for a very specific set of input amplitudes and frequencies. For the majority of input signals the SDMs operation is quasi-periodic such that for every period of the input signal a different digital output is produced.

IV. CONCLUSIONS The paper, demonstrated that a LC mechanism is present

in every SDM and is governed by the phase chracteristics of the implementation and the clock-added phase. A LCM of SDM operation was introduced, its graphical application was studied and shown to serve as a easy analytical tool. The LCM creates a new and powerful theoretical base for the analysis of the operation of closed-loop oversampled data converters that can be used in the investigation of many aspects of their operation and design.

REFERENCES [1] S. Ouzounov, E. Roza, H. Hegt, G.v.d. Weide, A. van Roermund,

"Analysis and Design of High-Performance Asynchronous Sigma Delta Modulators with a Binary Quantizer”, IEEE JSSC, vol. 41, no. 3, March 2006 pp.:588 – 596.

[2] S. Ouzounov, H. Hegt, A. van Roermund, "Sigma-Delta Modulators Operating at a Limit Cycle", IEEE TCAS II, vol. 53, no. 5, May 2006 pp. 399 – 403.

[3] S. Ouzounov, H. Hegt, A. van Roermund,, “Multi-Limit-Cycle Model for Σ∆ Modulators., Part I: Theory,” IEEE TCAS I, unpublished.

[4] D. Reefman, J. Reiss, E. Janssen, M. Sandler, “Description of Limit Cycles in Sigma-Delta Modulators”, IEEE TCAS I, Vol. 52, June 2005, pp. 1211 – 1223.

[5] H.C. Torng, W.E.Meserve, “Determination of Periodic Modes in Relay Servomechanisms Employing Sampled Data”, IRE Trans. on Automatic Control, September 1961.

[6] A.Gelb, W.V.Velde, “Multiple-Input Describing Functions and Nonlinear system design”, McGraw-Hill, 1968.

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