300 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 2 ...daifa01/Top/PubPapers/2010/J... · 300 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 2, FEBRUARY 2010 An 11-Bit 8.6

300 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 2, FEBRUARY 2010

An 11-Bit 8.6 GHz Direct Digital Synthesizer MMICWith 10-Bit Segmented Sine-Weighted DAC

Xueyang Geng, Student Member, IEEE, Fa Foster Dai, Fellow, IEEE, J. David Irwin, Life Fellow, IEEE, andRichard C. Jaeger, Life Fellow, IEEE

Abstract—This paper presents a low power, ultrahigh-speedand high resolution SiGe DDS MMIC with 11-bit phase and 10-bitamplitude resolutions. Using more than twenty thousand tran-sistors, including an 11-bit pipeline accumulator, a 6-bit coarsesine-weighted DAC and eight 3-bit fine sine-weighted DACs, thecore area of the DDS is 3 2.5 mm�. The maximum clock fre-quency was measured at 8.6 GHz with a 4.2958 GHz output. TheDDS consumes 4.8 W of power using a single 3.3 V power supply.It achieves the best reported phase and amplitude resolutions,as well as a leading power efficiency figure-of-merit (FOM) of81.1 GHz 2�� /W in the mm-wave DDS design. The measuredspurious-free-dynamic-range (SFDR) is approximately 45 dBcwith a 4.2958 GHz Nyquist output, and 50 dBc with a 4.2 MHzoutput in the Nyquist band at the maximum clock frequency of 8.6GHz. Under a 7.2 GHz clock input, the worst-case Nyquist bandSFDR and narrow band SFDR are measured as 33 dBc and 42 dBcrespectively. The measured phase noise with an output frequencyof 1.57 GHz is 118.55 dBc/Hz at a 10 kHz frequency offset witha 7.2 GHz clock input generated from an Agilent E8257D analogsignal generator. All the measurements were taken with the chipsbonded in a CLCC-52 package.

Index Terms—Accumulator, digital-to-analog converter (DAC),direct digital synthesizer (DDS), sine-weighted DAC, ROM-lessDDS.

I. INTRODUCTION

U LTRAHIGH-SPEED heterojunction transistors (HBT)allow a direct digital synthesizer (DDS) to operate at

mm-wave frequency, which is a preferable solution to the syn-thesis of sine waveforms with fine frequency resolution, fastchannel switching and versatile modulation capability [1], [2].There are several mm-wave DDS designs reported with clock fre-quencies from 9 GHz to 32 GHz and digital-to-analog converter(DAC) resolution from 5 bits to a maximum of 8 bits [3]–[5].These DDSs have been implemented in indium phosphide (InP)(HBT) technology and only tested on-wafer [3]–[5]. The max-imum achieved spurious-free-dynamic-range (SFDR) in theseDDSdesigns is less than30dBc,which isnot sufficient for typicalradar and wireless applications. The low yield and high powerconsumption of InP HBTs limits the InP HBT-based DDS fromachieving higher resolution. We have developed several DDSs

Manuscript received May 07, 2009; revised September 14, 2009. Current ver-sion published February 05, 2010. This paper was approved by Associate EditorJafar Savoj. This work was supported in part by the U.S. Army Research Labo-ratory and the U.S. Army Space and Missile Defense Command (SMDC) underContract W911QX-05-C-0003

The authors are with the Department of Electrical and Computer Engi-neering, Auburn University, AL 36849-5201 USA (e-mail: [email protected];[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JSSC.2009.2037542

in silicon germanium (SiGe) BiCMOS technology with morerobust and higher yield devices than the InP counterpart [6], [7].However, our earlier versions of SiGe DDSs still suffer fromless than 30 dBc SFDR. A higher spectrum purity and higheramplitude resolution are required in modern radar and communi-cation systems. With a segmented sine-weighted DAC, the DDSpresented in this paper achieves 11-bit phase and 10-bit ampli-tude resolutions with a maximum clock frequency of 8.6 GHz[8]. The DDS consumes 4.8 W with a leading power efficiencyfigure-of-merit (FOM) of 81.1 GHz 2 /W and the bestreported Nyquist band worst-case SFDR of 33 dBc in mm-waveDDS designs. This paper is organized as follows. Section II intro-duces the DDS architecture with a brief discussion of the DDSspectrum purity. In Section III, the segmentation scheme forthe mm-wave sine-weighted DAC design is discussed, and thecircuit implementation for the ROM-less DDS MMIC design isdescribed in Section IV. In Section V, experimental results arepresented, and conclusions are given in Section VI.

II. DDS ARCHITECTURE AND SPECTRAL PURITY

A. Conventional DDS and ROM-Less DDS

Conventional DDS design normally consists of a phase accu-mulator, a ROM lookup table (LUT) and a linear DAC. The phaseaccumulator computes the correct phase angle for the output sinewave by accumulating the input frequency control word (FCW)on each clock cycle. If the size of the accumulator is N bits, asshown in Fig. 1, the maximum phase value will be

. To save power and reduce the complexity of the sinu-soidal LUT, the N-bit output of the accumulator may be truncatedto P bits before addressing the ROM. The ROM LUT performsa phase-to-amplitude conversion (PAC) of the output sinusoidalwave. Once the amplitude information is obtained, it may be fur-ther truncated to D bits that correspond to the number of input bitsof the DAC. The digital amplitude codes are then fed into a linearDAC that generates an analog replica of the synthesized wave-form. A low-pass filter (LPF) usually follows the DAC to removethe unwanted frequency components. The input clock frequencyand FCW determine the frequency step size of the DDS as

(1)

and the output frequency of the DDS is given by

(2)

where is the DDS clock frequency, FCW is the input fre-quency control word, and is the size of the phase accumu-lator. Based upon the Nyquist theorem, at least two samples per

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Fig. 1. Block diagram of the conventional ROM-based DDS.

Fig. 2. Block diagram of the ROM-less DDS.

clock cycle are required to reconstruct a sinusoidal wave withoutaliasing. Thus, the largest value of the FCW is . There-fore, the maximum output frequency of the DDS is limited toless than . However, the output frequency of the DDS isusually constrained to be less than in a practical imple-mentation of the deglitch LPF.

The ROM size of the conventional DDS increases expo-nentially with an increase of the number of phase bits used toaddress the LUT. In general, increasing the ROM size resultsin higher power consumption and larger area in ROM-basedDDS designs. Numerous attempts have been made to com-press or eliminate the ROM LUT in the phase-to-amplitudeconversion. Langlois has published a comprehensive review ofthe phase-to-amplitude conversion techniques [9], includingangular decomposition [10]–[12], angular rotation, sine ampli-tude LUT compression [13], polynomial approximation andphase-to-sine amplitude conversion (PSAC)-DAC combina-tions. All the phase-to-amplitude conversion methods withthe exception of PSAC-DAC involve either a large ROM ora complex architecture, yet operate at relatively low speed.To overcome the speed and power performance limits of theROM-based DDS with high resolution, a ROM-less DDS withsine-weighted DAC (identified as PSAC-DAC by Langlois) hasbeen developed in both low speed and mm-wave DDSs.

The conceptual block diagram of this ROM-less DDS em-ploying a sine-weighted DAC is shown in Fig. 2. The ROM-lessDDS replaces the ROM and linear DAC with a sine-weighted

DAC that serves as a PAC block as well as a DAC. It elimi-nates the sine LUT, which is the speed and area bottleneck forhigh-speed DDS implementations. But, it is a design challengeto achieve high resolution in the sine-weighted DAC due to therequired nonlinear segmentation process.

The proposed DDS adopts a ROM-less architecture, whichcombines both the sine/cosine mapping and digital-to-analogconversion together in a sine-weighted DAC [14]. The blockdiagram of the ROM-less DDS, with N-bit phase and (P-1)-bitamplitude resolution is shown in Fig. 3. The major part of theROM-less DDS is an N-bit pipeline phase accumulator anda current-steering sine-weighted DAC. Since the output fre-quency cannot exceed the Nyquist rate, the most-significant-bit(MSB) of the accumulator input is tied to zero. The N-bit FCW(including ) feeds the accumulator which controls theoutput frequency of the synthesized sine wave. The two MSBsof the accumulator output are used to determine the quadrant ofthe sine waveform. The remaining (P-2)-bits are use to controlthe segmented sine-weighted DAC in generating the amplitudefor a quarter phase sine wave. With the segmentationmethod described in the following sections, MSBs areused to control the coarse DAC, while the a-bit MSBs and c-bitLSBs are used to control the fine DACs.

B. DDS Spectral Purity

In order to achieve fine step size, a large phase accumulatoris desired. However, the phase accumulator output is normally



Fig. 3. Block diagram of the ROM-less DDS with segmented DACs. Specifically for this design, � � �� and � � � � �.

truncated to save die area and power. For instance, the outputof the phase accumulator is truncated into P bits . Thenumber of phase bits (P) is chosen based on the power and areabudgets, as well as the signal-to-noise ratio (SNR) requirementof the DDS.

In the process of discrete phase accumulation and phase wordtruncation, spurs and quantization noise are introduced at theDDS output spectrum that can be modeled as a linear additivenoise to the phase of the sinusoidal wave. Phase truncation erroris periodic. If the MSBs of an N-bit phase word are used toaddress the DAC or LUT, the resultant spurs are mixed withthe DDS output frequency generating spurs at multiples of thatfrequency [8], given by

(3)

where GCD(A, B) denotes the greatest-common-divisor (GCD)of A and B.

In addition to the spurious components, the DDS outputwaveform will suffer from amplitude distortion due to the finitenumber of quantization levels in the DAC. The envelope of theDDS output waveform is modulated by a sine wave with thefrequency of

(4)

Note that the envelope of the DDS output waveform is mod-ulated by a low-frequency signal except when the FCW is aninteger power of 2. For a Nyquist output, the frequency of theamplitude distortion, which looks like amplitude modulation(AM), is given by

(5)

In addition to the spurs that come from phase truncation, DACspurs represent another big source of error. SFDR is one of themost important specifications for the dynamic performance of aDAC, as well as a DDS. The sine-weighted DAC shares many

design challenges with the linear DAC. The most important fac-tors affecting linear and sine-weighted DACs are summarizedbelow [15]:

a. imperfect synchronization of the control signal at theswitches;

b. digital signal feed-through via the or of theswitch transistors;

c. voltage variation at the drain of the current source transis-tors;

d. finite output impedance of the current switches.The first three problems can be minimized by careful layout

to balance the delays of the signal and clock paths such that thesignals arriving at the switches are synchronized. However, itis not easy to distribute the high frequency clocks across longdistances. To ensure clock synchronization, a specific clock dis-tribution scheme, such as an H-tree or a grid topology, need tobe employed.

SFDR is also affected by the output impedance of the DAC[16]. For an N-bit DAC with a switching structure as shown inFig. 9, the SFDR can be estimated as

(6)

where is the output impedance at the drain, or collector, ofeach switch, and is the load resistance for the DAC output.In addition to other factors, must be maintained as high aspossible in order to obtain a high SFDR in the desired frequencybandwidth. A cascode current source is a simple and effectiveway to increase the output impedance, and is adopted in thisultrahigh-speed sine-weighted DAC design.

III. SINE-WEIGHTED DAC SEGMENTATION

The sine-weighted DAC combines the sine/cosine map-ping block with the digital-to-analog amplitude converter.For high speed DAC design, a current-steering architectureis an excellent candidate because of its fast switching speed.It is quite difficult to build a non-segmented DAC with morethan 10 bit resolution due to the exponential increase in areaand power consumption that results from increasing the DACresolution. The problem becomes even more pronounced for



sine-weighted DAC designs. In linear DAC design, high accu-racy can be achieved using segmentation. For instance, a 10-bitDAC can be segmented into a 5-bit coarse DAC and a 5-bit fineDAC, i.e., a segmentation, while a 12-bit DAC can besegmented into an 8-bit coarse DAC and a 4-bit fine DAC, i.e.,

segmentation [8]. Similarly, a sine weighted DAC canalso be segmented into coarse DAC and fine DACs [17]. Themajor difference between the linear DAC and sine-weightedDAC is that the linear DAC has an identical current source ora power of 2 weighted current sources for each bit, dependingupon the decoder scheme, while the sine-weighted DAC has avariety of weighted current sources.

A. Quantization and Segmentation of the Sine Wave

In general, only one quarter of the sine wave needs to be gen-erated because of the quadrant symmetry of the sinusoidal func-tion. For a P-bit phase word, the first two MSBs are used to de-termine the quadrant of the sine wave, and the remainingbits will be used to represent one quarter of the sine wave, asshown in Fig. 3. If we further segment the remainingphase bits in three parts with a, b and c bits ,there are phase words for one quarter of the sine wave.The phase word can thus be represented as

(7)

where and are the phase sequence numbers related to thesegmented parts a, b and c. Thus, if the amplitude of the sinewave is given by , where is number of amplitudebits, and for a specific phase word , the quarter sine wave canbe represented as

(8)

Since

(9)

we have

(10)

Thus, the sine wave can be approximated as

(11)

with

(12)

(13)

where is the sinusoidal value to be stored in a coarseDAC, and denotes the sinusoidal value to be storedin fine DACs, respectively. From the above decomposition, twosub-DACs can be designed to convert a complete sine wave toits analog waveform. The fine DAC data can be usedto interpolate the coarse DAC data . In order to quan-tize , the amplitude differences between the two adjacentcoarse phase words are derived as shown in (14). To simplifythe quantization of , the average of is used to repre-sent every value and is thus simplified to .Hence, the amplitude difference between the two adjacent finephase words for the fine DACs can be obtained as shown in (15).In (14) and (15), it should be pointed out that:

a) is the truncated phase resolution, ;b) denotes the rounding of number down to the

nearest integer toward zero;

(14)

(15)



c) is theaverage value of ; and

d) , where is replacedwith its averaged value.

With (14) and (15), the sine function can be rewritten as

(16)

where the first term denotes the data stored in the coarse DACcurrent sources and the second term denotes the data stored inthe fine DAC current sources.

This trigonometric decomposition is similar to the ROM com-pression in the ROM-based DDS. In the approaches by Sunder-land [10] and Nicholas [11],

(17)

The following two approximations

(18)

have been made, while in the approach adopted here, the ap-proximation is improved by using

(19)

where is the mean value of . The approximation error willbe analyzed in the next subsection.

B. Approximation Error Analysis

In the previous subsection, two approximations are used forthe coarse DAC and fine DACs respectively. The first is repre-sented in (10). The second is the use of the mean value of forthe computation of . Both the approximations lead toerrors in the computation of the sine wave’s amplitude. For thecoarse DAC the approximation error is

(20)

The maximum value of is

(21)

when and .For the fine DACs,

(22)

and the maximum value of is

(23)

when and .If the whole DAC requires a 9-bit amplitude resolution, ex-

cluding the MSB mirroring, then the coarse DAC should haveat least a 9-bit resolution and the fine DACs should have c-bitresolution. From (21) and (23),

(24)

From (24),

(25)

As long as and are in the range of (25), the approximationerrors are less than the quantization noise and can be ignored.

C. Optimizing the Segmentation

From the above discussion, the quantization noise is signifi-cantly affected by the segmentation. To optimize the segmenta-tion for better performance, one or more optimization parame-ters need to be considered. SFDR, power consumption and diearea are the most critical parameters in the mm-wave DDS de-sign. An optimized segmentation figure-of-merit (FOM), nor-malized by the non-segmented values, is defined as

(26)

where , SFDR, and represent the segmentationfigure-of-merit, spurious-free-dynamic-range, power consump-tion and occupied area, respectively. The subscript “ ” meanssegmented DAC and “ ” denotes non-segmented DAC. Un-like CMOS logic design, where the power consumption resultsmainly from dynamic power, the primary power consumedby the current-mode-logic (CML) circuits that are used in themm-wave DDS designs is the static bias current in the CMLcurrent sources. Moreover, we assume that both the DAC powerconsumption and area are proportional to the number of DACswitch cells. If we segment the switch cells to and , thenormalized number of switch cells is given by

(27)

which can be used to represent either the normalized power con-sumption or the normalized area . For a sine-weighted DAC with total 9 input bits, Table I shows the simulatedSFDR, normalized power consumption or area and the .The results in Table I demonstrate that with a larger or , a betterSFDR can be achieved, but power consumption and area will in-crease as well. Segmentation with yields the bestSFDR, yet it also leads to the highest power consumption andlargest area. This result is understandable since meansa non-segmented DAC. The segmentation withresults in a good power and area efficiency, and a relatively high



TABLE ISIMULATED SEGMENTATION FOM FOR DIFFERENT SEGMENATIONS WITH

11-BIT PHASE AND 10-BIT AMPLITUDE RESOLUTIONS

SFDR. Moreover, it achieves the best of 0.47. Note thatthe simulated SFDR in Table I includes only the effect of staticquantization errors of the sine-weighted DAC, whereas the prac-tical integrated circuit also suffers from other nonlinearities anddistortions discussed in Section II. As a result, the measuredSFDR will be worse than what is given in Table I.

IV. CIRCUIT IMPLEMENTATION OF THE

11-BIT ROM-LESS DDS

With a 3.3 V power supply and a SiGe HBT base-collectorvoltage of 0.85 V–0.9 V, all of the digital logic is implementedusing 3-level CML with differential output swings of 400 mV. Atradeoff has been made between the DDS operational speed andits power consumption. For an 11-bit packaged DDS MMIC,power consumption is the primary concern. To save power, eachtail current in a CML current source is set to 0.3 mA, which isclose to 40% of the peak current. In the contrast, traditionalCML circuits are biased at 70–80% of the peak current. Atraditional implementation of the CML circuits would end upwith a DDS with power consumption larger than 9.0 W.

A. 11-Bit Pipeline Accumulator

To achieve the maximum operating speed with a fixed FCW,a pipeline accumulator is used in this design. It uses the mosthardware, but achieves the fastest speed. The total delay of theaccumulator is one full adder (FA) propagation delay plus oneD flip-flop (DFF) propagation delay.

Fig. 4 illustrates the architecture of the 11-bit pipeline phaseaccumulator, which has a total of 11 pipelined rows. Each rowhas a total of 12 DFF delay stages placed at the input and outputof a 1-bit FA. Eleven DFF stages are needed for an 11-bitpipeline accumulator. One more DFF is used for each row toretime the signal for data synchronization. This scheme retimesthe signal to remove the timing mismatch due to the metal wiredelays from the accumulator output to its input. Obviously,the pipeline accumulator has a propagation delay of 12 clockcycles, including a latency period of 11 clock cycles plus oneretiming clock cycle. Note that an accumulator requires atleast one delay stage even without any pipelined stages. Sothe pipeline architecture shown in Fig. 4 allows the 11-bitaccumulator to operate at the speed of a 1-bit accumulatorconsisting of an FA and a DFF.

B. 10-Bit Segmented Sine-Weighted DAC

The block diagram of the 10-bit sine-weighted DAC is shownin Fig. 5. It has a 9-bit complementor and a current-steeringsine-weighted DAC, which includes a 6-bit coarse DAC andeight 3-bit fine DACs. The MSB of the DAC input is used toprovide the proper mirroring of the sine waveform about thephase point. The 2nd MSB is used by the complementor to in-vert the remaining 9 bits for the 2nd and 4th quadrants of thesine waveform. The outputs of the complementor are applied tothe segmented sine-weighted DAC to form a quarter of the sinewaveform. Because of the quadrant mirror, the total amplituderesolution of the sine-weighted DAC is 10-bits, while a 9-bitsegmented sine-weighted DAC is used to generate the ampli-tude for a quarter phase sine wave.

Based on the discussion in Section III, settingresults in a segmentation with the best segmentation FOM.

Therefore, the 9-bit sine-weighted DAC is divided into a 6-bitcoarse sine-weighted DAC and eight 3-bit fine sine-weightedDACs. The first 6 bits of the complementor output control thecoarse sine-weighted DAC, and the highest 3 bits also addressthe selection of the fine DACs. The lowest 3 bits of the com-plementor output determine the output value of each of the fineDACs.

With 11-bit phase and 10-bit amplitude resolutions, theweighted current sources of the coarse DAC and fine DACscan be calculated from (14) and (15). The numbers within thecoarse DAC and fine DACs in Fig. 5 represent the weights of thevarious current sources. To describe the DAC core architectureand its operation, an operator is defined between two 8 8square matrices.

(28)

To match the sine-weighted DAC description, the matrix in-dexes start from 0 instead of 1. As an example, for a specificphase word

(29)

the quarter sine wave is rebuilt using (16) and represented in(30), where and represent the operation state (0 meansopen and 1 means closed) of the respective coarse DAC and fineDAC switches. Comparing to (16) and (30), we have

(31)

(32)

and

(33)

From (31), the control bits of the coarse DAC switch matrix canbe generated through thermometer decoders. Fig. 6 shows thecoarse DAC decoders. represent the input bits to thecoarse DAC and represent the complemented bits at the



Fig. 4. The 11-bit pipeline phase accumulator.

complementor output. The full 6-bit thermometer decoder in-cludes three parts: a column decoder, a row decoder and secondlevel decoders. and are inputs to the column de-

coder and row decoder, respectively. Following the second levelthermometer decoder, 6-bit binary codes are converted to 64-bitthermometer codes represented by . As shown in Fig. 7,

(30)



Fig. 5. 10-bit segmented sine-weighted DAC.

Fig. 6. Coarse DAC thermometer decoder. Fig. 7. Fine DACs thermometer decoders.



Fig. 8. Illustration of interpolating the two adjacent outputs of a coarse DAC using the fine DAC current matrix.

Fig. 9. Current switch circuit of the sine-weighted DAC.

the control bits of the fine DAC’s switch matrix can be generatedthrough a thermometer decoder, a binary decoder and a secondlevel address-select decoder. and representthe input bits to the fine DACs. and representthe complemented bits at the complementor output. isinput through the thermometer decoder and converts the inputbits for each fine DAC, and is input through the binarydecoder to generate the address-select code. The binary decoderand the address-select decoder work together to select whichfine DAC is used to interpolate the respective coarse DAC steps.Through a combination of all the decoders, the 64-bit fine DACcontrol matrix is generated and represented by as describedin (32).

As shown in Fig. 8, the coarse DAC current source matrixprovides 512 unit current sources. Each fine DAC uses about 8unit current sources to interpolate the two adjacent outputs of thecoarse DAC. For example, for a phase value represented by

and , the coarse DAC current output is the sumof all the numbers filled in the gray-shaded boxes in the coarseDAC current matrix in Fig. 8. The fine DAC current output,which is the sum of all the numbers filled in the gray-shadedboxes in the fine DAC current matrix, is added to the coarseDAC output. As a result, the total current output of the DAC

is the sum of all the gray-shaded boxes and equal to 237 unitcurrent sources. The unit current of each current source is set at26 A. The largest current in the current source matrix of this10-bit sine-weighted DAC is 338 A, which is composed of 13unit current sources.

The current switch contains two differential pairs with cas-code current sources for improved output impedance and currentmirror accuracy. The current outputs are converted to differen-tial voltages by a pair of off-chip 15 pull-up resistors. Fig. 9shows that the currents from the cascode current sources are fedto outputs and by pairs of switches . TheMSB controls the selection between different half periods. Thecurrent switch contains two differential pairs with minimum sizetransistors and a cascode transistor to isolate the current sourcesfrom the switches, which also improves the bandwidth of theswitching circuits.

In order to achieve current source matching in the layout, eachcurrent source is split into four identical small current sourceswhich carry a quarter of the required current. To further improvethis matching, all the current source transistors, including thosein the coarse DAC and fine DACs, are distributed in the currentsource matrix with a pseudo-double-centroid switching scheme[18]. The coarse DAC and fine DACs use a total of 568 currentsources. Therefore, a 24 row by 24 column current source cellsare used to build the current matrix in Fig. 10. All the currentsources are distributed through a rotation from the matrix centerto the edge. The total number of current source cells used forthe coarse DAC are 511 and 57 are used for fine DACs. Theremaining 8 current sources are used for bias. Four 24 by 24current source matrices are placed around a common cenrtoid.Two dummy rows and columns are added around the currentsource matrix to avoid edge effects. So the complete currentmatrix has 52 rows and 52 columns.

C. Clock Distribution

To synchronize the signal in high speed circuit design, nu-merous DFFs are used between the logic elements. In the ac-



Fig. 10. Diagram of the current source matrix.

cumulator design, the number of the DFFs in the pipeline ac-cumulator increases rapidly with the increasing number of thepipeline stages. Hence, there are more than 100 DFFs used inthe 11-bit pipeline accumulator. Counting the number of theDFFs used in the sine-weighted DAC to synchronize the currentswitches, it yields approximately 300 DFFs. All of these DFFsmust be synchronized with a simultaneous clock edge. In orderto minimize the phase difference and maintain the same drivestrength between the clock and DFFs, an H-tree clock schemeis used to ensure that the clock signal reaches each block si-multaneously. Fig. 11 shows a simplified architecture of the“H”-shaped clock tree. The actual clock tree is 3 times biggerthan the simplified version shown in Fig. 11. The external clockis buffered by a differential pair and then drives two emitter fol-lower pairs which are used as a level-shifter as well as a buffer.Each emitter follower pair drives two or four differential pairsand each differential pair drives other emitter follower pairs,until the clock reaches the leaves that finally drive the DFFs.The number of differential pairs or emitter follower pairs drivenby the previous stage depends on the driving strength of the pre-vious stage and is proportional to the CML tail current. To keepenough swing fully switching the next stage, a 1-driving-2 cur-rent ratio is maintained throughout the whole clock buffer tree.

V. EXPERIMENTAL RESULTS

The die photo of the SiGe DDS MMIC is shown in Fig. 12.This DDS design is quite compact with an active area of3 2.5 mm and a total die area of 4 3.5 mm . The DDSwas tested in a 52-pin ceramic leadless chip carrier (CLCC-52)package. Fig. 13 shows the packaged chip soldered on a PCBfabricated with RO4004 material. The clock signal is generatedfrom an Agilent E8257D analog signal generator and is con-verted to differential signals by a hybrid coupler. Two SMA

Fig. 11. Simplified clock tree distribution.

Fig. 12. Die photo of the 11-bit ROM-less DDS MMIC.

connectors and symmetrical tracks are used to send the clocksignal to the DDS chip. The DDS current outputs are convertedto voltage outputs through a pair of 15 on-board resistors andconnected to the spectrum analyzer or oscilloscope throughSMA connectors and RF cables.



Fig. 13. Evaluation board for the 11-bit ROM-less DDS MMIC.

Fig. 14. Measured DDS output spectrum with a 4.2 MHz output and a max-imum 8.6 GHz clock �� , illustrating about 50 dBc SFDR. The toneat 91.7 MHz is from the nearby campus FM radio station.

The package has a thermal resistance of approximately30 C/W. With a 4.8 W power consumption at room ambienttemperature, the junction temperature of the SiGe devices cantheoretically reach as high as 180 C. At such high tempera-ture, the device performance is greatly degraded and the DACcurrent switches are no longer synchronized due to increasedinternal delays, which introduce noticeable distortion in theoutput waveform. When the device is effectively cooled, theDDS operates at a maximum clock frequency of 8.6 GHz. Atroom temperature, the packaged DDS operates at the maximumclock frequency of 7.2 GHz.

Figs. 14–17 illustrate the measured DDS output spectra andwaveforms for different outputs and clock frequencies. Allmeasurements were done with packaged parts and without cali-brating the losses of the cables and PCB tracks. Fig. 14 presentsa 4.2 MHz DDS output spectrum with an 8.6 GHz clock input,and a minimum FCW of 1. The measured output power isapproximately 8.3 dBm, and the measured SFDR is about50 dBc. The tone at 91.7 MHz was generated by the nearbycampus FM radio station. To show the signal tone clearly, a100 MHz band spectrum plot is used instead of the full Nyquist

Fig. 15. Measured DDS output waveform with a 4.2 MHz output and an8.6 GHz clock.

Fig. 16. Measured DDS Nyquist output spectrum with a 4.2958 GHz outputand a maximum 8.6 GHz clock �� , illustrating about 45 dBcSFDR. The image tone is located at 4.3042 GHz.

band. However, the worst-case spur is located within this band,so within both the Nyquist band and the narrow band the SFDRis 50 dBc. Fig. 15 shows the waveform for the spectrum inFig. 14.

Fig. 16 demonstrates the operation of the DDS at a maximumclock frequency of 8.6 GHz with Nyquist output (i.e.,

). Thus, the output frequency is set as

GHz (34)

The first order image tone due to mixing the clock frequencyand the DDS output frequency occurs at

GHz GHz GHz (35)

The measured SFDR of the device is approximately 45 dBc.The tone at 91.7 MHz once again appears in the spectrum.Fig. 17 illustrates the measured DDS output waveform with a4.2958 GHz Nyquist output and an 8.6 GHz clock. The signal



Fig. 17. Measured DDS output waveform with a 4.2958 GHz Nyquist outputand an 8.6 GHz clock. The 8.4 MHz envelope frequency results from mixingthe output and its image.

Fig. 18. The measured DDS SFDR versus FCW at clock frequency of 7.2 GHz.Illustrating a worst-case SFDR of 33 dBc for the Nyquist band (3.6 GHz) and42 dBc for the narrow band (100 MHz), respectively.

envelope frequency results from mixing the output and itsimage, which is

MHz (36)

Fig. 18 shows the measured DDS SFDR plot at both the Nyquistband (3.6 GHz) and the narrow band (100 MHz) versus the FCWwith a clock frequency of 7.2 GHz. The worst-case SFDR is33 dBc and 42 dBc for the Nyquist band and narrow band, re-spectively. Fig. 19 shows the measured DDS phase noise at anoutput frequency of 1.57 GHz with a 7.2 GHz clock input fre-quency. There is a 118.55 dBc/Hz phase noise at a 10 kHzfrequency offset. The input clock is generated from an AgilentE8257D analog signal generator. The spurs showing in the mea-surement are not harmonically related to the synthesized outputfrequency. It is test environment related.

Fig. 19. The measured DDS phase noise at an output frequency of 1.57 GHzwith a 7.2 GHz clock input frequency. The input clock is generated from an Ag-ilent E8257D analog signal generator. The graph illustrates a�118.55 dBc/Hzphase noise at a 10 kHz frequency offset.

To evaluate the performance of mm-wave DDSs, an easilymeasured and calculated FOM must be defined from a combina-tion of performance parameters. In the previous literature [19],a power efficiency FOM has been defined as

GHz(37)

This previously defined FOM includes the maximum updatefrequency as well as the power consumption, but does not con-sider the amplitude resolution information, which is limited bythe DAC. For a mm-wave DDS, this lack of information is unfor-tunate since the DAC is the most challenging part of a mm-waveDDS design. Thus, we define a new FOM including the effec-tive number of bits (ENOB) that measures the DAC spuriousperformance. From [20], the signal to noise and total harmonicdistortion (SINAD) are used to calculate the ENOB as follows:

(38)

SINAD is the ratio of the root-mean-square (RMS) value of thesine wave (reconstructed output of a DAC) to the RMS valueof the noise plus the total harmonic distortion (THD) up tothe Nyquist frequency, excluding the fundamental and the DCoffset. SINAD is typically expressed in dB as

(39)

where and are the RMS energy values of the signal andnoise; THD is the total harmonic distortion defined as in (40).

are the first and second harmonic distortionenergy. is the fundamental tone or signal tone energy.

(40)



TABLE IIMM-WAVE DDS MMIC PERFORMANCE COMPARISION

Although the second items in (40) may be larger than the firstitem, the SFDR is easily obtained since it can be read directlyfrom the spectrum analyzer. Herein, we use 1/SFDR to representthe THD. In general, the RMS value of the noise is far belowthe THD. As a result, the SFDR is used to represent SINAD tocalculate the FOM, which can be defined as

GHz

GHz(41)

represents the ENOB obtained from the SFDRmeasurement [21]. Although the SFDR is defined in the Nyquistband, the narrow band SFDR is often more important sincewideband spurs can be removed relatively easily. It is only aspecific narrow band near the output, which is usually less than1% of the update frequency, which is of the interest of manyapplications.

Table II is a comparison of mm-wave DDS MMIC perfor-mance. Compared to the InP DDS MMICs, this SiGe DDS sig-nificantly improves the resolution, and it is the most compli-cated mm-wave DDS design containing approximately twentythousand transistors. Most of the InP DDS MMICs were mea-sured using probe stations [3]–[5], while this DDS MMIC waspackaged. As mentioned earlier, the package has a thermal re-sistance of approximately 30 C/W, and at room ambient tem-perature, the junction temperature of the SiGe devices can the-oretically reach as high as 180 C. At such high temperature,the device performance is greatly degraded and the DAC cur-rent switches are no longer synchronized due to increased in-ternal delays. When the device is effectively cooled, the DDSoperates at a maximum clock frequency of 8.6 GHz. At roomtemperature, the packaged DDS operates at the maximum clockfrequency of 7.2 GHz. When compared with the 9-bit 12.3 GHzDDS [6], this design achieves two more bits for both phase andamplitude. As a result, this DDS achieves a 10 dB larger SFDR.

VI. CONCLUSION

This paper presented an 11-bit 8.6 GHz SiGe DDS MMICdesign with a 10-bit segmented sine-weighted DAC, imple-mented in 0.13 m SiGe BiCMOS technology withof 200/250 GHz. With Nyquist output, the DDS achieves amaximum clock frequency of 8.6 GHz. The Power consumptionof the DDS is approximately 4.8 W and the power efficiencyFOM is 81.1 GHz 2 /W. This DDS MMIC is the firstmm-wave DDS with 11-bit phase and 10-bit DAC amplituderesolutions that achieves a record high SFDR of 33 dBc withleading power efficiency.

ACKNOWLEDGMENT

The authors would like to acknowledge Eric Adler and Geof-frey Goldman at the U.S. Army Research Laboratory and PeteKirkland and Rodney Robertson at the U.S. Army Space andMissile Defense Command for funding this project.

REFERENCES

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Xueyang Geng (S’08) received the B.S. degree indepartment of Physics from the University of Scienceand Technology of China (USTC), Hefei, China, in2001, and the Master degree in Institute of Semi-conductors, Chinese Academy of Sciences, Beijing,China, in 2004. He is currently working toward thePh.D. degree in Department of Electrical and Com-puter Engineering at Auburn University, Alabama,USA. From 2004 to 2005, he was with STMicroelec-tronics Design Center, Shenzhen, China. His researchinterests include VLSI circuits for digital, analog,

mixed-signal and RF applications, ultrahigh-frequency direct digital frequencysynthesis (DDS) and digital to ananlog converter (DAC).

Fa Foster Dai (M’92-SM’00-F’09) received a Ph.D.degree in electrical and computer engineering fromAuburn University, AL, USA in 1997 and a Ph.D. de-gree in electrical engineering from The PennsylvaniaState University, PA, USA in 1998.

From 1997 to 2000, he was with Hughes NetworkSystems of Hughes Electronics, Germantown,Maryland, USA, where he was a Member of Tech-nical Staff in very large scale integration (VLSI),designing analog and digital ICs for wireless andsatellite communications. From 2000 to 2001, he

was with YAFO Networks, Hanover, Maryland, USA, where he was a TechnicalManager and a Principal Engineer in VLSI designs, leading high-speed SiGeIC designs for fiber communications. From 2001 to 2002, he was with CognioInc., Gaithersburg, Maryland, USA, designing radio frequency (RF) ICs forintegrated multi-band MIMO wireless transceivers. From 2002 to 2004, hewas an RFIC consultant for Cognio Inc. In August 2002, he joined AuburnUniversity in Auburn, Alabama, USA, where he is currently a Professor inelectrical and computer engineering. His research interests include VLSIcircuits for analog and mixed-signal applications, RFIC designs for wirelessand broadband networks, ultrahigh frequency synthesis and mixed signalbuilt-in self-test (BIST). He co-authored the book Integrated Circuit Designfor High-Speed Frequency Synthesis (Artech House Publishers, Feb, 2006).

Dr. Dai has served as Guest Editors for IEEE Transactions on Industrial Elec-tronics in 2001 and 2009. He served on the technical program committees ofthe IEEE Symposium on VLSI Circuits from 2005 to 2008. He currently serveson the technical program committees of the IEEE Custom Integrated CircuitsConference (CICC), and the IEEE Bipolar/BiCMOS Circuits and TechnologyMeeting (BCTM). He holds 5 U.S. patents and received the Research Award forExcellence from the College of Engineering of Auburn University in 2009.

J. David Irwin (S’60–M’63–SM’71–F’82–LF’05)was born in Minneapolis MN in 1939. He receivedhis BEE from Auburn University in 1961 and theM.S. and Ph.D. degrees from the University of Ten-nessee at Knoxville in 1962 and 1967, respectively.He joined Bell Telephone Laboratories as a Memberof the Technical Staff in 1967 and was made aSupervisor in 1968. He joined Auburn University in1969, and became head of the Electrical EngineeringDepartment in 1973, and served in that capacity for36 years. He is now the Earle C. Williams Eminent

Scholar in the Electrical and Computer Engineering Department.He has held numerous positions within the IEEE, including President of both

the Education and Industrial Electronics Societies, as well as Editor-in-Chief ofthe IEEE Transactions on Industrial Electronics. He is the author or coauthorof numerous publications, including seventeen textbooks. He is a Fellow of theAmerican Society for Engineering Education, the American Association for theAdvancement of Science, and a Life Fellow of the Institute of Electrical andElectronic Engineers. He is the recipient of numerous education and technicalawards.

Richard C. Jaeger (M’69–SM’78–F’86–LF’09)received the B.S. and M.E. degrees in electricalengineering in 1966 and the Ph.D. degree in 1969,all from the University of Florida, Gainesville. From1969 to 1979 he was with the IBM Corporationworking on precision analog design, integratedinjection logic, microprocessor architecture andlow temperature MOS device and circuit behavior.He holds three patents and received two InventionAchievement Awards from the IBM Corporation.In 1979 he joined Auburn University where he is

now Professor Emeritus of Electrical and Computer Engineering. He wasinstrumental in founding the Alabama Microelectronics Science and Tech-nology Center in 1984 and served as its Director until 1998. From October2001 through 2004, he was Interim Director of Auburn University’s WirelessEngineering Program and led implementation of Auburn’s now accreditedBachelor of Wireless Engineering degrees, a joint effort between the ECE andCSSE departments.

He has published over 300 technical papers and articles, served as principalinvestigator on more than $8 M in research contracts, and authored or co-au-thored six textbook editions including the Second Edition of Introduction toMicroelectronic Fabrication, Prentice Hall, 2002, the Third Edition of Micro-electronic Circuit Design, McGraw-Hill, 2007 with T. N. Blalock, and Com-puterized Circuit Analysis Using SPICE Programs, McGraw-Hill, 1997 with B.M. Wilamowski. He received the 1998 IEEE Education Society McGraw-Hill/Jacob Millman Award for “Development of a Modern and Innovative Design-Oriented Electronic Circuits Text,” and the 2004 IEEE Undergraduate TeachingAward for “Excellence In Undergraduate Teaching and Development of Out-standing Textbooks for Courses In Microelectronics.”

Dr. Jaeger was a member of the IEEE Solid-State Circuits Council from1984–1991, serving the last two years as Council President. From 1995–1998he was Editor of the IEEE Journal of Solid-State Circuits. He was elected to theIEEE Solid-State Circuits Society Adcom in 1999, and served as its Vice Pres-ident in 2004–2005 and President in 2006–2007. He was Program Chairmanfor the 1993 International Solid-State Circuits Conference, and Chairman of the1990 VLSI Circuits Symposium. From 1980 to 1982 he served as founding Ed-itor-in-Chief of IEEE MICRO, and subsequently received an Outstanding Con-tribution Award from the IEEE Computer Society for development of that mag-azine. He was selected as one of the IEEE Computer Society’s “Golden Core”and received the IEEE Third Millennium Medal.

Dr. Jaeger was elected Fellow of the IEEE in 1986 and was appointed tothe Distinguished University Professorship by Auburn University in 1990. Hereceived the Birdsong Merit Teaching Award from the College of Engineeringin 1991. In 1993, he was chosen as the Outstanding EE Faculty Member by theundergraduate students.


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300 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 2 ...daifa01/Top/PubPapers/2010/J... · 300 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 2, FEBRUARY 2010 An 11-Bit 8.6