IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 8 ...ims.unipv.it/FIRB2006/pub/Monaco10a.pdf · IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 8, AUGUST 2010 1565 Injection-Locked

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 8, AUGUST 2010 1565

Injection-Locked CMOS Frequency Doublers for�-Wave and mm-Wave Applications

Enrico Monaco, Student Member, IEEE, Massimo Pozzoni, Francesco Svelto, Member, IEEE, andAndrea Mazzanti, Member, IEEE

Abstract—On-chip frequency generators for high frequency ap-plications suffer from degradation of key passive components, vari-able capacitors in particular. In this framework, frequency multi-pliers can play a key role, allowing the design of voltage-controlledoscillators running at a frequency lower than required with advan-tage in terms of signal spectral purity and frequency tuning range.In this paper we present two injection locked frequency doublersfor Ku-band and F-band applications respectively. Despite differ-ences in implementation details, the same topology where a push-push pair injects a double frequency tone locking an autonomousdifferential oscillator is adopted. The circuits require limited inputsignal swing and provide a differential output over a broad fre-quency range. Dissipating 5.2 mW, the Ku-band multiplier, real-ized in a 0.13 m CMOS node, displays an operation bandwidthfrom 11 GHz to 15 GHz with a peak voltage swing on each outputof 470 mV. The F-band multiplier, realized in 65 nm CMOS tech-nology, displays an operation bandwidth from 106 GHz to 128 GHzwith a peak voltage swing on each output of 330 mV and a powerdissipation of 6 mW. A prototype including the multiplier, drivenby a half-frequency standard LC-tank VCO, demonstrates an out-standing 13.1% tuning range around 115 GHz.

Index Terms—Frequency doubler, frequency multiplier, injec-tion locking, microwaves, millimeter waves, mmw, push-push.

I. INTRODUCTION

A PPLICATIONS at micro-waves, millimeter-waves andeven in the THz gap are flourishing due to the ever

increasing speed of CMOS devices in ultra-scaled nodes. In the10 GHz to 30 GHz frequency range, envisioned applicationsinclude broadcast satellite receivers, wireless connectivity,UWB imaging systems and anticollision radar sensors [1]–[3].At mm-waves, 7 GHz unlicensed frequency band around 60GHz have been allocated for gigabit/sec wireless connectivityand several CMOS transceiver realizations have already beenpresented [4]–[6]. Next generation automotive radars willoperate at 77 GHz [7], [8]. In the THz gap, imaging and spec-troscopy systems for scientific, medical, space, and industrial

Manuscript received November 16, 2009; revised January 29, 2010; acceptedMarch 11, 2010. Current version published July 23, 2010. This paper wasapproved by Guest Editor Ramesh Harjani. This work was supported in partby Italian national funding programs PRIN, Contract 2007B5RZLE and FIRB,Contract RBA06L4S5.

E. Monaco is with the Università degli Studi di Modena e Reggio Emiliaand Istituto Universitario Studi Superiori di Pavia, Pavia, Italy (e-mail: [email protected]).

M. Pozzoni is with STMicroelectronics, Pavia, Italy.F. Svelto and A. Mazzanti are with the Università degli Studi di Pavia, Pavia,

Italy (e-mail: [email protected]; [email protected]).Digital Object Identifier 10.1109/JSSC.2010.2049780

applications at low cost, light weight and easy assembly willbe pursued [9].

A major obstacle to low power high frequency transceiverimplementation is due to the degradation with increasing fre-quency of key passive components, variable capacitors in partic-ular. This is particularly severe in frequency synthesizers wherehigh frequency VCOs consume large power, display relativelypoor spectral purity and have limited tuning range, and PLLsprescalers require large input voltage swing and eventually burnmore power than the VCO itself [10], [11].

As an example, several VCOs running beyond 100 GHzhave been recently presented but the reported tuning range, instandard CMOS technology, is always less than 3%, not evenenough to cover processing spreads [12]–[14]. To tackle theproblem, receivers architectures avoiding the need of VCOand PLL running at the input signal frequency have been in-vestigated. Examples can be found in [15]–[18] and consist ofsub-harmonic receivers or conversion to a sliding intermediatefrequency.

An alternative approach, usually pursued with compoundsemiconductor devices, relies on frequency multiplier circuits,driven by VCOs running at a lower frequency [19]–[21]. Themost effective solution exploits the nonlinearity of active de-vices to generate harmonics of the input signal. When designedin CMOS, they suffer from low-conversion gain, or even loss,large input capacitance, and single-ended output. For thesereasons the principle of frequency multiplication did not findextensive application to date.

In this paper we introduce and analyze new topologies ofCMOS frequency multipliers by two based on injection locking.The proposed circuits lead to a very low power dissipation,require limited input signal swing and provide a differentialoutput over a broad frequency range [22], [23]. Two differentcircuit topologies, tailored to Ku-band (13 GHz) and F-band(115 GHz), are presented. From experimental results, theKu-band multiplier, realized in a 0.13 m CMOS technology,displays an operation bandwidth from 11 GHz to 15 GHzwith a peak single ended voltage swing of 470 mV, and a corepower dissipation of 5.2 mW. The F-band multiplier, realizedin 65 nm CMOS technology, displays an operation bandwidthfrom 106 GHz to 128 GHz and a single-ended on-chip peakoutput swing of 330 mV with a core power dissipation of 6 mW.A prototype including the multiplier, driven by a half-frequencystandard LC-tank VCO, demonstrates an outstanding 13.1%tuning range around 115 GHz.

The paper is organized as follows: Section II reviews themost common circuit topologies of frequency doublers and

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1566 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 8, AUGUST 2010

Fig. 1. Frequency multiplier based on a Gilbert cell mixer (� is the mixerconversion gain) (a). Frequency multiplier based on device nonlinearity (b) andpush-push configuration to suppress the fundamental component and oddharmonics (c).

introduces the multiplier principle proposed in this paper.Sections III and IV present the analysis and design of the Ku-and F-band multipliers respectively. Experimental results areprovided in Section V and the conclusions follow in Section VI.

II. REVIEW OF FREQUENCY DOUBLING TECHNIQUES

Frequency doubler circuits at microwaves and millimeter-waves can be categorized in two main groups: (1) mixer based,(2) device nonlinearity based. The principles of operation andthe limits in CMOS technology are discussed in this section.

Fig. 1(a) shows the conceptual diagram of a mixer based fre-quency doubler [24]–[27]. The RF and LO ports of a Gilbert-mixer are driven by the same input signal, generating an outputcomponent at twice the input frequency. The main merit of thissolution is the broad frequency range of operation. A state ofthe art BiCMOS realization displays a large bandwidth, span-ning from 36 GHz to 80 GHz output frequency although with alarge current dissipation of 43 mA from 3.3 V supply [27].

As a drawback, a DC offset large at least as the desireddouble frequency signal appears at the output. It may saturatethe mixer limiting the conversion gain. In order to suppressthe fundamental component, fully balanced mixer topologiesare employed, with the drawback of large capacitance at theinput ports. Maximum operation frequency is also limited bythe parasitic capacitance at the sources of the switching quad.A widely adopted alternative approach relies on selectionof the harmonic component generated by a nonlinear activedevice [28]–[34]. The simplest schematic diagram is shownin Fig. 1(b). If the MOS transistor is driven into compression,

Fig. 2. Operation principle of the proposed frequency doublers.

the drain current is rich of harmonic components of the inputsignal. A resonant load selects the desired one (e.g., 2nd har-monic for frequency doublers) and suppresses the fundamental.For maximum conversion efficiency the device conductionangle must be low i.e., it must be biased to operate in class-B orclass-C. The amplitude of the fundamental is nevertheless muchlarger than its harmonics and achieving adequate suppressionby means of integrated LC filters, showing a moderate qualityfactor, is troublesome. A simple circuit technique to cancel outthe fundamental frequency at the output, commonly known aspush-push pair, is shown in Fig. 1(c). With balanced inputs, thefundamental component of the total drain current is at twicethe input signal frequency. To gain insight in the circuit perfor-mances at millimeter waves, the doubler has been designed in a65 nm CMOS technology for 115 GHz output frequency. With40 m/65 nm devices and 300 mV 0-pk single-ended inputswing, it burns 7 mW and shows a voltage conversion loss of7 dB. A larger device size reduces the conversion loss. On theother hand, to achieve 0 dB loss, eight times larger devicesare required, leading to roughly 400 fF input capacitance,excessively large to be driven at mm-waves. Simulations showthe same issues yet at lower frequency (e.g., Ku-band) within aless scaled technology node as 0.13 m CMOS.

As a further drawback, while the input is differential, theoutput is single-ended not suited in general to drive high per-formance mixers. At such high frequencies, differential signalsare also desirable to avoid the need of accurate modelling of cur-rent return paths [35].

The solution we propose in this paper makes use of a push-push pair to injection lock an oscillator running close to twicethe input signal frequency. CMOS Injection locked oscillatorstopologies for millimeter waves multipliers have been recentlyintroduced but display a limited operation bandwidth [36]–[38].The conceptual block diagram of the proposed solution is shownin Fig. 2. Compared to a simple push-push multiplier, a differ-ential output can be easily obtained by selecting a differentialoscillator topology and the trade-off between device size andoutput swing is mitigated, being the amplitude of the outputsignal primarily determined by the DC biasing current of theoscillator instead of the 2nd harmonic component of the drivingpush-push pair. The output swing is also at first order inde-pendent of the input signal swing. Compared to previously re-ported injection locked multipliers, the relatively large secondharmonic current injected by the push-push pair leads to a widerfrequency locking range.

MONACO et al.: INJECTION-LOCKED CMOS FREQUENCY DOUBLERS FOR -WAVE AND MM-WAVE APPLICATIONS 1567

Fig. 3. Schematic of the Ku-band push-push injection locked frequencydoubler.

III. KU-BAND FREQUENCY DOUBLER

A. Circuit Description

The circuit schematic of the first proposed injection-lockedfrequency doubler is shown in Fig. 3. The circuit is derived froma differential LC-tank oscillator but with a modified cross-cou-pled pair. In fact only one transistor is used to sustain os-cillations while the other is split in two devices, and

, driven by the differential input signal and implementingthe push-push locking pair. In the absence of the input signal,transistors act as common-gate devices, while providesnegative conductance across the LC-resonator. By circuit in-spection, assuming an ideal tail current source, the negative con-ductance across the LC resonator is equal to . Providedthere is enough loop gain, the circuit oscillates at its natural fre-quency, . When a differential input signal is ap-plied, with a proper DC biasing, and modulate the tankcurrent at a rate which is twice the input frequency and lock theoscillator.

The block diagram reported in Fig. 4 has been developedto estimate the circuit behavior (e.g., locking range and outputswing) in terms of the design parameters. Referring to Fig. 3,and assuming a sufficiently large output swing, the biasing cur-rent is steered between transistors and . Inparticular flows through or if the input signal (ei-ther or ) is larger than the voltage at the positive outputnode while flows through in the opposite case. In theformer while in the latter . Themodified differential pair is therefore modeled as a saturationblock with the input given by the difference between the positiveoutput voltage, fed back to the gate of , and the rectified inputsignal. A voltage attenuator of 1/2 is introduced in the feedbackpath because only half of the differential output is fed back tothe input. The output current, injected into the tank, resembles asquare-wave in phase with the input voltage difference and tog-gles between . The LC-tank, in the forward path, selectsonly the harmonic component closer to its resonance frequency.

Fig. 4. Behavioral block diagram of the frequency doubler of Fig. 3.

For correct operation, the loop gain must be larger than onewhile total loop phase must be an integer multiple of . Fromthe analysis of the block diagram in Fig. 4, the expression forthe one-sided frequency locking range, derived in [22], follows:

(1)

where is the tank quality factor, and is the harmoniccomponent of the rectified signal at twice the input frequency:

(2)

The output swing, , is maximum at tank resonance while de-creases as departs from , following the shape of the LCresonator. Assuming a square-wave tank current, can be ap-proximated as

(3)

Equation (1) is compared against Spectre RF simulations inFig. 5 (curve a), where the circuit in Fig. 3 has been designedfor a center frequency of 13 GHz, a tank quality factor of 8 anda biasing current of 6 mA. The value of in (1) has been takenfrom simulations, for each value of Vi, at the edge of the corre-sponding locking range. A good agreement between simulationsand calculations is observed. The above analysis also suggestshow to widen the locking range. In particular, from (1) the larger

the wider the locking bandwidth. A simple voltage di-vider in the feedback path can be introduced on purpose, in orderto increase the bandwidth. The corresponding reduction of theloop gain can be compensated by means of active devices withlarger width, i.e., with higher . In this way the locking rangeis made wider without requiring higher input signal level or sac-rificing the output swing. To gain insight, a capacitive voltage at-tenuator of 50% has been introduced in the feedback path of thecircuit of Fig. 3. The calculated and simulated locking range im-provement is quantified in Fig. 5 (curve b). With 400 mV inputsignal, the double sided locking range is larger than 30%.


Fig. 5. Simulated (dots) and calculated (continuous) one-sided locking rangefor the circuit in Fig. 3 (curve a). Improvement when a capacitive voltage divideris inserted in the feedback path (curve b).

B. Circuit Design

The Ku-band frequency doubler has been realized in a0.13 m CMOS technology with six metal layers and Alucap.The final schematic diagram is reported in Fig. 6 where, forbetter readability, DC biasing networks are not shown. Com-plementary p-type transistors are introduced, with respect toFig. 3, providing three main benefits: 1) as in complemen-tary differential pair LC-tank oscillators, the output swing isdoubled, saving half the current consumption for a desired am-plitude [39]; 2) output signals remain below and nominalsupply can be selected without compromising the long-termdevice reliability; 3) pMOS improve the circuit symmetry andreinforce the balance between the differential output. Frompost-layout simulations, amplitude and phase unbalances areless than 0.4 dB and 4 respectively. Based on the results ofthe above analysis, attenuation of the feedback signal widensthe locking range. Capacitors and provide, togetherwith the gate capacitances of and % attenuationof the feedback voltage. The tank inductor is a two turns 430pH differential spiral. To compensate the output amplitudevariation due to the selectivity of the tank, resonance frequencyis made tunable through MOS varactors. The total single-endedinput capacitance at the gate of the push-push pairs is 120 fF,corresponding to a high reactive impedance of 200 at 6.5GHz (the center input frequency). Input matching is thereforestraightforwardly achieved with two on-chip 50 resistorsshunting the inputs. The multiplier core draws 4 mA from 1.3V supply. The outputs are connected to a pair of open-drainbuffers, supplied off-chip with bias-tees, which provide nomi-nally 0 dB voltage gain when driving the 50 load impedanceof the measurement instruments.

IV. F-BAND FREQUENCY DOUBLER

The same basic idea is applied to a multiplier operating be-yond 100 GHz but a different topology, shown in Fig. 7, isselected: nMOS only devices are employed by virtue of theirhigher versus pMOS counterpart. Moreover, this multiplier isintegrated in a 65 nm process, with 1 V available voltage supply,making stacking of three devices un-feasible.

Fig. 6. Schematic of the realized Ku-band injection locked frequency doubler.

Fig. 7. Schematic of the F-band frequency doubler.

A. Circuit Description

The C-L-C -network and transistor form a Pierce oscil-lator [40]. Transistors , connected in push-push config-uration, inject a current in the resonator node 1 at twice the inputsignal frequency to lock the oscillator.

The core transistors are biased at a constant DC current, setby the two current mirrors , while capacitors are largeenough to behave as AC shorts. The supply to the circuit is pro-vided through a choke inductor to the center tap of theresonator. Moreover notice that grounded capacitors are explic-itly required in each node for proper operation and absorb alldevice parasitics, making the circuit particularly suited for veryhigh operation frequency.

Capacitor is introduced to balance the two output volt-ages, and . In fact, even if transistor sets 180 be-tween and the current injected in the resonator node 2, thetwo ports of the -network are not driven symmetrically andthe outputs are not balanced. Capacitor (of capacitance


Fig. 8. Simplified equivalent circuit of the F-band frequency doubler.

2C) suppresses the output common mode voltage . As anintuitive view, is shorted to ground by the low impedanceprovided by the series resonator formed by and the L/2branches.

To gain insight in the circuit operation, let’s focus on thesimplified equivalent circuit shown in Fig. 8. The two portsresonator is modeled by the 2 2 impedance matrix reportedin the figure. Being the network passive and symmetric,

while . Resistors R representlosses near resonance frequency. The independent left currentgenerator represents the locking current from the push-pushpair while the controlled current source on the right modelsthe feedback transistor . The fundamental component ofits output current is aligned in phase with the drivingvoltage . Furthermore is assumed with zero phase, asa reference, while the phase of the two output voltages areand respectively.

The two output voltages are solutions of the following systemof equations:

(4)

and are balanced (e.g., and ) onlyif . Simulated magnitude and phase of the two im-pedances in the absence of capacitor are shown in Fig. 9,with dotted lines, for a design example ( pH,fF, ). The impedance magnitudes are significantlydifferent and the two phases deviate from 180 by more than20 . Simulations with capacitor are shown with contin-uous lines in Fig. 9. In this case, the impedance magnitudesdiffer less than 1 dB over a fractional bandwidth of 20% aroundresonance frequency while the phases are almost perfectly 180apart. In presence of , inspection of the resonator leads tothe following simplified expressions for Z and near reso-nance frequency

(5)

where

(6)

Fig. 9. Simulated impedance magnitude and phase of the two ports resonatorin Fig. 8 without capacitor � (dotted lines) and with capacitor � (blacksolid lines).

Using (5) the system of (4) becomes:

(7a)

(7b)

From (7b), the two output voltages are balanced. Solution of(7a) following the approach of [41] gives the (single-sided) fre-quency locking range:

(8)

Given the tank quality factor, the locking range is increased byincreasing . Considering that is usually smallerthan , the latter primarily determines the oscillation am-plitude, i.e., should be maximized for maximum lockingrange. Referring to Fig. 7, this is achieved either maximizingthe driving amplitude , the biasing current or the devicewidth of push-push locking pair, .

B. Circuit Design

The doubler has been designed for a target output frequencyof 115 GHz in a 65 nm CMOS technology provided by STMi-croelectronics. Resonator capacitors are device parasitics only.The center capacitor is also implemented with the gate capaci-tance of a dummy nMOS device. The loaded quality factor is rel-atively low 4 . Losses are primarily determined by parasiticdevice resistors (gate and bulk resistances) and output conduc-tances. The resonator inductor has been maximized, for max-imum output amplitude at given power consumption. It is a 80pH single turn spiral of 2.6 um width trace, realized shortingtogether the two top-most Cu metal layers. Estimated quality


Fig. 10. Buffer stage of the F-band doubler.

factor is 15. For maximum series impedance and self resonancefrequency, the choke inductor, which provides the supply tothe circuit, is realized as a 15 um diameter 3.5 turns spiral ofa thin 0.4 m width trace in the topmost metal only. Fromelectromagnetic simulations, the self resonant frequency of thetwo inductors is close to 200 GHz. is 20 m/65 nm while

are 10 m/65 nm each one. Transistor sizes are rel-atively small leading to a low capacitance ( 15 fF on eachinput) loading the half-frequency signal source. The two biasingcurrents have been set equal to 3 mA and supply voltage is1 V. From simulations, assuming 300 mV input swing on eachpush-push transistor, the frequency locking range is 18% whilethe single-ended peak output swing, when driving the measure-ments buffer shown in Fig. 10, is 340 mV.

The first stage of the buffer is a differential common-sourcepair with inductive loads while the second is a differ-ential pair , supplied off-chip with bias-tees, driving the50 load of the measurement setup. If an off-chip local oscil-lator (LO) signal is superimposed to the bias voltage of the tailtransistor , the latter works as a down-conversion mixertranslating the multiplier output signals at a lower frequency.The complete buffer draws 17 mA from 1 V supply. The circuitdisplays a simulated loss of 3 dB and 16 dB when the secondstage works as a standard differential pair and down-conversionmixer respectively.

Two different chip versions have been realized. In the first, themultiplier is locked by an off-chip half frequency reference. Atransformer balun has been integrated to make the input signaldifferential.

In a second chip version, the multiplier is locked by anon-chip half-frequency VCO. It is a standard differential pairLC-tank oscillator. Supplied by 750 mV, it dissipates 6 mW.

V. EXPERIMENTAL RESULTS

Photomicrographs of the realized test chips are shown inFig. 11. Active area is 370 m 225 m and 120 m 120

m for the Ku- and F-band doublers respectively. Dies havebeen glued on PCB for experimental characterization. Supplyand DC biasing are provided through bond-wires while the high

Fig. 11. Photomicrographs of the realized test-chips. (a) Ku-band doubler;(b) F-band doubler with on-chip balun; (c) F-band doubler with on-chip VCO.

Fig. 12. Typical output spectrum of the Ku-band frequency doubler.

frequency input and output signals are provided through micro-probes. For testing the Ku-Band frequency doubler, differentialprobes and off-chid baluns are adopted for the input and outputsignals. The locking signal is provided by a microwave signalsource while the combined outputs are monitored on a spectrumanalyzer. Fig. 12 shows a typical wideband output spectrum.Suppression of the undesired input tone and its third harmonicare 53 dB and 57 dB respectively. Several samples have beencharacterized, showing a suppression always better than 45 dB.The measured differential output swing versus output fre-quency is shown in Fig. 13. The signal power at the input balunis constant at 3 dBm. Each balun output delivers 0 dBm, corre-sponding to 300 mV 0-pk on each input transistor, a value thatcan be easily provided if the multiplier is driven by an on-chipVCO. Measured peak power at the output of the off-chip balunis 7 dBm The estimated single ended on-chip voltage swingis 470 mV and the peak voltage conversion gain is 4 dB. Thethree curves have been obtained setting the varactors controlat minimum, half and maximum voltage. Varactors provide10% frequency tuning. At fixed varactor voltage the lockingrange (e.g., the fractional band around the free-run frequencyover which the output tracks the input without spurious tones)


Fig. 13. Measured output power for the Ku-band frequency doubler with var-actor control set at minimum, half and maximum voltage.

Fig. 14. Phase noise of the input source and at the output of the Ku-band fre-quency doubler.

is larger than 20%. Including the varactors tuning, the totaloperation bandwidth is extended to 30%.

Measurements of phase noise are shown in Fig. 14. Whenthe doubler is driven by a high spectral purity signal source(Agilent E82507), phase noise at the output is 6 dB higherthan at the input (which is the minimum theoretically expectedfrom the frequency multiplication by two) up to more than100 MHz offset. This is a consequence of the large lockingrange. In fact, as in any injection locked oscillator [42], [43],the phase noise contribution of the doubler is rejected up to anoffset frequency comparable with the locking bandwidth. Twoalternative experiments have been setup for the characterizationof the F-band doubler. They are shown in Fig. 15. When thesecond buffer stage is operated as a down-conversion mixer,two signal sources provide the input signal and the LO, asshown in Fig. 15(a). The output is measured by means of aSpectrum Analyzer, extended to V-band (50–75 GHz) througha compatible external harmonic mixer. The doubler has beentested also as shown in Fig. 15(b), without translating on-chipthe outputs to a lower frequency. In this case W-band (75–110GHz) waveguide probe and harmonic mixer have been em-ployed. Measurements are carried out up to 125 GHz frequency,

Fig. 15. Experimental setup for testing the F-band doubler. Characteriza-tion with on-chip down-conversion to V-band (a) and at the actual outputfrequency (b).

Fig. 16. Measured power versus multiplier output frequency.

as previously reported in [44], beyond the nominal bandwidthof the waveguides. Estimated in-band losses have been linearlyextrapolated up to the measured frequency [44].

Fig. 16 shows the measured output power versus the doubleroutput frequency with a constant input power of 0 dBm. The topcurve corresponds to the setup of Fig. 15(b). Maximum outputpower at center frequency is dBm. Being the simulatedbuffer loss equal to 3 dB, the single ended zero-peak voltageswing at the doubler outputs is estimated to be 330 mV, and thevoltage conversion gain is 0 dB, in good agreement with sim-ulations. The lowest curve in Fig. 16 is referred to the setupof Fig. 15(a), where the output signal is first down-convertedon-chip. The LO frequency was set to 55 GHz leading to an in-termediate frequency spanning from 56 to 73 GHz. Being thesimulated conversion loss of the buffer 13 dB larger, when it isconfigured as a mixer, the two measurement setups give consis-tent results.


Fig. 17. Measured amplitude difference between the two outputs of the F-bandfrequency doubler.

Fig. 18. Phase noise of the input source and at the output of the F-band fre-quency doubler.

Due to the lack of differential probes and waveguide baluns,the two outputs of the frequency doubler have been testedsingle-ended. Measured amplitude difference between the twooutputs, shown in Fig. 17, is always less 1 dB, i.e., within themeasurement inaccuracy of the setup.

Test of the phase noise degradation at the output is shown inFig. 18. The lowest curve is the phase noise of the input source.The top curve is the phase noise at the output. At low offsetfrequency, the output phase noise is 6 dB higher than at the input,as expected. The measured output phase noise above 300 kHzoffset is bounded by the setup noise floor which is relatively high( dBc/Hz), determined by the large conversion losses ofthe harmonic mixer and probe.

Finally the doubler with on-chip half frequency VCO hasbeen tested [23]. The complete SubTHz frequency generatordisplays a 13.1% frequency tuning range around 115 GHz. Theoutput phase noise is estimated to be dBc/Hz at 3 MHzoffset frequency with a total power dissipation (VCO and dou-bler) of 12 mW.

VI. CONCLUSION

Frequency multipliers have not drawn much attention forRF CMOS applications mainly because no significant ad-vantage derives from running the oscillator at a fraction ofthe reference frequency. On the contrary, at microwaves andmillimeter-waves, one of the bottleneck for high performancelow power transceiver implementation resides in the frequencysynthesizer where both the reference oscillator and the dividerconsume significant power due to poor performance of pas-sive components, variable capacitors in particular. Two newfrequency doubler topologies have been introduced in thispaper. In both cases a pair of transistors arranged in push-pushconfiguration generates the 2nd harmonic current componentto lock a differential LC-tank oscillator. Compared to a simplepush-push pair driving a tuned load, already proposed in theliterature, the presented technique leads to smaller input capac-itance, higher conversion gain and provide a differential outputat low power dissipation. Performances have been provenexperimentally on two different test-chips, tailored to Ku-bandand F-band respectively.

Driven by a half frequency on-chip VCO, the F-band dou-bler demonstrates a 13.1% tuning range and low phase noise at115 GHz making this technique very promising for realizationof low power high performance frequency generators beyond100 GHz.

ACKNOWLEDGMENT

The authors are grateful to Prof. G. Jaquemod (Polytech’NiceSophia, UNS) and Prof. M. Borgarino (Università di Modena,Italy) for providing silicon access for the Ku-band prototype.

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Enrico Monaco (S’09) was born in Carpi, Italy, in1983. He received the Laurea degree (summa cumlaude) in electrical engineering from the Universityof Modena and Reggio Emilia, Modena, Italy, in2008. He is currently working toward the Ph.D.degree in electrical engineering at University ofModena and Reggio Emilia, Italy. He holds aresearch grant on RFIC design topics from IstitutoUniversitario di Studi Superiori di Pavia (IUSS).

His research activity is focused on integratedcircuit design for RF and millimeter-wave applica-

tions on CMOS technologies.Mr. Monaco received the AMD/CICC Student Scholarship Award for a paper

presented at CICC 2009.

Massimo Pozzoni received the Laurea degree inelectronics engineering from the University of Pavia,Italy, in 1994.

In the same year he joined STMicroelectronics,Italy, working as an analog IC designer for powermanagement and control. From 1998 to 2000, heled the analog design of the Wireline Division. In2000, he started working on multi-gigabit CMOSand BiCMOS clock-data recoveries and PLLs forserial communication. Mr. Pozzoni is presentlyleading the Radio Frequency and High Speed design

group in the Studio di Microelettronica, a Scientific Laboratory in cooperationbetween STMicroelectronics and the University of Pavia. His research interestsinclude multi-gigabit serial interfaces for I/O backplanes, millimetric-waveradio frequency design and frequency synthesis.


Francesco Svelto (M’98) received the Laurea andPh.D. degrees in electrical engineering from Univer-sità di Pavia, Italy, in 1991 and 1995, respectively.During 1995–1997 he hold an industry grant for re-search in RF CMOS. In 1997 he was appointed Assis-tant Professor at Università di Bergamo, and in 2000,he joined Università di Pavia, where he is now Pro-fessor. His current interests are in the field of RF andhigh speed integrated circuits.

He has been technical advisor of RFDomus Inc.,a start-up he co-founded in 2002 dedicated to highly

integrated GPS receivers. After merging with Glonav Inc. (Ireland), RFDomushas been acquired by NXP Semiconductors in 2007. Presently he is the Directorof a Scientific Laboratory, joint between Università di Pavia and STMicrolec-tronics, dedicated to research in Microelectronics, with emphasis to mm-wavesystems for wireless communications, high-speed serial links and read-writechannels for hard disk-drives.

Dr. Svelto is a member of the technical program committee of the IEEE In-ternational Solid State Circuits Conference and has been a member of IEEECustom Integrated Circuits Conference, Bipolar/BiCMOS Circuits TechnologyMeeting and European Solid State Circuits Conference. He served as AssociateEditor of IEEE JOURNAL OF SOLID-STATE CIRCUITS (2003–2007), and as GuestEditor for a special issue on the same journal in March 2003. He is co-recipientof the JOURNAL OF SOLID-STATE CIRCUITS 2003 Best Paper Award.

Andrea Mazzanti (M’06) received the Laurea andPh.D. degrees in electrical engineering from the Uni-versità di Modena and Reggio Emilia, Modena, Italy,in 2001 and 2005 respectively.

During the summer of 2003 he was with AgereSystems, Allentown, PA, as an internship. In 2005he got a postdoctoral position from the Università diPavia, Italy, working on CMOS RFICs for cell-phoneapplications. From 2006 to 2009 he was AssistantProfessor at the Università di Modena and ReggioEmilia, Italy, teaching a course on advanced analog

IC design. In January 2010 he moved to the Università di Pavia, Italy. His mainresearch interests cover device modelling and integrated circuit design for highspeed communications and millimeter-waves systems. In this field he is authorof more than 50 technical papers.

Since 2008, Dr. Mazzanti has served as a member of the technical programcommittee of the IEEE Custom Integrated Circuit Conference (CICC) and IEEEInternational Conference on IC Design and Technology (ICICDT).

Documents

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