RECONFIGURABLE BIT-STREAM PARSER

Sunyoung Lee, Hyungyu Kim, Sinwook Lee, Jaebum Jun, and Euee S. Jang

Digital Media Laboratory, Department of Electronics & Computer Engineering, Hanyang University, Seoul, Korea

ABSTRACT

In this paper, we propose a novel method to describe the bit stream syntax and parsing of video coding. Multiple codecs are being increasingly used in many applications, so flexible and efficient design of multiple codecs in a chip is becoming a very important issue. In MPEG, a standardization activity called reconfigurable video coding (RVC) addresses the reconfigurable design of video codecs based on functional units drawn from the existing MPEG codecs. In the RVC framework, reconfigurable bitstream syntax and its parsing play an important role in allowing new requirements, such as reconfigurable syntax manipulation and bitstream level transcoding, to be posed in multi-codec environments. In this paper, we propose a compact decoder description language (CDDL) to efficiently represent the syntax parsing of bitstreams in a compact manner. The effectiveness of the proposed method is demonstrated through bitstream conformance testing, bitstream manipulation, and compactness evaluation of the parser description.

Index Terms—Decoding, Multimedia systems, Reconfigurable architectures, Video codecs

1. INTRODUCTION As new digital media services are continuingly being introduced, the one-tool-one-functionality principle in MPEG is no longer true in video coding. Existing video coding standards have become competitors in emerging video services including digital TV, IPTV, and HD-DVD. Therefore, the support of multiple codecs in a single device has become one of the great challenges in the market.

Industry has responded by including multiple codecs in software or hardware provided to consumers. As a typical example, STMicroelectronics has released a set-top-box decoder chip, which supports both H.264/MPEG-4 AVC and MPEG-2 [1]. Texas Instruments has also developed a platform to support H.264/AVC main profile, VC-1, MPEG-2, and MPEG-4 simple profile (SP)/advanced SP [2].

However, the current implementation of multiple codecs in a single platform has limitations as it does not utilize the similarity of different codecs in the decoding process to a full scale. For example, DCT is a commonly used tool in

both MPEG-2 and MPEG-4. The usage of DCT in MPEG-2 is almost identical to that in MPEG-4 Part 2. In principle, other tools in one codec such as quantization and motion compensation could also be shared in other codecs.

For the more organized way to support multiple codecs in a single platform, MPEG recently started a standardization activity called reconfigurable video coding (RVC) [3]. MPEG RVC is a framework to define the generic description of the decoding process and the decoding tools. In MPEG RVC, additional information in the bitstream is defined as decoder description (DD) [4]. In DD, the bitstream syntax and parsing is described and represents not only the existing codecs, but also the new codecs based on the tools from the existing codecs.

In this paper, we propose a compact decoder description language (CDDL) to represent the syntax parsing of the bitstream in a compact manner. The syntax paring information includes the syntax elements, parsing rules of the syntax elements, and the parsed outputs. A mechanism to form a reconfigurable parser from the CDDL is also introduced. We demonstrate the effectiveness of the proposed method through bitstream conformance testing and bitstream manipulation such as bitstream level transcoding.

This paper is organized as follows: in Section 2, the concept of DD is introduced as well as how CDDL represents and processes DD. Section 3 deals with the process of forming a reconfigurable parser using CDDL. The use-case scenarios and results of the proposed method are given in Section 4. Finally, we summarize the paper in Section 5.

2. DECODER DESCRIPTION OF RVC RVC supports multiple codecs in a single platform that contains a tool library consisting of functional units (FUs) that are coding tools drawn from the existing MPEG coding standards [5]. New FUs can also be added to the tool library, and new codecs can be configured by these FUs.

The receiver in the RVC framework needs a decoder description to decode the encoded video bitstream; the decoder description describes the reconfigurable bitstream syntax parsing and the reconfigurable connection among the coding tools [4] as shown in Fig. 1.

1061978-1-4244-2571-6/08/$25.00 ©2008 IEEE ICME 2008

Transmitter

Encoder

Receiver

DecoderDecoder Description

Encoded Video Data

1. Reconfigurable bit2. Reconfigurable connection

Transmitter

Encoder

Receiver

DecoderDecoder Description

Encoded Video Data

1. Reconfigurable bitstream syntax2. Reconfigurable connection

Fig. 1. Transmitter and receiver connection in the RVC framework 2.1. Decoder description The decoder description is used to form a decoding solution in the RVC framework. How the decoder description is described is determined by the decoder description language (DDL). The two technologies have been introduced for DD representation [4] in the current MPEG standardization activity. In [4], we proposed the CDDL, which allows for compact representation of DD. In this paper, the DDL we introduce is based on CDDL. 2.2. Compact decoder description language CDDL uses several tables to represent bitstream syntax parsing and the decoding process. There are four tables for the description of bitstream syntax parsing. These tables describe syntax elements, their connections, and outputs of the syntax element parsing. In addition, the code values for variable length coding (VLC) such as Huffman coding are also described as follows: • SET (Syntax Elements Table): information about the

bitstream syntax element and its C-like parsing algorithm • SRT (Syntax Rule Table): branch information in the

bitstream parsing • CSCIT (Control Signal and Control Information Table):

output information extracted from the bitstream parsing • DVT (Default Value Table): symbols and code values

for VLC Tables 1 through 4 are examples of the four tables as

shown in Fig. 2. Each syntax element (SET in Table 1) is parsed when it is called during the processing of the SRT, as shown in Table 2. Also in Table 2, the syntax element, S0, is called first where 32 bits are read and put into C0. C0 is an element in the CSCI table in Table 3, which is used as a condition in the branch operation in the SRT. Table 4 (DVT) lists the pairs of the symbol and the code for decoding them.

These four tables can be described in the textual description (TD) for human readability and finally converted to a binary description (BD) for compact representation. Fig. 3 shows an example of a conversion of some parts of the MPEG-4 specification to BD [4].

Table 1. Syntax Element Table (SET)

Index Parameter Processing S0 2 READ P1 > P2; S1 2 READ P1 B > P2;

Table 2. Syntax Rule Table (SRT)

Index Parameter Processing R0 N/A do {

S0(32, C0); If ((232≤C0) && (C0≤235)) S0(8, C1); Else S1(3, C2);

…

Table 3. Control Signal and Context Information Table (CSCIT) Index Type Syntax output name C0 integer visual_object_start_code C1 integer profile_and_level_indication

Table 4. Default Value Table (DVT)

Index Name Type Value

D0 MCBPC symbol 0, 1, 2, 3, 4, 5, …

D1 MCBPC code 1, 001, 010, 011, 0001, …

Fig. 2. Bitstream syntax parsing process

3. RECONFIGURABLE BITSREAM PARSER

3.1. Syntax parser formation from CDDL A dedicated syntax parser for a bitstream can be built from a generic syntax parser based on a finite state machine (FSM), which is included in the tool-box as an FU. More specifically, a virtual FSM is configured to parse the bitstream according to the corresponding decoder description, as shown in Fig. 4. In this figure, the flow control of the syntax elements can be constructed; the syntax elements are from the SET of the DD, the connection information in the SRT, and the state definition in the CSCIT. It is possible to generate a syntax parser in various programming language environments (e.g., C or C++). In this paper, implementation using the C language is explained.

Fig. 5 shows how a virtual FSM can be configured with four tables. The SRT indicates the next syntax element and then the parser loads the parsing algorithm of the syntax element from the SET. During the parsing process, the

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parser brings the default values from the DVT if the syntax element needs the VLC codes. The parser reads the input bitstream, parses it, and then sends the outputs as CSCI. The outputs are classified by the CSCIT and can then be employed by the further parsing processes. Finally, they become data for decoding process (e.g., mcbpc, macroblock type and coded block pattern for chrominance; cbpy, coded block pattern for luminance; and DCT coefficients for MPEG-4).

VisualObjectSequence() { No. of bits Mnemonicdo {

visual_object_sequence_start_code 32 bslbfprofile_and_level_indication 8 uimsbfif (profile_and_level_indication == 11100001-11101000) {

next_start_code_studio()extension_and_user_data( 0 )StudioVisualObject()

} else {while ( next_bits()== user_data_start_code){

user_data()}VisualObject()

}} while ( next_bits() != visual_object_sequence_end_code)visual_object_sequence_end_code 32 bslbf

} (a) MPEG-4 specification

Index Parameter Processing DescriptionR0 do {

S0(32, C0);S0(8, C1);If ((C1 >= 225) && (C1 <= 232)) {

R1(); // next_start_code_studio()R2(0); // extension_and_user_data( 0 )R3(); // StudioVisualObject()

}Else {

while(S3(32,C2)==434){R4(); //user_data()}

R5(); // VisualObject()}

}while(S3(32,C3)!=433);S0(32, C3);

VisualObjectSequence

(b) SRT

[VisualObjectSequence] (“do {S0(32, C0);S0(8, C1);If ((C1 >= 225) && (C1 <= 232)) {

R1(); R2(0); R3(); }

Else {while(S3(32,C2)==434){

R4(); }R5(); }

}while(S3(32,C3)!=433); S0(32, C3);”)

(c) Textual description

00000000001100000000101100101001000110000000000000000000000010000000000000101110101001000110000000000000000000000010001111100000000000000010000010000000100000001100101001000001000010100010000011000000100000111001010000000000000001000010011010010000011……

(d) Binary description

Fig. 3. Conversion of MPEG-4 specification to binary description

Fig. 4. Flow control of syntax elements (Si: syntax element)

Fig. 5. Bitstream syntax parser

4. USE-CASE SCENARIOS

To meet RVC requirements [6], three important points must be confirmed: 1) the compactness of the DD representation, 2) the representation capability of the DD to support the conventional codecs and the new codecs, and 3) the reconfigurability of the bitstream syntax description. Based on these requirements, in this section we provide DDs for the conventional codecs using CDDL and suggest two application scenarios to evaluate the effectiveness of the proposed method: bitstream conformance testing and bitstream manipulation. 4.1. Compact decoder description representation We created a DD for each of the two codecs: MPEG-2 main profile (MP) and MPEG-4 simple profile (SP). Table 5 shows the amount of bits required to represent the DDs in both textual and binary representation. From the table, it is apparent that the texture description (TD) needs further compression; however, even if the compression efficiency could be increased, a compression algorithm such as WinZip would increase the computational complexity. In contrast, our proposed binary description (BD) avoids this problem by not requiring a compression algorithm while maintaining

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a comparable size to WinZip. Therefore, BD clearly shows its advantages in compactness and low complexity.

Table 5. Representation bits (bytes) Textual

description Binary

description TD compressed

by WinZip MPEG-2

Main Profile 32,575 6,060 5,678 MPEG-4

Simple Profile 19,555 3,105 3,091

4.2. Bit-stream conformance testing A reconfigurable bitstream parser built from a DD can be used for bitstream conformance testing. To test the bitstream, the parser can process the bitstream parsing after generating a syntax parser from the corresponding DD. If the bitstream is encoded differently, the parser can detect the parsing error without the need to invoke the entire decoding process. 4.3. Bit-stream reconfiguration In this section, we present two types of bitstream re-configuration: 1) bitstream manipulation and 2) profile-free configuration. Bitstream manipulation includes the order change of the syntax element order in the bitstream, the deletion of the syntax elements from the bitstream, and insertion of a new syntax element into the bitstream as shown in Fig. 6.

One good example of bitstream syntax manipulation can be shown by replacing the current entropy coding method with another. This means that we can design a codec the same as the conventional codec as far as the decoding process is concerned, but different from the current codec in entropy decoding with different VLD tables and algorithms.

A profile-free codec can be built by combining the coding tools in the RVC tool-box, as shown in Fig. 7. This codec produces a new bitstream that can be described by a new DD. The use of the DD allows the RVC decoder to be profile independent.

5. CONCLUSION In this paper, we reviewed an RVC framework and introduced a decoder description for RVC. We explained CDDL as an effective means to describe the DD. Using the DD, the bitstream parser for a codec can be adaptively generated. Finally, we demonstrated the effectiveness of the proposed method through bitstream conformance testing and bitstream reconfiguration.

ProcessingS0(32,C32);S0(2,C33);do{

S0(1,C34);}while(C34!=0);S0(1,C35);

ProcessingS0(32,C32);S0(1,C35);do{

S0(1,C34);}while(C34!=0);S0(2,C33);

(a) Syntax order exchange

ProcessingS0(32,C32);S0(2,C33);do{

S0(1,C34);}while(C34!=0);S0(1,C35);

ProcessingS0(32,C32);S0(1,C35);S0(32, C40);do{

S0(1,C34);}while(C34!=0);S0(2,C33);

(b) Syntax insertion

ProcessingS0(32,C32);S0(2,C33);do{

S0(1,C34);}while(C34!=0);S0(1,C35);

ProcessingS0(32,C32);S0(1,C35);S0(2,C33);

(c) Syntax deletion

Fig. 6. SRT updates for bitstream manipulation

Fig. 7. Profile-free configuration

6. REFERENCES

[1] DIGITAL TV DesignLine homepage http://www.digitaltvdesignline.com/products/showArticle.jhtml?articleID=205200512 [2] TEXAS INSTRUMENTS homepage http://focus.ti.com/docs/toolsw/folders/print/tmdmpeg4d.html [3] Study of Reconfigurable Video Coding V1.0, ISO/IEC JTC1/SC29/WG11 N8040, Montreux, CH, April 2006. [4] WD 5 of ISO/IEC 23001-4 Codec Configuration Representation, ISO/IEC JTC1/SC29/WG11 N9223, Lausanne, CH, July 2007. [5] WD 5 of ISO/IEC 23002-4 Video Tool Library, ISO/IEC JTC1/SC29/WG11 N9224, Lausanne, CH, July 2006. [6] Reconfigurable Video Coding Requirements v2.0, ISO/IEC JTC1/SC29/WG11 N8069, Montreux, Switzerland, April 2006.

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