Biasing Technique for Reduced Process and Temperature Variations of High Speed, Low

Power Switched Capacitor Circuits Botros George

Smart Wireless Systems botros.george@sws.com.eg

Mohamed Dessouky Ain Shams University

mohamed.dessouky@ieee.org

Hisham Haddara Ain Shams University

hisham.haddara@sws.com.eg

Abstract—A biasing technique that minimizes the process and temperature variations of the slew rate and the gain bandwidth product of the amplifiers at the core of any switched capacitor circuit is presented. It is based on using a switched capacitor current reference coupled with weak inversion biasing of the input differential pair of the amplifier. A minimum value for the inversion coefficient that maximizes the transconductance efficiency without compromising the parasitic capacitance at the amplifier’s input is analytically derived. The proposed biasing circuit is analyzed and designed using a 130nm CMOS process. The performance was verified by simulations with a high speed telescopic OTA.

Index Terms— constant slew rate, weak inversion.

I. INTRODUCTION rocess variations are one of the critical issues that an analog designer has to deal with. This typically leads to keeping large design margins to guarantee the

performance across different process, supply and temperature corners. Within the context of switched capacitor (SC) circuits, process variations manifest themselves in large variations of the settling error of the SC stage. These variations can be as large as +/-50% [1], which mandates using larger currents than required to maintain the performance. In high speed SC circuits, this extra current penalty can be quite large leading to unnecessarily higher power consumption.

This paper describes a biasing scheme that overcomes the above problem. The paper is organized as follows. Section II describes different schemes that are typically used to bias SC circuits. The proposed biasing scheme is discussed in Section III together with a quantitative comparison between biasing of differential pairs in weak and strong inversion regions in terms of the parasitic capacitance at the amplifier’s input. In Section IV, the design of the proposed SC current reference is discussed in detail. Finally Simulation results of the proposed technique are presented in Section V.

II. BIASING TECHNIQUES OF SWITCHED CAPACITOR CIRCUITS In a typical low power design, the amplifier within a SC

stage will be slewing for a portion of the clock phase then exponentially settling during the rest of the clock phase with a time constant that is proportional to its transconductance and its capacitive load such that the settling error is governed by the amplifier’s slew rate and gain bandwidth product (GBW). Different biasing schemes are reported in literature to control the amplifier’s dynamics across process and temperature corners. They will be briefly reviewed to better illustrate the problem [1]. Constant current biasing is an obvious alternative in which the current is referenced to a bandgap voltage and a trimmed resistor. The current value should be high enough to satisfy the settling requirements across different corners. This approach is the worst in terms its power efficiency. Another possible approach is to use a PTAT (Proportional to absolute temperature) current to compensate for transconductance drop with temperature. However this fails to compensate for the process variations. Meanwhile it increases the overdrive voltages at high temperatures. Constant-gm Biasing is also a widely used technique. The target of this technique is to maintain a constant transconductance by referencing it to a resistor. In practice this can only be achieved by using a precise off-chip resistor. Over and above, the amplifier’s current (and hence its slew rate) is still a strong function of process variations.

Manuscript received June 28, 2007.

All the above schemes suffer from a common problem that is the biasing current is referenced to a resistor, which has completely different process variations compared to the amplifier’s capacitive load. Thus the amplifier’s slew rate and GBW show very large process variations. In [1] the current was referenced to a capacitor to overcome this problem. This was done using a DLL to generate a current that tracks the capacitance and the sampling frequency variations. Although the slew rate is now kept constant, however due to the square root dependence of the transconductance on the current, the GBW (and hence the settling error) fails to track the capacitance and frequency variations.

III. CONSTANT SLEW RATE AND GBW BIASING The proposed scheme takes the constant slew rate biasing

approach one step further while using a much simpler implementation as follows. The differential pair of the amplifier can be biased in weak inversion to benefit from the

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linear relation between the transconductance and the current. Hence the GBW also tracks the capacitance and frequency variations. The different trade offs involved and the optimum value for the inversion coefficient will be analyzed in the next subsection. Meanwhile the DLL can be replaced by a switched capacitor current reference to generate a current that is proportional to the capacitance and the sampling frequency. The proposed switched capacitor current reference is discussed in detail in section IV.

Differential Pair Biasing: Weak Inversion region as a high speed, low power alternative for SC circuits

A key design parameter of any amplifier is the transconductance to current ratio (gm/ID) of its input differential pair (or equivalently the overdrive voltage). Reference [2] showed that operation in weak inversion having the maximum value of gm/ID ratio leads to the lowest power dissipation for a required settling accuracy. However the choice of gm/ID ratio entails a trade off between power efficiency and the input parasitic capacitance of the amplifier, which in turn contributes to the amplifier’s capacitive load in closed loop reducing its speed (or increasing its power dissipation). In this section we will analytically derive an engineering estimate for gm/ID ratio that resolves this trade off. Towards that end we start with an expression for the ratio between the parasitic capacitance seen at the input of a differential amplifier in both weak and strong inversion regions trying to find the condition that makes them equal from which we can deduce the maximum achievable gm/ID that does not increase the amplifier’s capacitive load. Those parasitic capacitances are given by [3]

2= ( ) in strong inversion3

1 ( ) in weak inversion

si ox si

parasitic

wi ox wi

Cp C WLC

nCp C WLn

⎧⎪⎪= ⎨ −⎪ =⎪⎩

(1)

Where with CDEP being the depletion capacitance per unit area and COX is the gate oxide capacitance per unit area, a typical value for n is about 1.5. To accurately model the transition between weak and strong inversion regions we resort to the EKV MOSFET modeling equations [3] as the square law fails short in this respect. A key parameter of this model is the inversion coefficient IC, which is a normalized measure of the drain current that describes the level of channel inversion. It is given by

( ) /ox DEP DEPn C C C= +

( ) ( )22 /D

OX T o

IICn C V W L I W Lμ

= =/

DI (2)

With Io being a technology dependent current defined at the transition point between weak and strong inversion, VT is the thermal voltage, μ is the surface mobility, ID is the drain current, W, and L are the effective channel width and length, respectively. Using (1) and (2) the ratio Cpsi/Cpwi can be written as

22=3 1

si D si wi si

wi D wi si wi

Cp n I IC LCp n I IC L

⎛ ⎞ ⎛ ⎞ ⎛⎜ ⎟ ⎜ ⎟ ⎜− ⎝ ⎠ ⎝ ⎠ ⎝

⎞⎟⎠

(3)

To find the ratio between the different elements we make

following assumptions. Firstly, the value of the required drain current for a given settling accuracy is inversely proportional to the gm/ID ratio, which is a reasonable assumption as long as the current is limited by the slewing portion of the settling time [2]. Secondly, to maintain the same intrinsic gain of the device (gm/gds), with gds being the output conductance of the device, the channel length will be also inversely proportional to gm/ID. Hence the ratio Cpsi/Cpwi is given by

( )( )

3

3

/2=3 1 /

Dsi wi

wi siD si

gm ICp n ICCp n ICgm I

⎛⎜− ⎝ ⎠

wi ⎞⎟ (4)

Based on the EKV model the inversion coefficient can be related to the gm/ID ratio and the over drive voltage [3] and the ratio Cpsi/Cpwi can be simplified to

22 1= with 3 1 1 ( / )

si si wii

wi wi si T D i

Cp n X X XCp n X X nV gm I

⎛ ⎞ ⎛ ⎞−=⎜ ⎟ ⎜ ⎟− −⎝ ⎠ ⎝ ⎠

1 (5)

The maximum (minimum) value for the gm/ID (IC) that can be used without increasing the capacitive load of the amplifier can be found by equating the above ratio to one. A typical value for the overdrive voltage is about 200mV (gm/ID=9V-1) from which XSi can be calculated. This gives a value of about 20V-1 for (gm/ID)wi and an inversion coefficient of about 0.1. Hence we can fully benefit of the power efficiency of the transistor in weak inversion and the linear relation between the transconductance and the biasing current together with other numerous advantages like reduced saturation voltage and reduced input referred noise and offset voltages.

IV. THE PROPOSED SWITCHED CAPCITOR CURRENT REFERENCE Switched capacitor current references make use of the

equivalence between a switched capacitor and a resistor. Historically they have been used for the low temperature dependence and reduced process variations of the capacitors compared to resistors [4]-[6]. In all these designs the current is referenced to a clock frequency, a capacitor, and a bandgap voltage reference. The design presented in [4] is almost the first SC current reference reported in open literature. It uses a switched capacitor integrator in a feedback loop at the core of the current reference, which consumes significant amount power because of the settling requirements of the integrator. The proposed SC current reference is shown in Fig. 1. It combines the advantages of the 2 architectures presented in [5] and [6] in a low power low voltage implementation. Firstly by using 2 SC branches clocked at opposite phases thus the voltage ripples generated at the gates of the current mirrors due to the charging and discharging of the capacitors are at twice the clock frequency which facilitates the filtering process of those ripples [5]. And secondly the reference voltage is applied to the amplifier’s input, which eliminates the need for a fast buffer if the reference was sampled by the SC branch [6].

A. Design Considerations 1) Current Ripple Magnitude Control

The main source of current ripples is the voltage ripples at

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node 1 due to charging and discharging of the switched capacitor. They will be filtered in 2 ways. Firstly, as shown in [6] the ratio between the switched capacitor C1 and the fixed capacitor C2 determines the ripples magnitude. Considering the proposed circuit of Fig. 1, the switched capacitor is split into 2 branches operating at opposite clock phases and the output current is given by Iout=C1FclkVref. This means that for the same current value the ripples magnitude is halved and its frequency is doubled making them four times easier to filter. Secondly, the residual voltage ripples at node 2 can be filtered to any desired magnitude using a passive RC filter as shown in Fig. 1.

2) Stability Analysis The dominant pole is at the amplifier’s output (node 2),

formed by the amplifier’s output resistance and capacitance and the capacitance at the gates of the current mirrors. The closest non-dominant pole is at node 1, formed by the ripple filtering capacitor C2 with the parallel combination of the SC capacitor resistor and the output resistance of the current mirror. The choice of C2 entails a trade off between the ripple magnitude reduction and the phase margin, which can be resolved using miller compensation capacitance between nodes 1 and 2. Thus C2 can be optimized to minimize the ripples. It is interesting to observe that the amplifier’s bandwidth is not proportional to the sampling frequency of the SC branch. In fact it is intentionally made slow to filter out the ripples. This means that there is no power penalty in increasing the sampling frequency unlike the originally proposed circuit of [4].

3) Effect of Temperature In conventional biasing schemes the temperature

dependence of the resistor causes large variations in the bias current. On the amplifier side, the transconductance drops with temperature. If we add to this the bias current variations then the expected spread of the gain bandwidth can be very large. On the other hand, for the proposed technique, capacitors in general have a much lower temperature dependence compared to resistors which leads to lower variations in the absolute value of the current with temperature. In addition, the reference voltage used for current generation can be designed to have a positive temperature coefficient that cancels the transconductance drop with temperature. Thus current at the lowest temperature limits the overall power consumption.

V. SIMULATION RESULTS To verify the above concepts, the proposed circuit was

designed using a 130nm CMOS process. It was used to bias a high speed telescopic OTA having a target GBW in the order of 1GHz with its input differential pair sized to have gm/ID=20V-1. The simulations were done over a temperature range of -40oC to 85oC with a constant reference voltage. Fig. 2 shows the transient response of the tail current of the OTA, a startup time in the order of 20μs is required for the current to reach its steady value of about 1mA. Fig. 3 and Fig. 4 show the transconductance and the tail current of differential pair of the amplifier as a function of the capacitance and the sampling frequency of the switched capacitor branches. A very linear relation is observed for both cases, which agrees with the theoretical expectations. This can be used for power scalable switched capacitor circuit design where the power consumption will adaptively scale with the sampling frequency. Table I and Table II compares the simulations results of both schemes across different process corners. Concerning the tail current variations, resistor based biasing showed a maximum variation of 110%. This large variation not only impacts the slew rate and the gain bandwidth product but also the amplifier’s gain and dynamic range through the output resistance and the saturation voltages of different transistors. On the other hand, the proposed scheme has a maximum variation of 20%, which is a reflection of +/-10% capacitor process spread and thus the slew rate is kept constant.

Concerning the gain bandwidth product, the process and temperature variations of the transconductance have a large impact. Thus for a fair comparison consider first resistor and capacitor process variations only. Resistor based biasing showed a maximum variation of 77%, while that of the proposed scheme is as low as 0.6%. If the temperature and MOSFET corners were also taken into consideration, the variations of resistor based biasing jumps to 153% while that of the proposed scheme is 31% over the temperature range of -40oC to 85oC. The above results show that large design margins can be saved by adopting the proposed biasing technique resulting in significant power savings.

Fig. 1. The proposed switched capacitor current reference.

VI. CONCLUSIONS A biasing scheme was presented that minimizes the effect

of process and temperature variations on the performance of switched capacitor circuits. It is based on weak inversion biasing of the amplifier’s differential pair, in addition to referencing the biasing current to capacitor of the same type of the amplifier’s load. Theoretical analysis was verified by simulations across process and temperature corners. The proposed technique proved to be superior to the standard resistor referenced biasing schemes resulting in much lower process and temperature sensitivity of the power consumption of SC circuits.

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REFERENCES

Fig. 2. Transient response of the proposed current reference.

[1] Nikolaus Klemmer, and Emad Hegazi, “A DLL-biased 14-bit DS analog-to-digital converter for GSM/GPRS/EDGE handsets,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 330-338 , Feb. 2006.

[2] Feng Wang, and Ramesh Harjani, “Power analysis and optimal design of Opamps for oversampled converters,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing , vol. 46, no. 4, pp. 359-369 , April 1999.

[3] D. M. Binkley, C. E. Hopper, S. D. Tucker, B. C. Moss, J. M. Rochelle, and D. P. Foty, “A CAD methodology for optimizing transistor current and sizing in analog CMOS design,” IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 2, pp. 225-237, Feb. 2003.

[4] G. Torelli, and A. de la Plaza, “Tracking switched-capacitor CMOS current reference,” IEE Proceedings-Circuits, Devices, and Systems, vol. 145, no. 1, pp. 44-47, Feb. 1998.

[5] Q. A. Khan, S. K. Wadhwa, and K. Misri, “A low voltage switched-capacitor current reference with low dependence on process, voltage and temperature,” Proceedings of the 16th International Conference on VLSI Design, pp. 504-506, 2003.

[6] S. Q. Malik, M. E. Schlarmann, and R. L. Geiger, “A low temperature sensitivity switched-capacitor current reference,” Proceedings of the European Conference on Circuit Theory and Design, pp. 269-272, 2001.

Fig. 3. Transconductance (dashed) and tail current (solid) vs. capacitance C1. Fig. 4. Transconductance (dashed) and tail current (solid) vs. frequency.

TABLE I SIMULATION RESULTS FOR DIFFERENT PROCESS AND TEMPERATURE CORNERS OF THE CONVENTIONAL RESISTOR REFERENCED TECHNIQUE

Gain Bandwidth Product (GHz)

Differential Pair Tail Current (mA) Simulated Corners

Min. Typ. Max.

Percentage Variations of Typical Min. Typ. Max.

Percentage Variations of Typical

Resistors and Capacitors. 0.831 1.148 1.716 77 0.737 0.957 1.367 66 MOSFET, Resistors, and Capacitors. 0.819 1.148 1.736 80 0.739 0.957 1.370 66 Temperature, MOSFET, Resistors, and Capacitors. 0.626 1.148 2.394 153 0.630 0.957 1.689 110

TABLE II SIMULATION RESULTS FOR DIFFERENT PROCESS AND TEMPERATURE CORNERS OF THE PROPOSED TECHNIQUE

Gain Bandwidth Product (GHz)

Differential Pair Tail Current (mA) Simulated Corners

Min. Typ. Max.

Percentage Variations of Typical Min. Typ. Max.

Percentage Variations of Typical

Resistors and Capacitors. 1.163 1.165 1.170 0.6 0.898 0.998 1.098 20 MOSFET, Resistors, and Capacitors. 1.144 1.165 1.198 4.6 0.898 0.998 1.095 19.7 Temperature, MOSFET, Resistors, and Capacitors. 1.01 1.165 1.369 31 0.901 0.998 1.092 19.1

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