Ideas for LLT hardware

Ideas for LLT hardware

Julien Cogan, Régis Lefevre, Patrick Robbe, 10 Apr 2013

2

Introduction

Initial LLT architecture: minimal modifications, reusing as much as possible existing hardware.Will show here the changes and improvements that are envisaged compared to this 1st approach

NEW

NEW

OLD

OLD

OLD

OLD

OLD

3

LLT Calo

4.8 Gbit/s

83 36 3683

Get rid of « all » electronics (TVB and 1.6 Gb transmission) that were using also old ECS(SPECS) and TFC commands.Optimized option with 3 TRIG40 also possible.

Cyril Drancourt

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LLT Calo• Modifications needed on the FE side (which has to be remade for 40

MHz readout)• Add one extra GBT link (80 bits) for the trigger in addition to the 4 links

for DAQ• Format:

– 5b local address of Max ET candidate– 16b data for trigger (candidate Max ET and Sum ET)– 12b BXID– 6b of number of calo cells above a threshold (to replace SPD multiplicity in LLT)– 5b crate ID (for global address computation), under discussion– 4b FEB ID (for global address computation), under discussion– 1b status – 49/80 bits used

• The firmware of the Trigger FPGA (from the old Front-End Board) will have to be slightly modified, in particular to include the multiplicity computation.

Olivier Duarte

5

LLT Calo• Implementation on the TRIG40 side

Output (per side): • Hadron candidate• « Electron » candidate• SumET HCAL• SumET ECAL• Multiplicity ECAL• Multiplicity HCAL

Cyril Drancourt

6

LLT Muon• Scenario for minimal changes on Muon FE side to use GBT to send data:

reduce the number of links by 2, readout + trigger would fit in 5 TELL40 that would do both functionalities.

TELL40 TELL40 TELL40 TELL40 TELL40

4.8 Gbit/s

• Final proposal will be a slightly more complex variation of this scheme, depending on the choices for the Muon upgrade.

Julien Cogan

7

~6 layers

Tracking

VELO

LLTTTRIG40

LLT acceptLLTT tracks

(for HLT and monitoring)

Low Level Track Triggerintegration

• “Copied” from an old muon scheme• Baseline plan is 6 VELO layers - extended plan includes 1-2 UT layers• Important step is to have a detailed status report at the June LLT

workshop showing architecture and performance

LLTT trigger bits

VELO

Giovanni Punzi

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LLTT connections

96 links * 6 layers = 576 links

ATCA backplane

256 engines per region = 49152 engines5 receptors/engine = 245760 receptors

4(?) final decision boards

24 AMC=6 TELL40

24*24 links = 576 links = 3links*192 regions 12 boards in

LLTT crate(+SOL40)

96 96 96 96 96 96

24 24 24 24 24 …

…12 regions/AMC3072 Engines/Stratix12 regions/AMC

3072 Engines/Stratix12 regions/AMC






2048 Engines/Stratix

Switch Logic Might fit inside existing AMCsif not, add up to 6 Tell40

Giovanni Punzi

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« L0DU »

AMC board on the S-ODIN ATCA40 board that will implement the current L0DU functionalities.Firmware to be adapted from current L0DU, and communication protocols to be defined.

Slide from Federico Alessio

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Other news

• TDR end 2013, common with readout board TDR• Emulation of LLT Calo and Muon available in

upgrade simulation software (to be updated to last changes)

• Workshop about LLT to be organized in June to discuss:– Simulation and performance studies– Implementation of the various firmwares– Preparation for TDR

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Conclusions• Ideas to get rid of old hardware with minimal

framework modifications exist for LLT Calo and Muon, and are being refined.

• Imply heavier processing in TRIG40, but possible given the power of these boards.

• Firmwares to be developped for these boards:– LLT Calo:

• LAL Orsay for the trigger part of the Front-End boards• LAPP Annecy for the TRIG40

– LLT Muon: CPPM Marseille– LLT « L0DU »: LPC Clermont

• Feasibility studies of a tracking LLT subsystem are ongoing (Pisa), fitting in the designed LLT framework.

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LLT Muon• Older possibility: no change on the Muon Front-End side,

move L0Muon computation to TELL40 (TRIG40).

TELL40 TELL40

TELL40TELL40

TELL40 TELL40 TELL40

TELL40 TELL40

Documents

Ideas for LLT hardware