Young Won Lim7/16/16

HW / SW Implementation Overview (0A)

Young Won Lim7/16/16

Copyright (c) 2013 - 2016 Young W. Lim.

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HW SW Implementation Overview (0A) 3 Young Won Lim

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HW Implementation

RTL design

Gate netlist

GDS

i0

i1s

sb

a0

a1

zU0

U1

U2

U3

D Q

clk

always @(posedge clk) if (load) q = d;

Logic Synthesis

Physical Synthesismask

ASIC (Application Specific Integrated Circuit)

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NAND Gate

A Transistor Level A Layout

A Wafer processed

A Gate Level

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SW Implementation

C++ / Java Code

Assembly Code

ELF

int i, s=0;for(i=0; i<10; ++i) s+= i;

Compile

Link with libraries

addi $s1, $0, 0add $s0, $0, $0addi $t0, $0, 10...

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OS Kernel

● Process Management

● Multitasking

● Interrupts

● Modes

● Memory Management

● Virtual Memory

● Disk access

● File System

● Device Drivers

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Interrupt

INT

ISR2

SWI

ISR4

SoftwareInterrupt

Instruction

ISR2

ISR4

Hardware Interrupt

Software InterruptUser Mode

Non-user Mode

User Mode

Non-user Mode

Synchronous

Asynchronous

INT 0x80...

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Interrupt and Parallelism

INT

ISR2 ISR2

Hardware InterruptUser Mode

Non-user Mode

Asynchronous

Two parallel threads of execution

Simulate parallelism

Time sharing

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Timer & Interrupt

INT

ISR

Hardware Interrupt

Timer

TMR_Init()

TRG_IncTick()

CheckCallbacks()

void main(void) { TMR_Init(); TRG_Init(); EnableInterrupt();

for ( ; ; );}

callback(data)

TRG_SetTrigger( … );Setting callback function & data

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Multi-tasking

A

● Time Slice● Time Sharing● Round Robin Scheduling● Context Switching

B

C

A

B

C

timer tick interrupt

Task A Thread

Task B Thread

Task C Thread

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GPIO

D Q

D Q

● write to port address

● read from port address

● write to port direction register

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HW (ASIC) & SW Implementations

RTL design

Gate netlist

GDS

Logic Synthesis

Physical Synthesis

C++ / Java Code

Assembly Code

ELF

Compile

Link with libraries

Parallelism is ensured by spatial allotment in a chip

Parallelism is ensured by temporal processing on a processor

HW (ASIC) SW

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FPGA Architecture

A Logic Block

A Configurable Interconnection

FPGA (Field Programmable Gate Array)

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1

0

1

0

0

0

0

1

Implementing Boolean Functions

0 1 1

0 1 0

0 0 1

0 0 0

1 1 1

1 1 0

1 0 1

1 0 0

inputs output

x y z

3

2

0

1

7

6

4

5

index

F

1

0

1

0

0

0

0

1

Size : 23 x 1

address3bits

Data 1 bit

LUT (Look up table)

A Logic Block

Memory

A Truth Table

Combinational Logic

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Configuring Logic Blocks

A Logic Block

select

LUT SRAM cells

An 2-bit SRAM cell

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Configuring Interconnections

An 1-bit SRAM cell

An 1-bit SRAM cell

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HW (FPGA) Implementations

RTL design

Gate netlist *

“Programming File”

Logic Synthesis

Physical Synthesis

FPGA configuration information

HW (FPGA)

select

LUT SRAM cells

An 2-bit SRAM cell

An 1-bit SRAM cell An 1-bit SRAM cell

LUTs, FF, etc

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HW (FPGA) & SW Implementations

RTL design

Gate netlist

“Programming File”

Logic Synthesis

Physical Synthesis

FPGA configuration information

HW (FPGA)

C++ / Java Code

Assembly Code

ELF

Compile

Link with libraries

SW

Machine Instructions of a processor

0100101...FPGA configuration information

10111011...

Young Won Lim7/16/16

References

[1] http://en.wikipedia.org/[2] D.M. Harris, S. L. Harris, “Digital Design and Computer Architecture”