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How Do I Plan to Power My FPGA?

Xilinx Training

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Objectives

After completing this module, you will be able to:

Explain how static power is different from dynamic power

Describe the impact a smaller device geometry has on static

power consumption

Define the relationship between leakage current and junction

temperature

Describe some of the device data sheet information that pertains

to power consumption

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Total Power = Static + Dynamic

Once the device has powered up, there are two maincomponents to power consumption

Static power

Primarily transistor leakage current

Source to Drain leakage IS D Gate to substrate leakage IGATE

Some current from special circuits (DCM, etc)

Dynamic power

Switching in the FPGA core and I/O

Determined by CV2f node capacitance,

supply voltage

switching frequency

source drain

gate

IGATE

IS

D

Buf Buf

C

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The Industry Trend in Leakage Current

New Technologies Smallertransistor length Higher IS D

Faster transistors (lower Vt )Smaller Gate Oxide thicknessHigher (IGATE)

The total leakage for alltransistors in the device

ICCINTQ = IS D + IGATE

Even when the device is notdoing a task it still draws somepower

This leads to the development ofnew features such as Suspend andHibernate mode

Smaller process geometrieslead to higher static power

Low

VT

Regular VT

220 180 150 130 90 75 650.1

1

10

100

100

0

Transistor Ileakage

Trend

Ileakage

(nA/um)

Technology Node

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Properties of Leakage Current

Junction Temp

C

LeakageCurrent

0 20 40 60 80 100 120 140-20-40

25 C

50 C

85 C

100 C

ICCINTQJunctionTemperature

(TJC)

Normalized

ICCINTQTypical

25 1.00

50 1.46

85 2.50

100 3.14

Leakage current increases dramatically with Junction

Temperature

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Data Sheet Specifications

Iccintq, Iccoq, Iccauxq These are the bare minimum currents (quiescent) required for

your power supply to operate the device Does not guarantee that your design is going to work, just that

this is the minimum current

Dynamic power requirements will increase the requiredcurrent during operation

Refer to the Spartan-6 FPGA Data Sheet or the Virtex-6FPGA Data Sheet

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Data Sheet Specifications

Power-On requirements are greater than the operating

current requirements These are the bare minimum currents (quiescent) required for

your power supply to power up the device This is used for picking out a sufficient power supply

Does not guarantee that your design is going to work, just thatthe device will configure

Refer to the Spartan-6 FPGA Data Sheet or the Virtex-6FPGA Data Sheet

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Design-Dependent Power

It is up to the user to plan on how much current their systemcan use This is dependent on the design, FPGA, and other devices used in

your system

It is also up to you to anticipate how much your worst case

power consumption might be Xilinx provides descriptions of the current draw your

FPGA might have at power-up, during minimal operation,but not for worst-case conditions Too much is design dependent (resources used, clock

frequency, etc.)

To get the best power estimate we offer a couple of powerestimation tools Please refer to the Power Estimation Video for more information

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Estimating Power Consumption

Power calculations can be performed at three distinct phases of

the design cycle

Concept phase: A rough estimate of power can be calculated based on

estimates of logic capacity and activity rates

Use the Xilinx Power Estimator spreadsheet Design phase: Power can be calculated more accurately based on detailed

information about how the design is implemented in the FPGA

Use the XPower Analyzer

System Integration phase: Power is calculated in a lab environment

Use actual instrumentation

Accurate power calculation at an early stage in the design cycle

will result in fewer problems later

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Summary

Static power is dependent on the transistor leakage current

Dynamic power is dependent on the switching of the logic in the

CLB array and IOB resources

Smaller device geometry increases the static power consumption

of all devices

Newer devices have a higher static power consumption

An increase in junction temperature dramatically increases the

leakage current and your static power

The minimum current required to operate and configure theFPGA is provided in your FPGAs data sheet

But the best way to estimate your power consumption is with either the

Xilinx Power Estimator spreadsheet or the XPower Analyzer utility

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Where Can I Learn More?

Xilinx online documents

www.support.xilinx.com

Spartan-6 FPGA Power Management User Guide, UG394

Introduces the Suspend and Hibernate modes

Describes the necessary voltage supplies

Introduces the low-power (-1L) devices

Describes the Power-On and Power-Down behavior

Power Estimation options are discussed

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Where Can I Learn More?

Xilinx Education Services courseswww.xilinx.com/training

Designing with Spartan-6 and Virtex-6 Device Families course

How to get the most out of both device families

How to build the best HDL code for your FPGA design

How to optimize your design for Spartan-6 and/or Virtex-6

How to take advantage of the newest device features

Free Video Based Training How Do I Plan to Power My FPGA?

Power Estimation

What are the Spartan-6 Power Management Features?

What are the Virtex-6 Power Management Features?

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