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1 PL136/MAPLD 2004 Rollins Evaluation of Power Costs in Triplicated FPGA Designs Nathan Rollins 1 , Michael J. Wirthlin 1 , and Paul Graham 2 Department of Electrical and Computer Engineering Brigham Young University Provo, UT Los Alamos National Laboratory Los Alamos, NM This work was supported by Los Alamos National Laboratory, U.S. Department of Energy (LA-UR #04-5285) 2 1

Evaluation of Power Costs in Triplicated FPGA Designs

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Evaluation of Power Costs in Triplicated FPGA Designs. Nathan Rollins 1 , Michael J. Wirthlin 1 , and Paul Graham 2. 1. 2. Department of Electrical and Computer Engineering Brigham Young University Provo, UT. Los Alamos National Laboratory Los Alamos, NM. - PowerPoint PPT Presentation

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Page 1: Evaluation of Power Costs in Triplicated FPGA Designs

1 PL136/MAPLD 2004Rollins

Evaluation of Power Costs in Triplicated FPGA Designs

Nathan Rollins1, Michael J. Wirthlin1,

and Paul Graham2

Department of Electrical andComputer EngineeringBrigham Young UniversityProvo, UT

Los Alamos National LaboratoryLos Alamos, NM

This work was supported by Los Alamos National Laboratory, U.S. Department of Energy (LA-UR #04-5285)

21

Page 2: Evaluation of Power Costs in Triplicated FPGA Designs

2 PL136/MAPLD 2004Rollins

Single-Event Effects of SRAM FPGAs

• Static memory sensitive to single-event upsets (SEU)

• Large amount of static memory in FPGAs

– Configuration memory

– User memory and flip-flops

• Upsets within the configuration memory may modify the behavior of the design– Internal Logic and Interconnect

– Global clocking and configuration modes

– Operation of Input/Output pads

• Design redundancy necessary for proper operation

Page 3: Evaluation of Power Costs in Triplicated FPGA Designs

3 PL136/MAPLD 2004Rollins

SEU Mitigation Through TMR

• Triple Modular Redundancy (TMR)– Triplicate circuit of interest– Vote on circuit output (majority voter)

• TMR masks all single failures in design

Design

Design

Design

Voter

Page 4: Evaluation of Power Costs in Triplicated FPGA Designs

4 PL136/MAPLD 2004Rollins

Area and Speed Costs of TMR

• Bulletproof design is possible with 3-voter TMR or feedback TMR and triplicated clocks

Design

Design

Design

VoterOBUF

Voter

Voter

OBUF

OBUF

BUFG

BUFG

BUFG

•Area Cost: 3x – 6x •Speed Cost: up to 50% slower

Page 5: Evaluation of Power Costs in Triplicated FPGA Designs

5 PL136/MAPLD 2004Rollins

Power Costs of TMR

• FPGAs consume relatively more power than ASICs

• TMR may cause a triplication of an already large power consumption

• Goal: Investigate the cost of TMR in terms of power consumption

Page 6: Evaluation of Power Costs in Triplicated FPGA Designs

6 PL136/MAPLD 2004Rollins

Power Analysis Tools

• Xilinx’s XPower tool– Estimates power consumption

• JPower tool– Measures power consumption

• JPower power measurement tool can be used to validate XPower power estimation tool

Page 7: Evaluation of Power Costs in Triplicated FPGA Designs

7 PL136/MAPLD 2004Rollins

XPower

• Xilinx power measurement tool

• Requires:– *.ncd and *.pcf files or *.par.ncd file– Activity rates for EVERY net in the design

• 3 ways to assign net activity rates:– Manually in the XPower tool (GOOD LUCK!)

– Import *.xml file

– Import *.vcd or *.xad files

Page 8: Evaluation of Power Costs in Triplicated FPGA Designs

8 PL136/MAPLD 2004Rollins

XPower

• Importing *.xml files:– XPower creates XML files as a way of saving session

settings – why not create them ourselves ?

– JHDL used to get activity rates

– 100% nets assigned activity rate• XPower reports “accurate” confidence level

– JHDL cannot simulate glitches• This method underestimates true power consumption

Page 9: Evaluation of Power Costs in Triplicated FPGA Designs

9 PL136/MAPLD 2004Rollins

XPower

• Importing *.vcd files:– Use back-annotation (ngd2vhdl) & ModelSim

to create *.vcd files– Accurate timing information available (*.sdf

file) provides most accurate results

Page 10: Evaluation of Power Costs in Triplicated FPGA Designs

10 PL136/MAPLD 2004Rollins

JPower

• Tool to measure total current on SLAAC1V board (in mA)

• Measurement functions added to SLAAC1V C API by LANL - summer 2003

• Tool named after LANL intern Jason Zimmerman

Page 11: Evaluation of Power Costs in Triplicated FPGA Designs

11 PL136/MAPLD 2004Rollins

JPower

• Current Measurments:– 2.5V channel sampled at 120 kHz– Current stored in a register as a 10-bit number

• Value in register multiplied by 4.8828125 mA and rounded to the nearest mA

• Max current reading: 4990mA

• Averaged current measurements are repeatable to within a few mA

Page 12: Evaluation of Power Costs in Triplicated FPGA Designs

12 PL136/MAPLD 2004Rollins

Calibrating JPower and XPower

• Blank Design – run JPower with no designs on SLAAC1V board (default X0 design)– Run JPower tool with and without clock

running at frequencies from 10MHz – 100MHz– Results from this blank design provides an

equation which allows us to isolate the power measurements to a single FPGA on the SLAAC1V board

Page 13: Evaluation of Power Costs in Triplicated FPGA Designs

13 PL136/MAPLD 2004Rollins

Test Calibration

• Four 8-bit Designs (non-TMR & TMR):– Incrementer

• 72 incrementers – each output to IOBs

– XOR’ed Incrementer• 416 incrementers – groups of outputs XOR’ed

– Up/Down Loadable Counter• 416 counters – final counter bits output to IOBs

– 3 CLK Implementations of above designs

Page 14: Evaluation of Power Costs in Triplicated FPGA Designs

14 PL136/MAPLD 2004Rollins

Calibration Results

3-CLK Auto-Placed

0100020003000400050006000700080009000

10000

0 20 40 60 80

Freq (Mhz)

Pow

er (m

W)

XPower INCR

J Power INCR

XPower XOR

J Power XOR

XPower CNT

J Power CNT

Incrementer Auto-Placed

0

200

400

600

800

1000

1200

1400

0 20 40 60 80

Freq (Mhz)

Pow

er (m

W)

XPower No-TM R

J Power No-TM R

XPower TM R

J Power TM R

XOR Incrementer Auto-P laced

0

1000

2000

3000

4000

5000

6000

0 20 40 60 80

Freq (Mhz)

Pow

er (m

W) XPower No-TM R

J Power No-TM R

XPower TM R

J Power TM R

Counter Auto-Placed

0100020003000400050006000700080009000

0 20 40 60 80

Freq (Mhz)

Pow

er (m

W) XPower No-TM R

J Power No-TM R

XPower TM R

J Power TM R

Page 15: Evaluation of Power Costs in Triplicated FPGA Designs

15 PL136/MAPLD 2004Rollins

Calibration Results

• “Close” match between JPower & XPower for non-TMR designs and for TMR designs with triplicated clock

• Large slope difference in counter TMR design

Non - TMR TMR 3 CLK (TMR)

INC XOR CNT INC XOR CNT INC XOR CNT

Frequency vs. Power Slopes

JPower 1.54 7.85 11.08 7.37 31.13 47.53 5.37 30.67 48.14

XPower 1.54 7.95 9.26 5.23 27.06 39.03 5.28 30.62 49.94

Area Costs

LUTs 576 3250 3328 1728 9750 19968 1728 9750 19968

Page 16: Evaluation of Power Costs in Triplicated FPGA Designs

16 PL136/MAPLD 2004Rollins

TMR Power Studies

• Effects of design placement on power consumption

• Power costs of realistic designs– Hitachi 8-bit CPU– QPSK demodulator

• Power costs of different Xilinx architectures

Page 17: Evaluation of Power Costs in Triplicated FPGA Designs

17 PL136/MAPLD 2004Rollins

Effects of Design Placement on Power Consumption

• Incrementer TMR design used to test effects of placement on power– 3 different placements used:

Placement 1 Placement 2 Placement 3

Cnt0-0 Cnt0-1 Cnt0-2

Cnt1-0 Cnt1-1 Cnt1-2

Cnt2-0 Cnt2-1 Cnt2-2

……

…

Cnt0-0 Cnt1-0 Cnt2-0 …Cnt0-0 Cnt0-1 Cnt0-2

Cnt1-0 Cnt1-1 Cnt1-2

Cnt2-0 Cnt2-1 Cnt2-2

…

…

…

……

…

…

Page 18: Evaluation of Power Costs in Triplicated FPGA Designs

18 PL136/MAPLD 2004Rollins

Effects of Placement

• Comparison of frequency vs. power slopes for auto-placed and hand-placed designs shows the effects of placement

• “JP/XP” row ratio indicates how closely JPower and XPower match

Incrementer XOR Incrementer Up/Down Counter

Auto-Place Hand-Place Auto-Place Hand-Place Auto-Place Hand-Place

Frequency vs. Power Slopes

JPower 7.37 4.78 31.13 22.18 47.53 41.22

XPower 5.23 4.76 27.06 25.10 39.03 36.40

JP / XP 1.41 1.00 1.15 0.88 1.22 1.13

Page 19: Evaluation of Power Costs in Triplicated FPGA Designs

19 PL136/MAPLD 2004Rollins

Effects of Placement

• JPower is much more sensitive to placement than Xpower

• JPower and XPower closest with placement 3 (optimized hand-placement)

Auto-Place Place 1 Place 2 Place 3

Frequency vs. power slopes (TMR)

JPower 7.37 10.65 6.15 4.76

XPower 5.23 6.20 5.21 4.78

Power increase due to TMR (TMR / non-TMR)

JPower 4.79x 7.04x 4.06x 3.15x

XPower 3.40x 4.04x 3.39x 3.10x

Page 20: Evaluation of Power Costs in Triplicated FPGA Designs

20 PL136/MAPLD 2004Rollins

Realistic Designs: Area and Speed Costs

QPSK Demodulator

Hitachi CPU

VirtexTMR Area Cost 3.03x 3.01x

TMR Speed Cost 95.2 % 71.1 %

Virtex2TMR Area Cost 3.03x 3.00x

TMR Speed Cost 84.6 % 100.0 %

Virtex2ProTMR Area Cost 3.03x 3.00x

TMR Speed Cost 77.9 % 80.8 %

Spartan 3TMR Area Cost 3.02x 3.00x

TMR Speed Cost 97.2% 87.0 %

Area and speed costs due to TMR

Page 21: Evaluation of Power Costs in Triplicated FPGA Designs

21 PL136/MAPLD 2004Rollins

Realistic Designs: Power CostsQPSK TMR

0

2000

4000

6000

8000

10000

12000

0 20 40 60 80

Freq (MHz)

Pow

er (m

W) Virtex

Virtex2

Virtex2Pro

Spartan3

J Power

Hitachi CPU TMR

050

100150200250300350400450

0 20 40 60

Freq (Mhz)

Pow

er (m

W) Virtex

Virtex2

Virtex2Pro

Spartan3

J Power

QPSK Non-TMR

0

500

1000

1500

2000

2500

3000

3500

0 20 40 60 80

Freq (Mhz)

Pow

er (m

W) Virtex

Virtex2

Virtex2Pro

Spartan3

J Power

Hitachi CPU Non-TMR

0

50

100

150

200

250

300

350

400

0 20 40 60 80

Freq (Mhz)

Pow

er (m

W) Virtex

Virtex2

Virtex2Pro

Spartan3

J Power

Page 22: Evaluation of Power Costs in Triplicated FPGA Designs

22 PL136/MAPLD 2004Rollins

Realistic Designs: Power Costs

Non - TMR TMRJPower Virtex Virtex2 Virtex2Pro Spartan3 JPower Virtex Virtex2 Virtex2Pro Spartan3

Dynamic

Power (mW)

QPSK 40.50 45.71 8.60 8.16 1.97 93.75 150.64 30.17 24.98 6.68

Hitachi 2.06 2.34 0.79 0.48 0.12 5.48 7.30 2.10 1.39 0.30

Static

Power (mW)

QPSK 28.57 22.14 150 336.86 179.83 26.43 37.86 139.5 334.71 182.23

Hitachi 27.17 26.43 150 337.07 180.00 28.25 27.50 150 337.50 180.34

JPower Virtex Virtex2 Virtex2Pro Spartan3

Dynamic Power Increase Due to TMR (TMR / non-TMR)

QPSK 2.53x 3.30x 3.51x 3.06x 3.39x

Hitachi 2.66x 3.12x 2.66x 2.88x 2.50x

NOTE: JPower measures power on Virtex parts only

Page 23: Evaluation of Power Costs in Triplicated FPGA Designs

23 PL136/MAPLD 2004Rollins

Power Study Results

• Power consumption increase due to TMR: ~3x– Poor design mapping can cause higher power

consumption

• Static power can be a significant contribution to total power consumption

• FPGA architecture is significant in determining power consumption


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