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TUTORIAL MY FIRST FPGA DESIGN Tristan Gingold - [email protected] - FOSDEM’18

TUTORIAL MY FIRST FPGA DESIGN - FOSDEMTUTORIAL MY FIRST FPGA DESIGN Tristan Gingold - [email protected] - FOSDEM’18. ... see gnucap, qucs, spice… (There are always analog parts

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  • TUTORIALMY FIRST FPGA DESIGNTristan Gingold - [email protected] - FOSDEM’18

    mailto:[email protected]

  • IT’S A TALK ABOUT HARDWARE!

    Things likethat…

    There are many talksat FOSDEM about software.Try a different room

  • IT’S A TALK ABOUTCHIP DESIGN

    • This

    This

    This is a PCB(Printed Circuit Board)KiCad is a tool to design boards, you also need electronic knowledge

  • MORE SPECIFICALLY,DIGITAL CHIPS

    Analog chipDigital

    chip

    See the difference ?

  • DESIGNING AN IC IS COMPLEX…

    Netlist

    Power Route

    Place

    Layout

    Cells

    X-talk

    Clock domains DRC

    Timing

    DFT

    LVS

    STA

    MasksDouble patterning

    SCE

    There aren’t many OSStools for ASICs.qflowmagic VLSI

  • … AND VERY EXPENSIVE

    ASML lithography machineExpect $$$ for the first chip…

  • BUT SOME ARE PROGRAMMABLE!

    Normal chip FPGAThere are other kinds ofprogrammable circuits:Gate arrayCPLD…

  • FPGA ARCHITECTURE

    Programmable pad:DirectionStrengthLevel…

    Programmable logic (LUT)

    Programmable switch box

    That’s a very simple view…Most FPGAs also have PLL, memories, multipliers, or even SERDES/PCI-e blocks.See FPGA databooks

  • DIGITAL IS ABOUT 0 AND 1That’s simple !Assuming youknow aboutbinary computation

    For analog design,see gnucap, qucs, spice…

    (There are alwaysanalog parts in acircuit)

  • DIGITAL IS ABOUT LOGICBASIC OPERATIONS

    bbc.co.uk

    InputsInputsInputs

    NOT gateD = ~A OR gateZ = D | E

    Output

    AND gateD = B & C

    http://bbc.co.uk

  • COMBINE THEM!

    Q = A ^ B

    Symbol for XOR gate

    wikipedia.org

    http://wikipedia.org

  • OR DO MATH (ONE BIT)

    Q = A ^ B = A + B = A ~= B

    wikipedia.org

    A B Q0 0 00 1 11 0 11 1 0

    http://wikipedia.org

  • THE ADDER

    S : SUMC : CARRY

    wikipedia.org

    Full Adder

    http://wikipedia.org

  • MULTIPLE BIT ADDER

    S = A + B

    There are more efficient way to design large addersSearch for Digital Logic Architecture

  • IF YOU CAN ADD,YOU CAN MULTIPLY!

    A3

    0 0 0 0 B0

    0

    A2 A1 A0

    A3B1

    0

    A2 A1 A0

    A3B2

    0

    A2 A1 A0

    A3B3

    0

    A2 A1 A0

    P0P1P2P3P4P5P6P7

    P = A * B

    There are more efficient wayto design multipliers

  • YOU CAN DESIGNANY LOGICAL/ARITH FUNCTION

    F()

    Inputs

    Outputs

    Well, many functions…But this is not very efficient (can take a lot of gates)

  • MORE POWERFUL:RECURSION!

    F()

    Inputs

    Outputs

    In math,recursion is very powerful.

    In digital design,it doesn’t work directly!

  • TIMINGSYNCHRONISATION

    wikipedia.org

    Do you remember the full adder ?

    It takes time for a signal to propagate through gates.(due to capacities).So the arrival times at S and Cout differ.

    http://wikipedia.org

  • TIMING DIAGRAM

    +1

    What you expect:

    What you get:

    Outputs are not available at the same time.Thanks to http://wavedrom.com/editor.html

    http://wavedrom.com/editor.html

  • SYNCHRONOUS DESIGNYou can try to balance paths, but:•It’s very hard•propagation time depends on too many factors

    You can use a logic that is not affected by delay variation(like gray code), but:•works only in some cases.

    Rule #1:no direct loop/feedback

    So how to do ?

  • SYNCHRONOUS DESIGN

    +1

    clk

    Flip Flop: update output on rising edge of the clock

    Clock

    AB

    Clean

  • DIGITAL DESIGNIt’s a mix of:•logic gates•flip flops

    It is possible to use schematic editors, but•tedious•doesn’t scale well

    Use an HDLHardware Description LanguageI will use VHDL

    There are other way to synchronise(latch, falling edge, double edge…)

  • MY FIRST DESIGNBLINKING LEDS

    latticesemi.com

    Using OSS tools:•ghdl•yosys•arachne-pnr•iceStorm

    Target: Lattice iCEstick~ 22 eurosSupported by OSS tools

    Leds

    http://latticesemi.com

  • VHDL: EXTERNAL INTERFACEboilerplate

    Comment(to not forget leds position)

    Input: clock(externally generated 3Mhz)

    outputs: leds

    interface

  • INTERNALSInternalsInternal

    wire

    Process:concurrent execution,triggered on clk

    concurrent assignments

    There are many VHDL or Verilog tutorials on the web.

  • SYNTHESISTranslating (or compiling) sources to gates (netlist)

    First, analysing sources:

    Synthesis: output fileunit name

    synthesis script

    frontend command

  • PLACE & ROUTEAllocate resources on the FPGA

    device input

    output place file

    IC pin #

  • PROGRAMWrite into the FPGA

    flashUSB interface

    Create the binary file:

    Write to flash:

    The FPGA is automatically reset and then load the new config

  • TOOLS USEDSynthesis:http://www.clifford.at/yosys/

    VHDL front-end:https://github.com/tgingold/ghdlsynth-betahttps://github.com/tgingold/ghdl

    Place and route:https://github.com/cseed/arachne-pnr

    iCE40 tools:http://www.clifford.at/icestorm/

    http://www.clifford.at/yosys/https://github.com/tgingold/ghdlsynth-betahttps://github.com/tgingold/ghdlhttps://github.com/cseed/arachne-pnrhttp://www.clifford.at/icestorm/

  • QUESTIONS ?


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