High-Speed, Step-Down Controller with Accurate Current ... · BATTERY 4.5V TO 28V OUTPUT 2.5V SHDN ILIM DL LX V+ BST DH CS OUT SKIP VDD MAX8764 UVP REF PGOOD LATCH OVP FB GND Minimal

General DescriptionThe MAX8764 pulse-width modulation (PWM) controllerprovides high efficiency, excellent transient response,and high-DC output accuracy needed for steppingdown high-voltage batteries to generate low-voltageCPU core or chipset/RAM supplies in notebook com-puters.

Maxim’s proprietary Quick-PWM™ quick-response,constant-on-time PWM control scheme handles wideinput/output voltage ratios with ease and provides100ns “instant-on” response to load transients whilemaintaining a relatively constant switching frequency.Efficiency is enhanced by an ability to drive very largesynchronous-rectifier MOSFETs. Accurate current sens-ing to ensure reliable overload protection is availableusing an external current-sense resistor in series withthe synchronous rectifier. Alternatively, the synchronousrectifier itself can be used for less-accurate currentsensing at the lowest possible power dissipation. Ahigh-output impedance in shutdown eliminates nega-tive output voltages, saving the cost of a Schottky diodeon the output.

Single-stage buck conversion allows the MAX8764 todirectly step down high-voltage batteries for the highestpossible efficiency. Alternatively, two-stage conversion(stepping down the 5V system supply instead of thebattery) at a higher switching frequency allows the mini-mum possible physical size.

The MAX8764 is intended for CPU core, chipset,DRAM, or other low-voltage supplies as low as 1V. It isavailable in 20-pin QSOP and thin QFN packages andincludes both adjustable overvoltage and undervoltageprotection.

For a dual step-down PWM controller with accurate cur-rent limit, refer to the MAX8743 data sheet. TheMAX1714/MAX1715 single/dual PWM controllers aresimilar to the MAX8764, but do not use current-senseresistors.

ApplicationsNotebook Computers

CPU Core Supplies

Chipset/RAM Supplies as Low as 1V

1.8V and 2.5V Supplies

Features♦ Ultrahigh Efficiency

♦ Accurate Current-Limit Option

♦ Quick-PWM with 100ns Load-Step Response

♦ 1% VOUT Accuracy Over Line and Load

♦ 1.8V/2.5V Fixed or 1V to 5.5V Adjustable OutputRange

♦ 2V to 28V Battery Input Range

♦ 200/300/450/600kHz Switching Frequency

♦ Adjustable Overvoltage Protection

♦ Adjustable Undervoltage Protection

♦ 1.7ms Digital Soft-Start

♦ Drives Large Synchronous-Rectifier FETs

♦ 2V ±1% Reference Output

♦ Power-Good Window Comparator

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High-Speed, Step-Down Controller with Accurate Current Limit for Notebook Computers

________________________________________________________________ Maxim Integrated Products 1

19-3626; Rev 0; 3/05

Pin Configurations appear at end of data sheet.

Quick-PWM is a trademark of Maxim Integrated Products, Inc.

VCC

5V INPUT

BATTERY 4.5V TO 28V

OUTPUT2.5V

SHDN

ILIM

DL

LX

V+

BST

DH

CS

OUT

SKIP

VDD

MAX8764

UVP

REF

PGOOD

LATCH

OVP

FB

GND

Minimal Operating Circuit

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering InformationPART TEMP RANGE PIN-PACKAGE

MAX8764EEP -40°C to +85°C 20 QSOP

MAX8764EEP+ -40°C to +85°C 20 QSOP

MAX8764ETP -40°C to +85°C 20 Thin QFN

MAX8764ETP+ -40°C to +85°C 20 Thin QFN

+Denotes lead-free package.

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ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

V+ to GND..............................................................-0.3V to +28VVCC, VDD to GND .....................................................-0.3V to +6VOUT, PGOOD, SHDN to GND..................................-0.3V to +6VFB, ILIM, LATCH, OVP, REF, SKIP,

TON, UVP to GND ..................................-0.3V to (VCC + 0.3V)BST to GND............................................................-0.3V to +34VCS to GND.................................................................-6V to +30VDL to GND..................................................-0.3V to (VDD + 0.3V)DH to LX .....................................................-0.3V to (BST + 0.3V)LX to BST..................................................................-6V to +0.3V

REF Short Circuit to GND...........................................ContinuousContinuous Power Dissipation (TA = +70°C)

20-Pin QSOP (derate 9.1mW/°C above +70°C)...........727mW20-Pin 5mm x 5mm Thin QFN (derate 20.0mW/°C above +70°C).................................................................1.60W

Operating Temperature Range ...........................-40°C to +85°CJunction Temperature ......................................................+150°CStorage Temperature Range .............................-65°C to +150°CLead Temperature (soldering, 10s) .................................+300°C

ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V+ = 15V, VCC = VDD = 5V, SKIP = LATCH = GND, TA = 0°C to +85°C, unless otherwise noted. Typical valuesare at TA = +25°C.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Battery voltage, V+ 2 28 Input Voltage Range VCC , VDD 4.5 5.5

V

FB = OUT 0.99 1.01

FB = GND 2.475 2.5 2.525 Error Comparator Threshold (DC Output Voltage Accuracy) (Note 1)

V+ = 4.5V to 28V, SKIP = VCC FB = VCC 1.782 1.8 1.818

V

Load Regulation Error ILOAD = 0 to 3A, SKIP = VCC 9 mV

Line Regulation Error VCC = 4.5V to 5.5V, V+ = 4.5V to 28V 5 mV

FB Input Bias Current -0.1 +0.1 µA

Output Adjustment Range 1.0 5.5 V FB = GND 90 190 350 OUT Input Resistance FB = VCC or adjustable feedback mode 70 145 270

kΩ

Soft-Start Ramp Time Rising edge of SHDN to full current limit 1.7 ms

TON = GND (600kHz) 140 160 180

TON = REF (450kHz) 175 200 225

TON = unconnected (300kHz) 260 290 320 On-Time

V+ = 24V, VOUT = 2V (Note 2)

TON = VCC (200kHz) 380 425 470

ns

Minimum Off-Time (Note 2) 400 500 ns

Quiescent Supply Current (VCC) FB forced above the regulation point 550 800 µA

Quiescent Supply Current (VDD) FB forced above the regulation point <1 5 µA

Quiescent Supply Current (V+) 25 40 µA

Shutdown Supply Current (VCC) SHDN = GND <1 5 µA

Shutdown Supply Current (VDD) SHDN = GND <1 5 µA

Shutdown Supply Current (V+) SHDN = GND, V+ = 28V, VCC = VDD = 0 or 5V <1 5 µA

Reference Voltage VCC = 4.5V to 5.5V, no external REF load 1.98 2.00 2.02 V Reference Load Regulation IREF = 0 to 50µA 0.01 V

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ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC = VDD = 5V, SKIP = LATCH = GND, TA = 0°C to +85°C, unless otherwise noted. Typical valuesare at TA = +25°C.)


REF Sink Current REF in regulation 10 µA

REF Fault Lockout Voltage Falling edge, hysteresis = 40mV 1.6 V Overvoltage Trip Threshold (Fixed-Threshold Mode)

With respect to error comparator threshold, no load OVP = GND, rising edge, hysteresis = 1%

12 14.5 17 %

External feedback, measured at FB with respect toVOVP, 1V < VOVP < 1.8V, rising edge, hysteresis =1%

-30 +30 mV

Overvoltage Comparator Offset (Adjustable-Threshold Mode) Internal feedback, measured at OUT with respect to the

nominal OUT regulation voltage, 1V < VOVP < 1.8V,rising edge, hysteresis = 1%

-3.5 +3.5 %

OVP Input Leakage Current 1V < VOVP < 1.8V -100 0 +100 nA

Overvoltage FaultPropagation Delay

FB forced 2% above trip threshold 1.5 µs

Output Undervoltage ProtectionTrip Threshold (Fixed-ThresholdMode)

With respect to error comparator threshold, UVP = VCC 65 70 75 %

External feedback, measured at FB with respect toVUVP, 0.4V < VUVP < 1V

-40 +40 mV Output Undervoltage ProtectionTrip Threshold (Adjustable-Threshold Mode) Internal feedback, measured at OUT with respect to the

nominal OUT regulation voltage, 0.4V < VUVP < 1V -5 +5 %

UVP Input Leakage Current 0.4V < VUVP < 1V -100 <1 +100 nA

Output Undervoltage ProtectionBlanking Time

From rising edge of SHDN 10 30 ms

PGOOD Trip Threshold (Lower) With respect to error comparator threshold, no load -12.5 -10 -8.0 % PGOOD Trip Threshold (Upper) With respect to error comparator threshold, no load 8.0 10 12.5 % PGOOD Propagation Delay FB forced 2% beyond PGOOD trip threshold, falling 10 µs

PGOOD Output Low Voltage ISINK = 1mA 0.4 V PGOOD Leakage Current High state, forced to 5.5V 1 µA

ILIM Adjustment Range 0.25 3.00 V Current-Limit Threshold (Fixed) GND - VCS, ILIM = VCC 90 100 110 mV

VILIM = 0.5V 40 50 60 Current-Limit Threshold(Adjustable)

GND - VCS VILIM = 2V 170 200 230 mV

Current-Limit Threshold(Negative Direction)

GND - VCS, SKIP = VCC, ILIM = VCC, TA = +25°C -140 -117 -95 mV

Current-Limit Threshold(Zero Crossing)

GND - VCS, SKIP = GND 3 mV

Thermal Shutdown Threshold Hysteresis = 10°C +150 °C VCC UndervoltageLockout Threshold

Rising edge, hysteresis = 20mV, PWM disabled below this level

4.1 4.4 V

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ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC = VDD = 5V, SKIP = LATCH = GND, TA = 0°C to +85°C, unless otherwise noted. Typical valuesare at TA = +25°C.)


MAX8764EEP 1.5 5 DH Gate-Driver On-Resistance BST - LX forced to 5V(Note 4) MAX8764ETP 1.5 6

Ω

MAX8764EEP 1.5 5 DL Gate-Driver On-Resistance DL, high state(Note 4) MAX8764ETP 1.5 6 Ω

MAX8764EEP 0.5 1.7 DL Gate-Driver On-Resistance DL, low state(Note 4) MAX8764ETP 0.5 2.7

Ω

DH Gate-Driver Source/SinkCurrent

DH forced to 2.5V, BST-LX forced to 5V 1 A

DL Gate-Driver Source Current DL forced to 2.5V 1 A DL Gate-Driver Sink Current DL forced to 5V 3 A

DL rising 35 Dead Time DH rising 26 ns

Logic Input High Voltage LATCH, SHDN, SKIP 2.4 V Logic Input Low Voltage LATCH, SHDN, SKIP 0.8 V Logic Input Current LATCH, SHDN, SKIP -1 +1 µA

Dual Mode™ Threshold, Low OVP, UVP, FB 0.15 0.20 0.25 V OVP, UVP VCC - 1.5 VCC - 0.4 Dual Mode Threshold, High FB 1.9 2.0 2.1

V

TON VCC Level VCC - 0.4 V TON Float Voltage 3.15 3.85 V TON Reference Level 1.65 2.35 V TON GND Level 0.5 V TON Input Current Forced to GND or VCC -3 +3 µA

ILIM Input Leakage Current -100 0 +100 nA


Battery voltage, V+ 2 28 Input Voltage Range VCC , VDD 4.5 5.5

V

FB = OUT 0.985 1.015

FB = GND 2.462 2.538 Error Comparator Threshold (DC Output Voltage Accuracy)

V+ = 4.5V to 28V, SKIP = VCC (Note 1) FB = VCC 1.773 1.827

V

TON = GND (600kHz) 140 180

TON = REF (450kHz) 175 225

TON = Unconnected (300kHz) 260 320 On-Time

V+ = 24V, VOUT = 2V (Note 2)

TON = VCC (200kHz) 380 470

ns

ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V+ = 15V, VCC = VDD = 5V, SKIP = LATCH = GND, TA = -40°C to +85°C, unless otherwise noted.) (Note 3)

Dual Mode is a trademark of Maxim Integrated Products, Inc.

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Minimum Off-Time (Note 2) 500 ns

Quiescent Supply Current (VCC) FB forced above the regulation point 800 µA

Quiescent Supply Current (VDD) FB forced above the regulation point 5 µA

Quiescent Supply Current (V+) Measured at V+ 40 µA

Shutdown Supply Current (VCC) SHDN = GND 5 µA

Shutdown Supply Current (VDD) SHDN = GND 5 µA

Shutdown Supply Current (V+) SHDN = GND, V+ = 28V, VCC = VDD = 0 or 5V 5 µA

Reference Voltage VCC = 4.5V to 5.5V, no external REF load 1.98 2.02 V Overvoltage Trip Threshold (Fixed-Threshold Mode)

With respect to error comparator threshold, no load OVP = GND, rising edge, hysteresis = 1%

12 17 %

External feedback, measured at FB with respect toVOVP, 1V < VOVP 1.8V, rising edge, hysteresis = 1%

-30 +30 mV Overvoltage Comparator Offset (Adjustable-Threshold Mode) Internal feedback, measured at OUT with respect to the

nominal OUT regulation voltage, 1V < VOVP < 1.8V -3.5 +3.5 %

Output Undervoltage ProtectionTrip Threshold (Fixed ThresholdMode)

With respect to error comparator threshold,UVP = VCC

65 70 75 %

Output Undervoltage ProtectionTrip Threshold (Adjustable Mode)

Measured at FB/OUT with respect to VUVP; 0.4V < VUVP< 1.0V

-5 +5 %

PGOOD Trip Threshold (Lower) With respect to error comparator threshold, no load OUT falling edge, hysteresis = 1%

-12.5 -7.5 %

PGOOD Trip Threshold (Upper) With respect to error comparator threshold, no load OUT rising edge, hysteresis = 1%

7.5 12.5 %

PGOOD Output Low Voltage ISINK = 1mA 0.4 V PGOOD Leakage Current High state, forced to 5.5V 1 µA

Current-Limit Threshold (Fixed) GND - VCS, ILIM = VCC 85 115 mV

GND - VCS, VILIM = 0.5V 35 65 Current-Limit Threshold(Adjustable) GND - VCS, VILIM = 2V 160 240

mV

VCC UndervoltageLockout Threshold

Rising edge, hysteresis = 20mV, PWM disabled below this level

4.1 4.4 V

Logic Input High Voltage LATCH, SHDN, SKIP 2.4 V Logic Input Low Voltage LATCH, SHDN, SKIP 0.8 V Logic Input Current LATCH, SHDN, SKIP -1 +1 µA

ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC = VDD = 5V, SKIP = LATCH = GND, TA = -40°C to +85°C, unless otherwise noted.) (Note 3)

Note 1: When the inductor is in continuous conduction, the output voltage has a DC regulation level higher than the error compara-tor threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regu-lation level higher than the trip level by approximately 1.5% due to slope compensation.

Note 2: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, VBST = 5V,and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching speeds.

Note 3: Specifications to -40°C are guaranteed by design, not production tested.Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin

QFN package. The MAX8764EEP and MAX8764ETP contain the same die and the thin QFN package imposes no additionalresistance in-circuit.

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100

600.01 1 10

EFFICIENCY vs. LOAD CURRENT

70

65

75

80

85

90

95M

AX87

64 to

c01

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

0.1

VIN = 7V

VIN = 12V

VIN = 20V

350

00.01 1 10

FREQUENCY vs. LOAD CURRENT

100

50

150

200

250

300

MAX

8764

toc0

2

LOAD CURRENT (A)

FREQ

UENC

Y (k

Hz)

0.1

VIN = 15V, SKIP = VCC

VIN = 15V, SKIP = GND

VIN = 7V, SKIP = GND

VIN = 7V, SKIP = VCC320

310

300

290

2800 155 10 20 25 30

FREQUENCY vs. INPUT VOLTAGE

MAX

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INPUT VOLTAGE (V)

FREQ

UENC

Y (k

Hz)

ILOAD = 1A

290

300

310

320

330

-40 -10 20 50-25 5 35 65 80

FREQUENCY vs. TEMPERATURE

MAX

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TEMPERATURE (°C)

FREQ

UENC

Y (k

Hz)

ILOAD = 1A

ILOAD = 4A

-40 5 20-25 -10 35 50 65 80

CURRENT LIMIT vs. TEMPERATURE

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TEMPERATURE (°C)

CURR

ENT

LIM

IT (A

)

3

4

5

6

0

100

200

300

400

500

600

700

800

0 105 15 20 25 30

CONTINUOUS-TO-DISCONTINUOUS INDUCTORCURRENT vs. INPUT VOLTAGE

MAX

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INPUT VOLTAGE (V)

LOAD

CUR

RENT

(mA)

CONTINUOUS INDUCTOR CURRENT

DISCONTINUOUS INDUCTOR CURRENT

0

1

2

3

4

5

6

7

8

0 105 15 20 25 30

CURRENT LIMIT vs. INPUT VOLTAGE

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INPUT VOLTAGE (V)

CURR

ENT

LIM

IT (A

)

1.8

1.6

1.4

1.2

1.01.0 1.41.2 1.6 1.8

NORMALIZED OVERVOLTAGETRIP THRESHOLD vs. VOVP

MAX

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VOVP (V)

NORM

ALIZ

ED T

HRES

HOLD

(V/V

)

OVERVOLTAGE TRIP THRESHOLDOUTPUT VOLTAGE SET POINT

110

112

116

114

118

120

-40 10-15 35 60 85

OVERVOLTAGE TRIP THRESHOLDvs. TEMPERATURE

MAX

8764

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TEMPERATURE (°C)

OVER

VOLT

AGE

TRIP

THR

ESHO

LD (%

)

__________________________________________Typical Operating Characteristics(Circuit of Figure 1, VIN = 15V, SKIP = LATCH = GND, TON = unconnected, TA = +25°C, unless otherwise noted.)

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0

2

6

4

8

10

0 105 15 20 25 30

NO-LOAD SUPPLY CURRENTvs. INPUT VOLTAGE (PWM MODE)

MAX

8764

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0

INPUT VOLTAGE (V)

SUPP

LY C

URRE

NT (m

A)

IIN

IDD

ICC

0.8

0.6

0.4

0.2

00 155 10 20 25 30

NO-LOAD SUPPLY CURRENTvs. INPUT VOLTAGE (SKIP MODE)

MAX

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INPUT VOLTAGE (V)

SUPP

LY C

URRE

NT (m

A)

ICC

IINIDD

20µs/div

LOAD-TRANSIENT RESPONSE(PWM MODE)

INDUCTOR CURRENT2A/div

VOUTAC-COUPLED100mV/div

DL5V/div

MAX8764 toc12A

20µs/div

LOAD-TRANSIENT RESPONSE(SKIP MODE)

INDUCTORCURRENT2A/div

VOUTAC-COUPLED100mV/div

DL5V/div

MAX8764 toc12B

400µs/div

STARTUPMAX8764 toc14

VOUT2V/div

SHDN5V/div

PGOOD5V/div

DL5V/div

INDUCTORCURRENT 5A/div

RLOAD = 0.4Ω

40µs/div

OUTPUT OVERLOAD WAVEFORM(UVP = GND)

VOUT2V/div

LOAD FET2V/div

PGOOD5V/div

DL5V/div


MAX8764 toc13A

40µs/div

OUTPUT OVERLOAD WAVEFORM(UVP = VCC)

MAX8764 toc13B

VOUT2V/div

LOAD FET2V/div

PGOOD5V/div

DL5V/div


100µs/div

SHUTDOWN WAVEFORMMAX8764 toc15A

RLOAD = 0.4Ω

VOUT2V/div

SHDN5V/div

PGOOD5V/div

DL5V/div


1ms/div

OUTPUT OVERVOLTAGE WAVEFORM(OVP = GND)

VOUT1V/div

PGOOD5V/div

DL5V/divINDUCTORCURRENT 5A/div

MAX8764 toc15B

Typical Operating Characteristics (continued)(Circuit of Figure 1, VIN = 15V, SKIP = LATCH = GND, TON = unconnected, TA = +25°C, unless otherwise noted.)

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PIN

QSOP THINQFN

NAME FUNCTION

1 18 CS

Current-Sense Input. Connect a low-value, current-sense resistor between CS and GND for accuratecurrent sensing. For lower power dissipation (less accurate) current sensing, connect CS to LX touse the synchronous rectifier as the sense resistor. The PWM controller does not begin a cycleunless the current sensed at CS is less than the current-limit threshold programmed at ILIM.

2 19 LATCH

Overvoltage Protection Latch Control Input. The synchronous rectifier MOSFET is always forced tothe ON state when an overvoltage fault is detected. If LATCH is low, the synchronous rectifierremains on until either OVP is brought high, or VCC is cycled below 1V. If LATCH is high, the faultprotections (UVP and OVP) are disabled.

3 20 SHDN Shutdown Control Input. Drive SHDN to GND to force the MAX1844 into shutdown. Drive or connectto VCC for normal operation. A rising edge on SHDN clears the overvoltage and undervoltageprotection fault latches.

4 1 OVP

Overvoltage Protection Control Input. An overvoltage fault occurs if the internal or external feedbackvoltage exceeds the voltage at OVP. Apply a voltage between 1V and 1.8V to set the overvoltagelimit between 100% and 180% of nominal output voltage. Connect to GND to assert the defaultovervoltage limit at 114% of the nominal output voltage. Connect OVP or LATCH to VCC to disableovervoltage fault detection and clear the overvoltage protection fault latch.

5 2 FB Feedback Input. Connect to VCC for a 1.8V fixed output or to GND for a 2.5V fixed output. For anadjustable output (1V to 5.5V), connect FB to a resistive divider from the output voltage. The FBregulation level is 1V.

6 3 OUT Output-Voltage Sense Connection. Connect directly to the junction of the external output filtercapacitors. OUT senses the output voltage to determine the on-time for the high-side switchingMOSFET. OUT also serves as the feedback input in fixed-output modes.

7 4 ILIM

Current-Limit Threshold Adjustment. The current-limit threshold at CS is 0.1 times the voltage at ILIM.Connect ILIM to a resistive divider (typically from REF) to set the current-limit threshold between25mV and 300mV (with 0.25V to 3V at ILIM). Connect to VCC to assert the 100mV default current-limitthreshold.

8 5 REF 2V Reference Voltage Output. Bypass to GND with a 0.22µF (min) bypass capacitor. Can supply50µA for external loads. Reference turns off in shutdown.

9 6 UVP

Undervoltage Protection Control Input. An undervoltage fault occurs if the internal or externalfeedback voltage is less than the voltage at UVP. Apply a voltage between 0.4V and 1V to set theundervoltage limit between 40% and 100% of the nominal output voltage. Connect to VCC to assertthe default undervoltage limit of 70% of the nominal output voltage. Connect UVP to GND or LATCHto VCC to disable undervoltage fault detection and clear the undervoltage protection latch.

10 7 PGOOD Power-Good, Open-Drain Output. PGOOD is low when the output voltage is more than 10% above orbelow the normal regulation point or during soft-start. PGOOD is high impedance when the output isin regulation and the soft-start circuit has terminated. PGOOD is low in shutdown.

11 8 GND Analog and Power Ground

12 9 DL Synchronous Rectifier Gate-Driver Output. Swings from GND to VDD.

13 10 VDD Supply Input for the DL Gate Drive. Connect to the system supply voltage, 4.5V to 5.5V. Bypass toGND with a 1µF (min) ceramic capacitor.

Pin Description

Standard Application CircuitThe standard application circuit (Figure 1) generates a2.5V rail for general-purpose use in a notebook computer.

See Table 1 for component selections. Table 2 lists com-ponent manufacturers.

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PIN

QSOP THINQFN

NAME FUNCTION

14 11 VCC Analog Supply Input. Connect to the system supply voltage, 4.5V to 5.5V, with a series 20Ω resistor.Bypass to GND with a 1µF (min) ceramic capacitor.

15 12 TON On-Time Selection-Control Input. This four-level logic input sets the nominal DH on-time. Connect toGND, REF, VCC, or leave TON unconnected to select the following nominal switching frequencies:GND = 600kHz, REF = 450kHz, floating = 300kHz, and VCC = 200kHz.

16 13 V+ Battery-Voltage Sense Connection. Connect to input power source. V+ is used only to set the PWMone-shot timing.

17 14 SKIP Pulse-Skipping Control Input. Connect to VCC for low-noise, forced-PWM mode. Connect to GND toenable pulse-skipping operation.

18 15 BST Boost Flying-Capacitor Connection. Connect to an external capacitor and diode according to theStandard Application Circuit (Figure 1). See the MOSFET Gate Drivers (DH, DL) section.

19 16 LX External Inductor Connection. Connect LX to the switched side of the inductor. LX serves as thelower supply rail for the DH high-side gate driver.

20 17 DH High-Side Gate-Driver Output. Swings from LX to BST.

Pin Description (continued)

Table 1. Component Selection forStandard Applications

COMPONENT 2.5V AT 4A

C1 Input Capacitor10µF, 25VTaiyo Yuden TMK432BJ106KM orTDK C4532X5R1E106M

C2 Output Capacitor330µF, 6VKemet T510X477108M006AS orSanyo 6TPB330M

D1 Schottky Nihon EP10QY03

L1 Inductor4.7µHCoilcraft DO33116P-682 orSumida CDRH124-4R7MC

Q1 High-Side MOSFETFairchild Semiconductor1/2 FDS6982A

Q2 Low-Side MOSFETFairchild Semiconductor1/2 FDS6982A

RSENSE

0.015Ω ±1%, 0.5W resistorIRC LR2010-01-R015F orDale WSL-2010-R015F

Table 2. Component Suppliers

*Distributor

SUPPLIER USA PHONE FACTORY FAX

Coilcraft 847-639-6400 1-847-639-1469

Dale-Vishay 203-452-5664 1-203-452-5670

Fairchild 408-822-2181 1-408-721-1635

IRC 800-752-8708 1-828-264-7204

Kemet 408-986-0424 1-408-986-1442

NIEC (Nihon) 805-867-2555* 81-3-3494-7414

Sanyo 619-661-6835 81-7-2070-1174

Sumida 847-956-0666 81-3-3607-5144

Taiyo Yuden 408-573-4150 1-408-573-4159

TDK 847-390-4461 1-847-390-4405

Detailed DescriptionThe MAX8764 buck controller is targeted for low-voltagepower supplies for notebook computers. Maxim’s propri-etary Quick-PWM pulse-width modulator in the MAX8764is specifically designed for handling fast load steps whilemaintaining a relatively constant operating frequencyand inductor operating point over a wide range of inputvoltages. The Quick-PWM architecture circumvents thepoor load-transient timing problems of fixed-frequency,current-mode PWMs while also avoiding the problemscaused by widely varying switching frequencies in con-ventional constant-on-time and constant-off-time PWMschemes.

5V Bias Supply (VCC and VDD)The MAX8764 requires an external 5V bias supply inaddition to the battery. Typically, this 5V bias supply isthe notebook’s 95% efficient 5V system supply. Keepingthe bias supply external to the IC improves efficiencyand eliminates the cost associated with the 5V linear reg-ulator that would otherwise be needed to supply thePWM circuit and gate drivers. If stand-alone capability isneeded, the 5V supply can be generated with an exter-nal linear regulator such as the MAX1615.

The battery and 5V bias inputs can be connectedtogether if the input source is a fixed 4.5V to 5.5V supply.If the 5V bias supply is powered up prior to the

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10 ______________________________________________________________________________________

VCC

UVP

VIN7V TO 20V

5VBIAS SUPPLY

C2330µF

SEE TABLE 1 FOR OTHER COMPONENT SELECTIONS.

POWER-GOODINDICATOR

L14.7µH

VOUT 2.5V

SHDN

V+

D2CMPSH-3

C63.3µF

C70.1µF

C40.22µF270kΩ

130kΩ

Q1

D1

R2100kΩ

Q2

RSENSE15mΩ

C54.7µF

R120Ω

SKIP

ILIM

ON/OFFCONTROL

LOW-NOISECONTROL

DL

LX

BST

DH

CS

OUT

FBLATCH

OVP

PGOOD

VDD

MAX8764

5V

TON

REF

GND

C110µF

Figure 1. Standard Application Circuit

battery supply, the enable signal (SHDN) must bedelayed until the battery voltage is present to ensurestartup. The 5V bias supply provides VCC and gate-drivepower, so the maximum current drawn is:

IBIAS = ICC + f (QG1 + QG2) = 5mA to 30mA (typ)

where ICC is 550µA (typ), f is the switching frequency,and QG1 and QG2 are the MOSFET data sheet totalgate-charge specification limits at VGS = 5V.

Free-Running, Constant-On-Time PWMController with Input Feed-Forward

The Quick-PWM control architecture is a pseudo-fixed-fre-quency, constant-on-time, on-demand PWM with voltagefeed-forward (Figure 2). This architecture relies on the out-put filter capacitor’s ESR to act as a current-sense resistor,so the output ripple voltage provides the PWM ramp sig-nal. The control algorithm is simple: the high-side switchon-time is determined solely by a one-shot whose pulse

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Figure 2. MAX8764 Functional Diagram

REF-10%

FROMOUT

REF

FB

ERRORAMP

TOFF

TON

REF+10%

FEEDBACKMUX

(SEE FIGURE 6)

CHIPSUPPLY

x2

1.0V

R

0.1V

POR

OVP

9RILIM

VCC - 1V

VCC - 1V

VCC - 1V

SHDN

PGOOD

ON-TIMECOMPUTE

TON

1-SHOT

1-SHOT

TRIG

IN2V TO 28V

TRIG

Q

Q

S

R

2VREF

REF

5V

OUTPUT

DL

CS

GND

VCC

VDD

LX

ZERO CROSSING

CURRENTLIMIT

DH

BST

5V

+5V

Q

SKIP

TON

LATCH

V+

Σ

MAX8764

S

RQ

0.7V

1.14V

UVP

20msTIMER

OVP/UVPLATCH

0.1V

OUT

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width is inversely proportional to input voltage and directlyproportional to output voltage. Another one-shot sets aminimum off-time (400ns typ). The on-time, one-shot istriggered if the error comparator is low, the low-side switchcurrent is below the current-limit threshold, and the mini-mum off-time, one-shot has timed out.

On-Time One-Shot (TON)The heart of the PWM core is the one-shot that sets thehigh-side switch on-time. This fast, low-jitter, adjustableone-shot includes circuitry that varies the on-time inresponse to battery and output voltage. The high-sideswitch on-time is inversely proportional to the batteryvoltage as measured by the V+ input, and proportionalto the output voltage. This algorithm results in a nearlyconstant switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a constantswitching frequency are twofold: first, the frequency canbe selected to avoid noise-sensitive regions such as the455kHz IF band; second, the inductor ripple-currentoperating point remains relatively constant, resulting in

easy design methodology and predictable output volt-age ripple. The on-time is given by:

On-Time = K (VOUT + 0.075V) / VIN

where K (switching period) is set by the TON pin-strapconnection (Table 4), and 0.075V is an approximation toaccommodate for the expected drop across the low-sideMOSFET switch. One-shot timing error increases for theshorter on-time settings due to fixed propagation delays;it is approximately ±12.5% at 600kHz and 450kHz, and±10% at the two slower settings. This translates toreduced switching-frequency accuracy at higher frequen-cies (Table 5). Switching frequency increases as a func-tion of load current due to the increasing drop across thelow-side MOSFET, which causes a faster inductor-currentdischarge ramp. The on-times guaranteed in theElectrical Characteristics are influenced by switchingdelays in the external high-side power MOSFET.

Two external factors that influence switching-frequencyaccuracy are resistive drops in the two conduction loops(including inductor and PC board resistance) and thedead-time effect. These effects are the largest contribu-tors to the change of frequency with changing load cur-rent. The dead-time effect increases the effectiveon-time, reducing the switching frequency as one orboth dead times are added to the effective on-time. Itoccurs only in PWM mode (SKIP = high) when the induc-tor current reverses at light or negative load currents.With reversed inductor current, the inductor’s EMF caus-es LX to go high earlier than normal, extending the on-time by a period equal to the low-to-high dead time.

For loads above the critical conduction point, the actualswitching frequency is:

f V V

t (V V )OUT DROP1

ON IN DROP2

=+

+


12 ______________________________________________________________________________________

Table 3. Operating Mode Truth Table

Good operating point forcompound buck designsor desktop circuits.

+5V input600

TON = GND

450TON = REF

3-cell Li+ notebook

Useful in 3-cell systemsfor lighter loads than theCPU core or where size iskey.

Considered mainstreamby current standards.

4-cell Li+ notebook 300

TON = Floating

200 TON = VCC

4-cell Li+ notebook Use for absolute bestefficiency.

COMMENTSTYPICAL

APPLICATIONFREQUENCY

(kHz)

Table 4. Frequency Selection Guidelines

SHDN SKIP DL MODE COMMENTS

0 X LowShutdown, output UVP fault,

thermal shutdown, UVLOLow-power shutdown state. DL is forced to GND. ICC < 1µA typ.

1 VCC Switching Run (PWM), low noiseLow-noise operation with no automatic switchover. Fixed-frequencyPWM action is forced regardless of load. Inductor current reverses atlight-load levels. Low noise. High IQ.

1 GND Switching Run (PFM/PWM)Normal operation with automatic PWM/PFM switchover for pulseskipping at light loads. Best light-load efficiency.

1 X High FaultFault latch has been set by overvoltage protection. Device remains inFAULT mode until VCC power is cycled.

where VDROP1 is the sum of the parasitic voltage dropsin the inductor discharge path, including synchronousrectifier, inductor, and PC board resistances; VDROP2 isthe sum of the resistances in the charging path, and tONis the on-time calculated by the MAX8764.

Automatic Pulse-Skipping SwitchoverIn skip mode (SKIP low), an inherent automaticswitchover to PFM takes place at light loads (Table 3).This switchover is affected by a comparator that trun-cates the low-side switch on-time at the inductor current’szero crossing. This mechanism causes the thresholdbetween pulse-skipping PFM and nonskipping PWMoperation to coincide with the boundary between continu-ous and discontinuous inductor-current operation (alsoknown as the “critical conduction” point; see theContinuous-to-Discontinuous Inductor Current vs. InputVoltage graph in the Typical Operating Characteristics).In low-duty-cycle applications, this threshold is relativelyconstant, with only a minor dependence on battery voltage.

where K is the on-time scale factor (Table 5). The load-current level at which PFM/PWM crossover occurs,ILOAD(SKIP), is equal to 1/2 the peak-to-peak ripple cur-rent, which is a function of the inductor value (Figure 3).For example, in the Standard Application Circuit with K = 3.3µs (Table 5), VOUT = 2.5V, VIN = 15V, and L =6.8µH, switchover to pulse-skipping operation occurs atILOAD = 0.51A or about 1/8 full load. The crossover pointoccurs at an even lower value if a swinging (soft-satura-tion) inductor is used.

The switching waveforms may appear noisy and asyn-chronous when light loading causes pulse-skippingoperation, but this is a normal operating condition that

results in high light-load efficiency. Trade-offs in PFMnoise vs. light-load efficiency are made by varying theinductor value. Generally, low inductor values produce abroader efficiency vs. load curve, while higher valuesresult in higher full-load efficiency (assuming that the coilresistance remains fixed) and less output voltage ripple.Penalties for using higher inductor values include largerphysical size and degraded load-transient response(especially at low-input voltage levels).

DC output accuracy specifications refer to the thresholdof the error comparator. When the inductor is in continu-ous conduction, the output voltage has a DC regulationlevel higher than the trip level by 50% of the ripple. Indiscontinuous conduction (SKIP = GND, light load), theoutput voltage has a DC regulation level higher than theerror-comparator threshold by approximately 1.5% dueto slope compensation.

Forced-PWM Mode (SKIP = High)The low-noise, forced-PWM mode (SKIP = high) disablesthe zero-crossing comparator, which controls the low-side switch on-time. This causes the low-side gate-drivewaveform to become the complement of the high-sidegate-drive waveform. This in turn causes the inductorcurrent to reverse at light loads while DH maintains aduty factor of VOUT/VIN. The benefit of forced-PWMmode is to keep the switching frequency fairly constant,but it comes at a cost: the no-load battery current can be10mA to 40mA, depending on the external MOSFETs.

Forced-PWM mode is most useful for reducing audio-frequency noise, improving load-transient response, pro-viding sink-current capability for dynamic output voltage adjustment, and improving the cross-regulation ofmultiple-output applications that use a flyback trans-former or coupled inductor.

IKV

2L

V -VV

LOAD(SKIP)OUT IN OUT

IN≈ ×

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Figure 3. Pulse-Skipping/Discontinuous Crossover Point

INDU

CTOR

CUR

RENT

ILOAD = IPEAK / 2

ON-TIME0 TIME

IPEAKL

VBATT -VOUT∆i∆t

=

Figure 4. ‘‘Valley’’ Current-Limit Threshold Point

ILIMIT

ILOAD

0 TIME

IPEAK

INDU

CTOR

CUR

RENT

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4 Current-Limit Circuit (ILIM)The current-limit circuit employs a unique “valley” cur-rent-sensing algorithm (Figure 4). If the magnitude of thecurrent-sense voltage at CS is above the current-limitthreshold, the PWM is not allowed to initiate a new cycle.The actual peak current is greater than the current-limitthreshold by an amount equal to the inductor ripple cur-rent. Therefore, the exact current-limit characteristic andmaximum load capability are a function of the senseresistance, inductor value, and battery voltage.

There is also a negative current limit that prevents exces-sive reverse inductor currents when VOUT is sinking cur-rent. The negative current-limit threshold is set toapproximately 120% of the positive current limit andtherefore tracks the positive current limit when ILIM isadjusted.

The current-limit threshold is adjusted with an externalresistor-divider at ILIM. A 1µA (min) divider current isrecommended. The current-limit threshold adjustmentrange is from 25mV to 300mV. In the adjustable mode,the current-limit threshold voltage is precisely 1/10 thevoltage seen at ILIM. The threshold defaults to 100mVwhen ILIM is connected to VCC. The logic threshold forswitchover to the 100mV default value is approximatelyVCC - 1V.

Carefully observe the PC board layout guidelines toensure that noise and DC errors do not corrupt the cur-rent-sense signal seen by CS. Mount or place the ICclose to the low-side MOSFET and sense resistor withshort, direct traces, making a Kelvin sense connection tothe sense resistor.

In Figure 1, the Schottky diode (D1) provides a currentpath parallel to the Q2/RSENSE current path. Accuratecurrent sensing demands D1 to be off while Q2 con-ducts. Avoid large current-sense voltages that, com-bined with the voltages across Q2, would allow D1 toconduct. If very large sense voltages are used, connectD1 in parallel with Q2.

MOSFET Gate Drivers (DH, DL)The DH and DL drivers are optimized for driving moder-ate-sized high-side, and larger low-side powerMOSFETs. This is consistent with the low duty factorseen in the notebook environment, where a large VBATT -VOUT differential exists. An adaptive dead-time circuitmonitors the DL output and prevents the high-side FETfrom turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to theMOSFET gate for the adaptive dead-time circuit to work

properly; otherwise, the sense circuitry in the MAX8764interprets the MOSFET gate as “off” while there is actual-ly still charge left on the gate. Use very short, wide tracesmeasuring no more than 20 squares (50 mils to 100 milswide if the MOSFET is 1in from the MAX8764).

The dead time at the other edge (DH turning off) is deter-mined by a fixed 35ns (typ) internal delay.

The internal pulldown transistor that drives DL low isrobust, with a 0.5Ω (typ) on-resistance. This helps pre-vent DL from being pulled up during the fast rise time ofthe inductor node, due to capacitive coupling from thedrain to the gate of the low-side synchronous-rectifierMOSFET. However, for high-current applications, thereare still some combinations of high- and low-side FETsthat will cause excessive gate-drain coupling, which canlead to efficiency-killing, EMI-producing, shoot-throughcurrents. This is often remedied by adding a resistor inseries with BST, which increases the turn-on time of thehigh-side FET without degrading the turn-off time (Figure 5).

POR, UVLO, and Soft-StartPower-on reset (POR) occurs when VCC rises aboveapproximately 2V, resetting the fault latch and soft-startcounter, and preparing the PWM for operation. Until VCCreaches 4.2V, VCC undervoltage lockout (UVLO) circuitryinhibits switching. DL is held low. When VCC rises above4.2V, an internal digital soft-start timer begins to ramp upthe maximum allowed current limit. The ramp occurs infive steps: 20%, 40%, 60%, 80%, and 100%; 100% cur-rent is available after 1.7ms ±50%.


14 ______________________________________________________________________________________

BST

+5VVIN

5Ω

DH

LX

MAX8764

Figure 5. Reducing the Switching-Node Rise Time

Power-Good Output (PGOOD)The PGOOD window comparator continuously monitorsthe output. PGOOD is actively held low in shutdown,standby, and soft-start. After digital soft-start terminates,PGOOD is released if the output is within 10% of thenominal output voltage setting. Note that the PGOODwindow detector is completely independent of the over-voltage and undervoltage protection fault detectors.

Output Overvoltage ProtectionOVP controls the output overvoltage protection func-tion. Connect OVP to VCC or LATCH to VCC to disableovervoltage protection. If overvoltage protection isenabled (OVP < 1.8V, LATCH = GND), the output iscontinuously monitored. If the output exceeds the over-voltage protection threshold, overvoltage protection istriggered and the DL low-side gate-driver output isforced high. This turns on the low-side MOSFET switchto rapidly discharge the output capacitor and reducethe output voltage.

If LATCH is high, the overvoltage protection is dis-abled. If LATCH is low, the DL gate-driver outputremains high until OVP is driven to VCC, or VCC iscycled below 1V. When the condition that caused theovervoltage persists (such as a shorted high-side MOS-FET), the battery fuse opens.

Note that forcing DL high causes the output voltage togo slightly negative when energy has been previouslystored in the LC tank circuit (see the output overvoltagewaveforms in the Typical Operating Characteristics). Ifthe load cannot tolerate being forced to a negative volt-age, it may be desirable to place a power Schottkydiode across the output to act as a reverse-polarityclamp.

Output Undervoltage ProtectionUVP controls the output undervoltage protection func-tion. Connect UVP to GND or LATCH to VCC to disableundervoltage protection. The output undervoltage pro-tection function is similar to foldback current limiting butemploys a timer and latch rather than a variable currentlimit. If the output voltage is below the undervoltage pro-tection threshold after the output undervoltage protectionblanking time has elapsed, the PWM is latched off, DL ispulled low, and the controller does not restart until VCCpower is cycled. SHDN is toggled, or UVP is pulledbelow 0.4V.

Connect UVP to VCC to enable the default undervoltagetrip threshold of 70% of nominal. To select a differentthreshold, drive UVP to a voltage between 0.4V and 1Vfor a threshold between 40% and 100% of nominal.

Fixed-Output VoltagesThe MAX8764’s Dual Mode operation allows the selec-tion of common voltages without requiring external com-ponents (Figure 6). Connect FB to GND for a fixed 2.5Voutput or to VCC for a 1.8V output, or connect FB directlyto OUT for a fixed 1V output.

Setting VOUT with a Resistor-DividerThe output voltage can be adjusted from 1V to 5.5V witha resistor-divider if desired (Figure 7). The equation foradjusting the output voltage is:

where VFB is 1V.

Design ProcedureComponent selection for the MAX8764 is primarily dictat-ed by the following four criteria:

1) Input voltage range. The maximum value (VIN(MAX))must accommodate the worst-case high AC-adaptervoltage. The minimum value (VIN(MIN)) must accountfor the lowest battery voltage after drops due to con-nectors, fuses, and battery selector switches. Lowerinput voltages result in better efficiency.

V V 1 R1R2OUT FB= +⎛

⎝⎜⎞⎠⎟

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______________________________________________________________________________________ 15

0.2V

2V

OUT

FB

FIXED1.8V

TO ERROR AMP

FIXED2.5V

MAX8764

Figure 6. Feedback Mux

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4 2) Maximum load current. There are two values to con-sider. The peak load current (ILOAD(MAX)) determinesthe instantaneous component stresses and filteringrequirements and thus drives output capacitor selec-tion, inductor saturation rating, and the design of thecurrent-limit circuit. The continuous load current(ILOAD) determines the thermal stresses and thus dri-ves the selection of input capacitors, MOSFETs, andother critical heat-contributing components.

3)Switching frequency. This choice determines thebasic trade-off between size and efficiency. The opti-mal frequency is largely a function of maximum inputvoltage, due to MOSFET switching losses that areproportional to frequency and VIN2. The optimum fre-quency is also a moving target, due to rapid improve-ments in MOSFET technology that are making higherfrequencies more practical (Table 4).

4) Inductor operating point. This choice providestrade-offs between size vs. efficiency. Low inductorvalues cause large ripple currents, resulting in thesmallest size, but poor efficiency and high output rip-ple. The minimum practical inductor value is one thatcauses the circuit to operate at the edge of criticalconduction (where the inductor current just toucheszero with every cycle at maximum load). Inductor val-ues lower than this grant no further size-reductionbenefit.

The MAX8764’s pulse-skipping algorithm initiates skipmode at the critical conduction point. So, the inductoroperating point also determines the load-current valueat which PFM/PWM switchover occurs.

These four factors impact the component selectionprocess. Selecting components and calculating theireffect on the MAX8764’s operation is best done with aspreadsheet. Using the formulas provided, calculate theLIR (the ratio of the inductor ripple current to thedesigned maximum load current) for both the minimumand maximum input voltages. Maintaining an LIR within a20% to 50% range is recommended. The use of aspreadsheet allows quick evaluation of componentselection.

Inductor SelectionThe switching frequency and inductor operating pointdetermine the inductor value as follows:

Example: ILOAD(MAX) = 8A, VIN = 7V, VOUT = 1.5V, f = 300kHz, 33% ripple current or LIR = 0.33:

Find a low-loss inductor having the lowest possible DCresistance that fits in the allotted dimensions. Ferritecores are often the best choice, although powdered ironis inexpensive and can work well at 200kHz. The coremust be large enough not to saturate at the peak induc-tor current (IPEAK):

IPEAK = ILOAD(MAX) + [(LIR / 2) ILOAD(MAX)]

Most inductor manufacturers provide inductors in stan-dard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc.Also look for nonstandard values, which can provide abetter compromise in LIR across the input voltage range.If using a swinging inductor (where the no-load induc-tance decreases linearly with increasing current), evalu-ate the LIR with properly scaled inductance values.

Transient Response The inductor ripple current also impacts transient-response performance, especially at low VIN - VOUT dif-ferentials. Low inductor values allow the inductorcurrent to slew faster, replenishing charge removedfrom the output filter capacitors by a sudden load step.The amount of output sag is also a function of the maxi-mum duty factor, which can be calculated from the on-time and minimum off-time:

L1.5V (7V -1.5V)

7V 300kHz 0.33 8A 1.49 H=

× × ×= µ

L = V (V - V )

V f LIR IOUT IN OUT

IN LOAD(MAX) × × ×


16 ______________________________________________________________________________________

DL

GND

OUT

CS

DH

FB

VBATT

VOUT

R1

R2

MAX8764

Figure 7. Setting VOUT with a Resistor-Divider

where

and minimum off-time = 400ns (typ) (see Table 5 for Kvalues).

The amount of overshoot during a full-load to no-loadtransient due to stored inductor energy can be calculatedas:

Setting the Current LimitFor most applications, set the MAX8764 current limit bythe following procedure:

1) Determine the minimum (valley) inductor currentIL(MIN) under conditions when VIN is small, VOUT islarge, and load current is maximum. The minimuminductor current is ILOAD minus half the ripple cur-rent (Figure 4).

2) The sense resistor determines the achievable current-limit accuracy. There is a trade-off between current-limit accuracy and sense-resistor power dis-sipation. Most applications employ a current-sensevoltage of 50mV to 100mV. Choose a sense resistorso that:

RSENSE = CS Threshold Voltage / IL(MIN)

Extremely cost-sensitive applications that do notrequire high-accuracy current sensing can use the on-resistance of the low-side MOSFET switch in place ofthe sense resistor by connecting CS to LX (Figure 8b).Use the worst-case value for RDS(ON) from the MOSFETQ2 data sheet, and add a margin of 0.5%/°C for therise in RDS(ON) with temperature. Then use thatRDS(ON) value and IL(MIN) from step 1 above to deter-mine the CS threshold voltage. If the default 100mVthreshold is unacceptable, set the value as in step 2above.

In all cases, ensure an acceptable CS threshold volt-age despite inaccuracies in resistor values.

Output Capacitor SelectionThe output filter capacitor must have low enough effectiveseries resistance (ESR) to meet output ripple and load-

transient requirements, yet have high enough ESR to sat-isfy stability requirements.

For CPU core voltage converters and other applicationswhere the output is subject to violent load transients, theoutput capacitor’s size depends on how much ESR isneeded to prevent the output from dipping too low undera load transient. Ignoring the sag due to finite capaci-tance:

In nonCPU applications, the output capacitor’s size oftendepends on how much ESR is needed to maintain anacceptable level of output voltage ripple:

The actual microfarad capacitance value required relatesto the physical size needed to achieve low ESR, as wellas to the chemistry of the capacitor technology. Thus, thecapacitor is usually selected by ESR and voltage ratingrather than by capacitance value (this is true of tantalums,OS-CONs, and other electrolytics).

When using low-capacity filter capacitors, such asceramic or polymer types, capacitor size is usually deter-mined by the capacity needed to prevent VSAG andVSOAR from causing problems during load transients.Generally, once enough capacitance is added to meetthe overshoot requirement, undershoot at the rising loadedge is no longer a problem (also, see the VSAG andVSOAR equation in the Transient Response section).

RV

LIR IESRP-P

LOAD(MAX)

≤×

RV

IESR

DIP

LOAD(MAX)

≤

LV

f x LIR x IOUT

LOAD MAX=

( )

DUTYK (V + 0.075V)/ V

K (V + 0.075V)/ V + min off - timeOUT IN

OUT OUT =

V( I ) L

2 C DUTY (V - V ) SAG

LOAD(MAX)2

OUT IN(MIN) OUT

=×

× ×∆

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DL

CS

LX

a) b)

MAX8764

DL

CS

LX

MAX8764

Figure 8. Current-Sense Circuits

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4 Output Capacitor Stability ConsiderationsStability is determined by the value of the ESR zero rela-tive to the switching frequency. The point of instability isgiven by the following equation:

where:

For a typical 300kHz application, the ESR zero frequencymust be well below 95kHz, preferably below 50kHz.

Tantalum and OS-CON capacitors in widespread use atthe time of publication have typical ESR zero frequenciesof 25kHz. In the design example used for inductor selec-tion, the ESR needed to support 60mVP-P ripple is 60mV/2.7A = 22mΩ. Two 470µF/4V Kemet T510 low-ESRtantalum capacitors in parallel provide 22mΩ (max) ESR.Their typical combined ESR results in a zero at 27kHz,well within the bounds of stability.

Do not put high-value ceramic capacitors directly acrossthe feedback sense point without taking precautions toensure stability. Large ceramic capacitors can have ahigh ESR zero frequency and cause erratic, unstableoperation. However, it is easy to add enough seriesresistance by placing the capacitors a couple of inchesdownstream from the feedback sense point, whichshould be as close as possible to the inductor.

Unstable operation manifests itself in two related but dis-tinctly different ways: double-pulsing and fast-feedbackloop instability.

Double-pulsing occurs due to noise on the output orbecause the ESR is so low that there is not enough volt-age ramp in the output voltage signal. This “fools” theerror comparator into triggering a new cycle immediatelyafter the 400ns minimum off-time period has expired.Double-pulsing is more annoying than harmful, resultingin nothing worse than increased output ripple. However,it can indicate the possible presence of loop instability,which is caused by insufficient ESR.

Loop instability can result in oscillations at the output after line or load perturbations that can trip the overvolt-age protection latch or cause the output voltage to fallbelow the tolerance limit.

The easiest method for checking stability is to apply avery fast zero-to-max load transient and carefullyobserve the output voltage ripple envelope for over-shoot and ringing. It can help to monitor simultaneouslythe inductor current with an AC current probe. Do not

allow more than one cycle of ringing after the initialstep-response under- or overshoot.

Input Capacitor SelectionThe input capacitor must meet the ripple currentrequirement (IRMS) imposed by the switching currents.Nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to power-upsurge currents:

For optimal circuit reliability, choose a capacitor thathas less than 10°C temperature rise at the peak ripplecurrent.

Power MOSFET SelectionMost of the following MOSFET guidelines focus on thechallenge of obtaining high load-current capability (>5A)when using high-voltage (>20V) AC adapters. Low-cur-rent applications usually require less attention.

For maximum efficiency, choose a high-side MOSFET(Q1) that has conduction losses equal to the switchinglosses at the optimum battery voltage (15V). Check toensure that the conduction losses at minimum inputvoltage do not exceed the package thermal limits or violate the overall thermal budget. Check to ensure thatconduction losses plus switching losses at the maxi-mum input voltage do not exceed the package ratingsor violate the overall thermal budget.

Choose a low-side MOSFET (Q2) that has the lowestpossible RDS(ON), comes in a moderate to small pack-age (i.e., 8-pin SO), and is reasonably priced. Ensurethat the MAX8764 DL gate driver can drive Q2; in otherwords, check that the gate is not pulled up by the high-side switch turn on, due to parasitic drain-to-gate capac-itance, causing crossconduction problems. Switchinglosses are not an issue for the low-side MOSFET since itis a zero-voltage switched device when used in the bucktopology.

MOSFET Power DissipationWorst-case conduction losses occur at the duty factorextremes. For the high-side MOSFET, the worst-casepower dissipation due to resistance occurs at minimumbattery voltage:

PD(Q1 Resistive) = (VOUT / VIN(MIN)) ILOAD2 RDS(ON)

Generally, a small high-side MOSFET is desired toreduce switching losses at high input voltages. However,the RDS(ON) required to stay within package power-dissi-

I IV V - V

V RMS LOAD

OUT IN OUT

IN=

( )⎛

⎝

⎜⎜⎜

⎞

⎠

⎟⎟⎟

ff

f1

2 R C

ESR

ESRESR OUT

=

=× × ×

π

π


18 ______________________________________________________________________________________

pation limits often limits how small the MOSFET can be.Again, the optimum occurs when the switching (AC)losses equal the conduction (RDS(ON)) losses. High-sideswitching losses do not usually become an issue untilthe input is greater than approximately 15V.

Switching losses in the high-side MOSFET can becomean insidious heat problem when maximum AC adaptervoltages are applied, due to the squared term in theCV2f switching loss equation. If the high-side MOSFETchosen for adequate RDS(ON) at low battery voltagesbecomes extraordinari ly hot when subjected toVIN(MAX), reconsider the choice of MOSFET.

Calculating the power dissipation in Q1 due to switchinglosses is difficult, since it must allow for difficult-to-quanti-fy factors that influence the turn-on and turn-off times.These factors include the internal gate resistance, gatecharge, threshold voltage, source inductance, and PCboard layout characteristics. The following switching losscalculation provides only a very rough estimate and is nosubstitute for breadboard evaluation, preferably includinga sanity check using a thermocouple mounted on Q1:

where CRSS is the reverse transfer capacitance of Q1,and IGATE is the peak gate-drive source/sink current (1Atyp).

For the low-side MOSFET, Q2, the worst-case power dis-sipation always occurs at maximum battery voltage:

PD(Q2) = (1 - VOUT / VIN(MAX)) ILOAD2 RDS(ON)

The absolute worst case for MOSFET power dissipationoccurs under heavy overloads that are greater thanILOAD(MAX) but are not quite high enough to exceed thecurrent limit. To protect against this possibility, you must“overdesign” the circuit to tolerate ILOAD = ILIMIT(HIGH) +[(LIR / 2) ILOAD(MAX)], where ILIMIT(HIGH) is the maxi-mum valley current allowed by the current-limit circuit,including threshold tolerance and sense-resistance vari-ation. If short-circuit protection without overload protec-tion is adequate, enable undervoltage protection, anduse ILOAD(MAX) to calculate component stresses.

Choose a Schottky diode D1 having a forward voltagedrop low enough to prevent the Q2 MOSFET body diodefrom turning on during the dead time. As a general rule,a diode having a DC current rating equal to 1/3 of theload current is sufficient. This diode is optional, and ifefficiency is not critical it can be removed.

Applications InformationDropout Performance

The output voltage adjust range for continuous-conduc-tion operation is restricted by the nonadjustable 500ns(max) minimum off-time one-shot. For best dropout per-formance, use the slower (200kHz) on-time settings.When working with low input voltages, the duty-factorlimit must be calculated using worst-case values for on-and off-times. Manufacturing tolerances and internalpropagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table5). Also, keep in mind that transient response perfor-mance of buck regulators operated close to dropout ispoor, and bulk output capacitance must often beadded (see the VSAG equation in the TransientResponse section).

The absolute point of dropout is when the inductor cur-rent ramps down during the minimum off-time (∆IDOWN)as much as it ramps up during the on-time (∆IUP). Theratio h = ∆IUP/∆IDOWN indicates the circuit’s ability toslew the inductor current higher in response toincreased load, and must always be greater than 1. Ash approaches 1, the absolute minimum dropout point,the inductor current is less able to increase duringeach switching cycle, and VSAG greatly increasesunless additional output capacitance is used.

A reasonable minimum value for h is 1.5, but this canbe adjusted up or down to allow trade-offs betweenVSAG, output capacitance, and minimum operatingvoltage. For a given value of h, the minimum operatingvoltage can be calculated as:

where VDROP1 and VDROP2 are the parasitic voltagedrops in the discharge and charge paths, tOFF(MIN) isfrom the Electrical Characteristics table, and K is takenfrom Table 5. The absolute minimum input voltage is cal-culated with h = 1.

If the calculated VIN(MIN) is greater than the requiredminimum input voltage, operating frequency must bereduced or output capacitance added to obtain anacceptable VSAG. If operation near dropout is anticipat-ed, calculate VSAG to be sure of adequate transientresponse.

VV V

t h

K

V VIN MINOUT DROP

OFF MINDROP DROP( )

( )

=+( )

×⎛

⎝⎜⎜

⎞

⎠⎟⎟

+1

2 1

1-

-

PD(Q1 switching)C V f I

IRSS IN(MAX)

2LOAD

GATE

=× × ×

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______________________________________________________________________________________ 19

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20 ______________________________________________________________________________________

Dropout Design Example:

VOUT = 2.5V

fsw = 300kHz

K = 1.8µs, worst-case K = 2.97µs

tOFF(MIN) = 500ns

VDROP1 = VDROP2 = 100mV

h = 1.5:

Calculating again with h = 1 gives the absolute limit ofdropout:

VV V

s

s

V V VIN MIN( )

. .

.

.

. . .

=+( )

µ ×µ

⎛

⎝⎜

⎞

⎠⎟

+ =2 5 0 1

10 5 1

2 97

0 1 0 1 3 13

-

-

VV V

s

s

V V VIN MIN( )

. .

. .

.

. . .

=+( )

µ ×µ

⎛

⎝⎜

⎞

⎠⎟

+ =2 5 0 1

10 5 1 5

2 97

0 1 0 1 3 48

-

-

AGND PLANE

PGNDPLANE

VIA TO IC OUTPOWER

GROUND

VIA TO ICCS PIN

VDDBYPASS

REFBYPASS

VCCBYPASS

USE AGND PLANE TO: - BYPASS VCC AND REF - TERMINATE EXTERNAL FB, ILIM, OVP, UVP DIVIDERS - PIN-STRAP CONTROL INPUTS

USE PGND PLANE TO: - BYPASS VDD - CONNECT IC GND PIN TO TOP-SIDE POWER GROUND

VIA TO POWERGROUND

TOP SIDEBOTTOM SIDE

VOUT

L1

C1

C2

D1

Q1

VIN

Q2

Q

VIA RS

VIA TO PGND PLANEAND IC GND PIN

Figure 9. Power-Stage PC Board Layout Example

Table 5. Approximate K-Factor ErrorsTON

SETTING(kHz)

APPROXIMATEK-FACTORERROR (%)

MINIMUM VINAT VOUT = 2V

(V)

200 ±10 2.6

300 ±10 2.9

450 ±12.5 3.2

600 ±12.5 3.6

KFACTOR

(µs)

5

3.3

2.2

1.7

Therefore, VIN must be greater than 3.13V, even withvery large output capacitance, and a practical input volt-age with reasonable output capacitance would be 3.48V.

PC Board Layout GuidelinesCareful PC board layout is critical to achieving lowswitching losses and clean, stable operation. The switch-ing power stage requires particular attention (Figure 9). Ifpossible, mount all power components on the top side ofthe board, with their ground terminals flush against oneanother. Follow these guidelines for good PC board lay-out:

• Keep the high-current paths short, especially at theground terminals. This practice is essential for stable,jitter-free operation.

• Keep the power traces and load connections short.This practice is essential for high efficiency. Usingthick copper PC boards (2oz vs. 1oz) can enhancefull-load efficiency by 1% or more. Correctly routingPC board traces is a difficult task that must beapproached in terms of fractions of centimeters,where a single milliohm of excess trace resistancecauses a measurable efficiency penalty.

• Minimize current-sensing errors by connecting CSdirectly to the RSENSE terminal.

• When trade-offs in trace lengths must be made, it ispreferable to allow the inductor charging path to bemade longer than the discharge path. For example,it is better to allow some extra distance between theinput capacitors and the high-side MOSFET than toallow distance between the inductor and the low-side MOSFET or between the inductor and the out-put filter capacitor.

• Route high-speed switching nodes (BST, LX, DH, andDL) away from sensitive analog areas (REF, FB, CS).

Layout Procedure1) Place the power components first, with ground termi-

nals adjacent (Q2 source, CIN-, COUT-, D1 anode). Ifpossible, make all these connections on the top layerwith wide, copper-filled areas.

2) Mount the controller IC adjacent to MOSFET Q2,preferably on the back side opposite Q2 to keep LX,GND, and the DL gate-drive lines short and wide. TheDL gate trace must be short and wide, measuring 10to 20 squares (50 mils to 100 mils wide if the MOSFETis 1in from the controller IC GND pin.

3) Group the gate-drive components (BST diode andcapacitor, VDD bypass capacitor) together near thecontroller IC.

4) Make the DC-DC controller ground connections asshown in Figure 9. This diagram can be viewed ashaving two separate ground planes: power ground,where all the high-power components go; and an ana-log ground plane for sensitive analog components.The analog ground plane and power ground planemust meet only at a single point directly at the IC.

5) Connect the output power planes directly to the out-put filter capacitor positive and negative terminalswith multiple vias. Place the entire DC-DC convertercircuit as close to the load as is practical.

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______________________________________________________________________________________ 21

Chip InformationTRANSISTOR COUNT: 2963

PROCESS: BiCMOS

Pin Configurations

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

DH

LX

BST

SKIPOVP

SHDN

LATCH

CS

TOP VIEW

V+

TON

VCC

VDDREF

ILIM

OUT

FB

12

11

9

10

DL

GNDPGOOD

UVP

MAX8764EEP

QSOP

321

20

19

4 5

6

7

8

9

10

1112131415

16

17

18

THIN QFN

MAX8764ETP

V CC

TON

V+SKIP

BST

REF

ILIM

OUTFB

OVP

LX

DH

CS

LATCH

SHDN

VDD

DL

GND

PGOOD

UVP

+

+

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22 ______________________________________________________________________________________

Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)

QS

OP

.EP

S

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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

23 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)

QFN

TH

IN.E

PS

D2

(ND-1) X e

e

D

C

PIN # 1 I.D.

(NE-1) X e

E/2

E

0.08 C

0.10 C

A

A1 A3

DETAIL A

E2/2

E2

0.10 M C A B

PIN # 1 I.D.

b

0.35x45°

D/2D2/2

LC

LC

e e

LCCL

k

LL

DETAIL B

LL1

e

XXXXXMARKING

H1

221-0140

PACKAGE OUTLINE,16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm

-DRAWING NOT TO SCALE-

L

e/2

COMMON DIMENSIONS

3.353.15T2855-1 3.25 3.353.15 3.25

MAX.

3.20

EXPOSED PAD VARIATIONS

3.00T2055-2 3.10

D2NOM.MIN.

3.203.00 3.10

MIN.

E2NOM. MAX.

NEND

PKG.CODES

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3, AND T2855-6.

NOTES:

SYMBOL

PKG.

N

L1

e

ED

b

A3

A

A1

k

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

JEDEC

T1655-1 3.203.00 3.10 3.00 3.10 3.200.70 0.800.75

4.904.90

0.25

0.25

0

- -

4

WHHB

4

16

0.350.305.105.105.00

0.80 BSC.

5.00

0.05

0.20 REF.

0.02

MIN. MAX.NOM.

16L 5x5

3.10T3255-2 3.00 3.20 3.00 3.10 3.20

2.70T2855-2 2.60 2.602.80 2.70 2.80L 0.30 0.500.40

- -- - --

WHHC

20

55

5.005.000.30

0.55

0.65 BSC.

0.45

0.25

4.904.90

0.25

0.65

--

5.105.10

0.35

20L 5x5

0.20 REF.

0.75

0.02

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

- --

WHHD-1

28

77

5.005.000.25

0.55

0.50 BSC.

0.45

0.25

4.904.90

0.20

0.65

--

5.105.10

0.30

28L 5x5

0.20 REF.

0.75

0.02

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

- --

WHHD-2

32

88

5.005.00

0.40

0.50 BSC.

0.30

0.25

4.904.90

0.50

--

5.105.10

32L 5x5

0.20 REF.

0.75

0.02

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

0.20 0.25 0.30

DOWN BONDS ALLOWED

NO

YES3.103.00 3.203.103.00 3.20T2055-33.103.00 3.203.103.00 3.20T2055-4

T2855-3 3.15 3.25 3.35 3.15 3.25 3.35

T2855-6 3.15 3.25 3.35 3.15 3.25 3.35

T2855-4 2.60 2.70 2.80 2.60 2.70 2.80T2855-5 2.60 2.70 2.80 2.60 2.70 2.80

T2855-7 2.60 2.70 2.80 2.60 2.70 2.80

3.203.00 3.10T3255-3 3.203.00 3.103.203.00 3.10T3255-4 3.203.00 3.10

NO

NONO

NO

NO

NO

NO

NO

YESYES

YES

YES

3.203.00T1655-2 3.10 3.00 3.10 3.20 YESNO3.203.103.003.10T1655N-1 3.00 3.20

3.353.15T2055-5 3.25 3.15 3.25 3.35 YES

3.353.15T2855N-1 3.25 3.15 3.25 3.35 NO3.353.15T2855-8 3.25 3.15 3.25 3.35 YES

3.203.10T3255N-1 3.00 NO3.203.103.00

L

0.40

0.40

********

**

**

********

**

****

**********

** SEE COMMON DIMENSIONS TABLE

±0.15

11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.

H2

221-0140

PACKAGE OUTLINE,16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm

-DRAWING NOT TO SCALE-

12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.

3.30T4055-1 3.20 3.40 3.20 3.30 3.40 ** YES

0.050 0.02

0.600.40 0.50

10

-----

0.30

4010

0.40 0.50

5.104.90 5.00

0.25 0.35 0.45

0.40 BSC.

0.154.90

0.250.205.00 5.10

0.20 REF.

0.70

MIN.

0.75 0.80

NOM.

40L 5x5MAX.

13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.

Documents

High-Speed, Step-Down Controller with Accurate Current ... · BATTERY 4.5V TO 28V OUTPUT 2.5V SHDN ILIM DL LX V+ BST DH CS OUT SKIP VDD MAX8764 UVP REF PGOOD LATCH OVP FB GND Minimal