1248 IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 11, NOVEMBER 2010

High-Performance and Stable TransparentHf–In–Zn–O Thin-Film Transistors With

a Double-Etch-Stopper LayerJoon Seok Park, Tae Sang Kim, Kyoung Seok Son, Kwang-Hee Lee, Ji Sim Jung, Wan-Joo Maeng, Hyun-Suk Kim,

Eok Su Kim, Kyung-Bae Park, Jong-Baek Seon, Jang-Yeon Kwon, Myung Kwan Ryu, and Sangyoon Lee

Abstract—Transparent hafnium indium zinc oxide thin-filmtransistors adopting single- and double-etch-stopper layers wereevaluated. Compared to devices with a single SiOx etch stopper(ES) grown at 150 ◦C, a double ES with a second SiOx film grownat 350 ◦C provides a superior device performance such as im-proved subthreshold swing, threshold voltage, field effect mobility,and higher stability under a negative bias stress. The stretched-exponential analyses of the bias stress results indicate that thedenser high-temperature SiOx protects more effectively the un-derlying semiconductor during the source/drain etch process andsuppresses the generation of defect states therein.

Index Terms—Etch stopper (ES), hafnium indium zinc oxide(HIZO), thin-film transistor (TFT).

I. INTRODUCTION

THIN-FILM transistors (TFTs) that incorporate oxidesemiconductors such as ZnO, GaInZnO, or HfInZnO

(HIZO) are nowadays drawing much attention owing to theirhigh potential for application in flat panel displays [1]–[6].Oxide-based TFTs are suitable switching elements for trans-parent active matrix liquid crystal display (AMLCD) or activematrix organic light-emitting diode (AMOLED) panels.

Most devices produced in the industry consist of the invertedstaggered bottom gate configuration. It is reported in previousstudies that the use of a SiOx etch stopper (ES) layer promotes ahigher device performance and superior stability since, in back-channel-etched devices, the active layer is directly exposedto the etchant during the source–drain metal etch process,and the associated contamination generates defect states inthe semiconductor bulk and/or at its interfaces [7], [8]. Theability of the final passivation layer to suppress the penetrationof external oxygen or moisture down to the underlying oxidesemiconductor is also a critical parameter that determines adevice’s stability under a bias stress. The device degradationby environmental effects is suggested to occur by the creation

Manuscript received July 27, 2010; accepted August 2, 2010. Date ofpublication September 7, 2010; date of current version October 22, 2010. Thereview of this letter was arranged by Editor J. K. O. Sin.

J. S. Park, T. S. Kim, K. S. Son, K.-H. Lee, W.-J. Maeng, H.-S. Kim,E. S. Kim, K.-B. Park, J.-B. Seon, M. K. Ryu, and S. Lee are with theDisplay Laboratory, Samsung Advanced Institute of Technology, Yongin 446-712, Korea.

J. S. Jung and J.-Y. Kwon are with the Materials Science and EngineeringDepartment, Seoul National University, Seoul 151-744, Korea.

Color versions of one or more of the figures in this letter are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2010.2065793

of defect levels in the oxide semiconductor, which results fromthe adsorption of oxygen or water-related molecules [9]–[11].

However, in this letter, the environmental effects are put asideby performing the measurements in a vacuum chamber, andmore emphasis is given to the quality of the ES layer in orderto examine how the latter can be grown to effectively protectthe active layer during the source–drain etch process. In thisletter, transparent HIZO TFTs that employ single- and double-ES systems involving SiOx films grown at different substratetemperatures are compared.

Since real operating TFT arrays in display products undergo,most of the time, a negative gate pulse bias that maintains theOFF state of the device, the device reliability must be ensuredunder such conditions in order to promote commercially viablepanels. Moreover, because TFTs in AMLCD or AMOLEDpanels are constantly exposed to a visible light emanating eitherfrom the AMLCD backlight unit or from the light-emittinglayer in the AMOLED modules, the device stability has to beevaluated under both a negative bias stress and illumination.

II. EXPERIMENTAL PROCEDURE

The devices were fabricated by first depositing a 200-nm-thick indium tin oxide (ITO) gate by electron beam evaporationonto 150 mm × 150 mm glass substrates and subsequentlygrowing a 400-nm-thick SiOx as the gate insulator by plasma-enhanced chemical vapor deposition (PECVD). A 40-nm-thickHIZO active layer was formed by radio-frequency sputtering.For the single-ES device, a 200-nm-thick SiOx ES layer wasdeposited by PECVD at a substrate temperature of 150 ◦C.For the double-ES device, a 100-nm-thick SiOx film was firstdeposited at 150 ◦C, and an additional 100-nm-thick SiOx

layer was grown at 350 ◦C so that a total ES thickness of200 nm was achieved. The 200-nm-thick indium zinc oxide(IZO) was sputtered and patterned by photolithography usinga proprietary mixture of nitric and acetic acid for 3 min to formthe source–drain electrodes. The aforementioned transistorswere then annealed in air for 1 h at 250 ◦C. The deviceswith channel width/length = 70/20 μm were characterized ina vacuum chamber equipped with a Keithley 4200-SCS pa-rameter analyzer. Fig. 1 shows the cross-sectional diagram ofthe double-ES device and how the measurements were done.A halogen lamp was used to provide visible radiation with aluminance of 200 lx during the negative bias stress experiments.

0741-3106/$26.00 © 2010 IEEE

PARK et al.: HIGH-PERFORMANCE AND STABLE TRANSPARENT Hf–In–Zn–O TFTS 1249

Fig. 1. Cross-sectional diagram of the transparent TFT and the measurementscheme with the presence of visible light provided by a halogen lamp.

TABLE IINITIAL TRANSFER CHARACTERISTICS OF THE DEVICES

For the latter, a gate voltage (V g) of −20 V and a drain voltage(V d) of 10 V were applied.

III. RESULTS AND DISCUSSIONS

The transfer curves were obtained for the single- and double-ES devices (see Fig. 1), and the initial parameters measured inthe dark are listed in Table I. The double-ES TFT exhibits asuperior field effect mobility and subthreshold swing and oper-ates closer to an enhancement mode. The S value is in generalassociated with the number of defects in the semiconductor bulk(Nbulk) and at the semiconductor/gate dielectric interface (Nit)by [12]

Ntot = Nbulk + Nit =(

S log10 e

kT/q− 1

)Cox

q(1)

where k is the Boltzmann’s constant, q is the charge of anelectron, and Cox is the capacitance of the gate insulator perunit area. The estimated total number of the bulk and interfacialdefects (Ntot) from the aforementioned equation is listed foreach type of device in Table I.

Upon a negative bias stress with the presence of visible lightradiation, the transfer curves shift in the negative direction, asindicated by the arrows in Fig. 2.

Fig. 3 shows the time evolution of VT with respect to stresstime. The results conform to the stretched-exponential equation,which reflects the device degradation by charge trapping at thesemiconductor/dielectric interface and is defined as [13]

|ΔVT | = |ΔVT0|(

1 − exp

{−

(t

τ

)β})

(2)

where ΔVT0 is the VT shift at an infinite time, β is thestretched-exponential exponent, and τ reflects the characteristic

Fig. 2. Initial transfer curves measured in the dark, and the degradation ofthe devices under negative bias stress with illumination are shown for the(a) single- and (b) double-ES devices.

Fig. 3. ΔVT -versus-stress time plots of the devices subjected to negative biasstress under illumination. Extended solid lines represent the calculated valuesin compliance with the stretched-exponential function.

TABLE IISTRETCHED-EXPONENTIAL PARAMETERS IN THE STRESSED DEVICES

trapping time of the carriers. The plots in Fig. 3 were fitted ac-cordingly as solid lines, and the extracted stretched-exponentialparameters are listed in Table II.

From the initial transfer parameters, it may be inferred thatthe device using a single-ES SiOx grown at 150 ◦C containsa higher number of defect states within the HIZO bulk and/orat the semiconductor/dielectric interface. The severe negativeshift in VT observed in the single-ES TFT is indicative ofmore abundant positive charge trapping at the HIZO/dielectricinterface. Because HIZO is an n-type semiconductor with ma-jority electron carriers, previous studies with the presence of avisible light report that photogenerated positive hole carriersare responsible for the negative VT shift [6]–[8]. Moreover,although the S values for both devices appear to vary inthe course of the bias stress experiment, this is due to thepresence of light-induced subthreshold photocurrents, and theS values before and after the negative bias stress measured inthe dark do not vary. This is a typical behavior of the devicedegradation by charge trapping at the semiconductor/dielectric

1250 IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 11, NOVEMBER 2010

interface and thus implies a higher density of trap sites at thesemiconductor/gate insulator interface in the single-ES TFT.

Because the experiments were carried out in a vacuumchamber with a pressure lower than 10−5 torr, it is reasonableto conclude that the previously mentioned degradation doesnot take place because of environmental effects. In order todirectly compare the influence of the etch process, another setof devices was prepared and dipped into the IZO etchant for10 min during the source–drain etch step. It was then observedthat the underlying active layer completely vanished in thesingle-ES device while the semiconductor remained intact inthe double-ES TFT. At this point, it can only be speculated that,once the etchant penetrates the low-temperature ES and attacksthe underlying HIZO, permanent damage may be induced,which can result in compositional disorder or the generationof undesired trap sites.

It is thus suggested that the use of a double ES that uses adenser SiOx film grown at 350 ◦C on top of the stack [14]is more effective at protecting the underlying HIZO semi-conductor in the course of the source–drain etching process;hence, fewer defect states are generated within the semiconduc-tor bulk and/or at the semiconductor/gate dielectric interface.X-ray reflectivity analyses showed that the low-temperatureSiOx has a density of 2.20 g/cm3 while that of the highertemperature SiOx is 2.26 g/cm3. In addition, the etch rate in6 : 1 buffered oxide etchant for the lower temperature SiOx isapproximately 10 nm/s while that for the higher temperatureSiOx is about 4 nm/s, which is indicative of a higher density inthe latter case.

When an ES layer that consists of the higher temperatureSiOx only is used, with a thickness equal to the double ES, theresulting devices exhibit conductor-like behavior. This phenom-enon is ascribed to the reduction of indium oxide by the incor-poration of hydrogen (originating from the SiH4 precursor usedin the SiOx growth) into the underlying HIZO at higher sub-strate temperatures. Similar behavior was previously observedin ITO thin films, where hydrogen plasma treatment resulted inthe segregation of metallic indium at high temperatures [15].

IV. CONCLUSION

In this letter, the performance and stability of transparentHIZO TFTs that incorporate single- and double-ES stacks havebeen evaluated. The latter has exhibited a superior field effectmobility and subthreshold swing and a higher stability upon anegative bias stress with the presence of a visible light. Sucha phenomenon is attributed to the effectiveness of the high-temperature SiOx on top of the double-ES stack at protecting

the semiconductor from damage during the source–drain etchprocess.

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