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SILICON SYSTEMS GROUP
Applied Centura® Avatar™ Etch Enabling New Dimensions in High Aspect Ratio Etching
Brad Howard
Head of Advanced Technology
Etch Business Unit
Silicon Systems Group
June 27, 2012
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SILICON SYSTEMS GROUP
0
5,000
10,000
15,000
20,000
25,000
30,000
35,000
40,000
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011E 2012F
Te
rab
yte
s
Flash Memory Phenomenon
2
Source: Gartner (March 2012)
512GB
NAND
iPhone® 64GB
NAND
NAND
Flash
DRAM
>75%
CAGR 2009-2014 (est.)
Where will these low-cost terabytes come from?
Incredible
cost/bit reduction
0.1
1
10
100
1000
150nm 100nm
Technology Node
60nm 50nm 40nm 20nm 1Ynm
$ per GB
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3D NAND – The Solution
20 years of success in 2D NAND
technology & manufacturing
Current 2D NAND scaling is approaching
technology limitation
Solution - vertically integrating a 2D NAND
cell string for a path beyond 1x
Concept published by Toshiba in 2007
Potentially scalable up to petabytes Cell Periphery
2D NAND
3D NAND
3 SILICON SYSTEMS GROUP
“…decreased number of stored electrons will impede further scaling of planar NAND…below
the 20nm equivalent technology node, 3D NAND flash will be the solution…”
Dr. Kinam Kim – EVP – Semiconductor R&D Center, Samsung Electronics
Electron Devices Meeting (IEDM), 2010 IEEE
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SILICON SYSTEMS GROUP
Visualizing the 3D NAND Concept
N N N N N N N N N N N
P
Ground
Select
Transistor
Word
Line 0
Word
Line 1
Word
Line 2
Word
Line 3
Word
Line 4
Word
Line 5
Word
Line 6
Word
Line 7
Ground
Select
Transistor
Bit Line
Start with a typical planar NAND cell string
(8 cell string shown)
4
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SILICON SYSTEMS GROUP
Visualizing the 3D NAND Concept
N N N N N N N N N N N
P
Stretch it out
5
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SILICON SYSTEMS GROUP
Visualizing the 3D NAND Concept
N N N N N
N N N N N
N
P
P
N
Fold it over
6
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SILICON SYSTEMS GROUP
Stand it up
N
N
N
N
N N
N
N
N
N
N
P P
N
7
Visualizing the 3D NAND Concept
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3D NAND Poses New Critical Etch Challenges
Sources: VLSI and IEDM publications
Arguably the most complex set of etch challenges ever
Gate Trench
Millions Per Die
Channel Hole
Billions Per Die
Staircase Contact (1,2)
Billions per Die
Cell Periphery
APF
Mask Open
SILICON SYSTEMS GROUP 8
32, 48, 64 Layers
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Mask Open Challenges
SILICON SYSTEMS GROUP 9
Mask open performance must be extremely high quality.
Any error in the mask profile will be magnified.
Photoresist
ARC
APF Mask
16-64 Pairs
Silicon
Each distinct HAR dielectric
etch needs its own mask
open
Highest aspect ratio ever for
mask open ~20:1
Faster etch rates required to
avoid throughput hit
Ability to etch mask and final
feature “all-in-one”
Mask Open Steps
Channel Hole
Staircase
Gate Trench
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SILICON SYSTEMS GROUP 10
Gate Trench Challenges
Etching tens of thousands sheets of paper
simultaneously – from the edge!
30:1 Vertical aspect ratio
- Narrowing affects cell-cell matching
50k:1 Horizontal aspect ratio
- Trench bending leads to memory cell
loss
Feature ~70nm W x ~3µm D x 100’s µm L
Alternating material pairs
- Ultimate control of chemistry required
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SILICON SYSTEMS GROUP 11
Channel Hole Challenges
Very high aspect ratio >60:1
Channel hole diameter ~40 - 50nm
Channel hole pitch ~80 - 100nm
Must land on tiny pad
- Vertical profile critical
Etch alternating oxide/nitride stack
- Source of bending
Need to maintain vertical geometry through as
many as 128 alternating material layers
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SILICON SYSTEMS GROUP 12
Staircase Contact Challenges
Staircase
Must create all staircase contacts at once to
avoid extra patterning steps
Wide range of aspect ratios
- 30:1 to >80:1
Contact diameter ~55 - 65nm
Contact pitch ~200nm
Must not punch through stop layer
- Critical for reliability
Extreme simultaneous multi-depth etch
control required
Must land on a very small step
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SILICON SYSTEMS GROUP 13
Today’s Etch Systems Cannot Meet these
Challenges
A breakthrough etch technology is required
Gate Trench Etch Degrades cell
reliability
Mask Open Impacts entire die
Staircase Etch Causes cell
cross talk
Channel Hole Etch Creates non-
functioning cells
Introducing the New
Applied Centura® Avatar™ Etch System Innovation in High Aspect Ratio Etch for the Next Generation
14
New benchmarks in high
aspect ratio etch – near vertical
profiles in multi-material stacks
Breakthrough simultaneous
multi-depth etch – key enabler
of staircase architecture
Speed: achieves extremely high
mask etch rate
Designed from the ground up to meet the challenges of 3D NAND
SILICON SYSTEMS GROUP External Use
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SILICON SYSTEMS GROUP
Mask Etch Performance
15
Stellar mask etch fidelity lays foundation for accurate
pattern transfer during the subsequent etch step
Current Technology
Smooth vertical profiles achieved
Extremely high etch rate is
enabled by unique plasma
source
Single chamber mask and final
feature etch demonstrated –
allows for maximum flexibility
Avatar
Mask Open Steps
Channel Hole
Staircase
Gate Trench
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SILICON SYSTEMS GROUP
Gate Trench Performance
16
Optimum integrity of trenches enables
memory cell performance
Current Technology Avatar
Achieves smooth vertical
sidewalls with no bending or
warping across the entire
length of the die
Smooth profile transitions
between alternating stack layers
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SILICON SYSTEMS GROUP 17
Channel Hole Performance
Vertical profiles enable consistent memory cell
performance across all layers
Near vertical profiles with no measurable distortion down to the landing pad
Smooth profile transitions
between alternating stack layers
– key to avoiding profile bending
The contact hole performance is enabled by proprietary multi-frequency bias power control
Current Technology Avatar
External Use
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SILICON SYSTEMS GROUP 18
Staircase Contact Etch Performance
First system able to achieve this level of performance
Achieved very high
selectivity – critical to
etching contacts to the
entire staircase all at once
Enabled by unique, closed-
loop, high capacity wafer
temperature control system
and precise in feature
polymer control
Applied Centura® Avatar™ Etch Innovation in High Aspect Ratio Etch for the Next Generation
19
Smooth vertical profiles achieved
High etch rates enabled by unique
plasma source
Demonstrated mask and final
feature etch in single chamber –
allows for maximum flexibility
SILICON SYSTEMS GROUP External Use
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